2 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
4 // The LLVM Compiler Infrastructure
6 // This file is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the Hexagon implementation of the TargetInstrInfo class.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
18 #include "HexagonRegisterInfo.h"
19 #include "MCTargetDesc/HexagonBaseInfo.h"
20 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
21 #include "llvm/Target/TargetFrameLowering.h"
22 #include "llvm/Target/TargetInstrInfo.h"
24 #define GET_INSTRINFO_HEADER
25 #include "HexagonGenInstrInfo.inc"
30 class HexagonSubtarget;
31 class HexagonInstrInfo : public HexagonGenInstrInfo {
32 virtual void anchor();
33 const HexagonRegisterInfo RI;
34 const HexagonSubtarget &Subtarget;
37 typedef unsigned Opcode_t;
39 explicit HexagonInstrInfo(HexagonSubtarget &ST);
41 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
42 /// such, whenever a client has an instance of instruction info, it should
43 /// always be able to get register info as well (through this method).
45 const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
47 /// isLoadFromStackSlot - If the specified machine instruction is a direct
48 /// load from a stack slot, return the virtual or physical register number of
49 /// the destination along with the FrameIndex of the loaded stack slot. If
50 /// not, return 0. This predicate must return 0 if the instruction has
51 /// any side effects other than loading from the stack slot.
52 unsigned isLoadFromStackSlot(const MachineInstr *MI,
53 int &FrameIndex) const override;
55 /// isStoreToStackSlot - If the specified machine instruction is a direct
56 /// store to a stack slot, return the virtual or physical register number of
57 /// the source reg along with the FrameIndex of the loaded stack slot. If
58 /// not, return 0. This predicate must return 0 if the instruction has
59 /// any side effects other than storing to the stack slot.
60 unsigned isStoreToStackSlot(const MachineInstr *MI,
61 int &FrameIndex) const override;
64 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
65 MachineBasicBlock *&FBB,
66 SmallVectorImpl<MachineOperand> &Cond,
67 bool AllowModify) const override;
69 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
72 MachineBasicBlock *FBB,
73 const SmallVectorImpl<MachineOperand> &Cond,
74 DebugLoc DL) const override;
76 bool analyzeCompare(const MachineInstr *MI,
77 unsigned &SrcReg, unsigned &SrcReg2,
78 int &Mask, int &Value) const override;
80 void copyPhysReg(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator I, DebugLoc DL,
82 unsigned DestReg, unsigned SrcReg,
83 bool KillSrc) const override;
85 void storeRegToStackSlot(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator MBBI,
87 unsigned SrcReg, bool isKill, int FrameIndex,
88 const TargetRegisterClass *RC,
89 const TargetRegisterInfo *TRI) const override;
91 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
92 SmallVectorImpl<MachineOperand> &Addr,
93 const TargetRegisterClass *RC,
94 SmallVectorImpl<MachineInstr*> &NewMIs) const;
96 void loadRegFromStackSlot(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator MBBI,
98 unsigned DestReg, int FrameIndex,
99 const TargetRegisterClass *RC,
100 const TargetRegisterInfo *TRI) const override;
102 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
103 SmallVectorImpl<MachineOperand> &Addr,
104 const TargetRegisterClass *RC,
105 SmallVectorImpl<MachineInstr*> &NewMIs) const;
107 /// expandPostRAPseudo - This function is called for all pseudo instructions
108 /// that remain after register allocation. Many pseudo instructions are
109 /// created to help register allocation. This is the place to convert them
110 /// into real instructions. The target can edit MI in place, or it can insert
111 /// new instructions and erase MI. The function should return true if
112 /// anything was changed.
113 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
115 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
116 ArrayRef<unsigned> Ops,
117 MachineBasicBlock::iterator InsertPt,
118 int FrameIndex) const override;
120 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
121 ArrayRef<unsigned> Ops,
122 MachineBasicBlock::iterator InsertPt,
123 MachineInstr *LoadMI) const override {
127 unsigned createVR(MachineFunction* MF, MVT VT) const;
129 bool isBranch(const MachineInstr *MI) const;
130 bool isPredicable(MachineInstr *MI) const override;
131 bool PredicateInstruction(MachineInstr *MI,
132 const SmallVectorImpl<MachineOperand> &Cond) const override;
134 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
135 unsigned ExtraPredCycles,
136 const BranchProbability &Probability) const override;
138 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
139 unsigned NumTCycles, unsigned ExtraTCycles,
140 MachineBasicBlock &FMBB,
141 unsigned NumFCycles, unsigned ExtraFCycles,
142 const BranchProbability &Probability) const override;
144 bool isPredicated(const MachineInstr *MI) const override;
145 bool isPredicated(unsigned Opcode) const;
146 bool isPredicatedTrue(const MachineInstr *MI) const;
147 bool isPredicatedTrue(unsigned Opcode) const;
148 bool isPredicatedNew(const MachineInstr *MI) const;
149 bool isPredicatedNew(unsigned Opcode) const;
150 bool DefinesPredicate(MachineInstr *MI,
151 std::vector<MachineOperand> &Pred) const override;
152 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
153 const SmallVectorImpl<MachineOperand> &Pred2) const override;
156 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
158 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
159 const BranchProbability &Probability) const override;
162 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
164 bool isSchedulingBoundary(const MachineInstr *MI,
165 const MachineBasicBlock *MBB,
166 const MachineFunction &MF) const override;
167 bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
168 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
169 bool isMemOp(const MachineInstr *MI) const;
170 bool isSpillPredRegOp(const MachineInstr *MI) const;
171 bool isU6_3Immediate(const int value) const;
172 bool isU6_2Immediate(const int value) const;
173 bool isU6_1Immediate(const int value) const;
174 bool isU6_0Immediate(const int value) const;
175 bool isS4_3Immediate(const int value) const;
176 bool isS4_2Immediate(const int value) const;
177 bool isS4_1Immediate(const int value) const;
178 bool isS4_0Immediate(const int value) const;
179 bool isS12_Immediate(const int value) const;
180 bool isU6_Immediate(const int value) const;
181 bool isS8_Immediate(const int value) const;
182 bool isS6_Immediate(const int value) const;
184 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
185 bool isConditionalTransfer(const MachineInstr* MI) const;
186 bool isConditionalALU32 (const MachineInstr* MI) const;
187 bool isConditionalLoad (const MachineInstr* MI) const;
188 bool isConditionalStore(const MachineInstr* MI) const;
189 bool isNewValueInst(const MachineInstr* MI) const;
190 bool isNewValue(const MachineInstr* MI) const;
191 bool isNewValue(Opcode_t Opcode) const;
192 bool isDotNewInst(const MachineInstr* MI) const;
193 int GetDotOldOp(const int opc) const;
194 int GetDotNewOp(const MachineInstr* MI) const;
195 int GetDotNewPredOp(MachineInstr *MI,
196 const MachineBranchProbabilityInfo
198 bool mayBeNewStore(const MachineInstr* MI) const;
199 bool isDeallocRet(const MachineInstr *MI) const;
200 unsigned getInvertedPredicatedOpcode(const int Opc) const;
201 bool isExtendable(const MachineInstr* MI) const;
202 bool isExtended(const MachineInstr* MI) const;
203 bool isPostIncrement(const MachineInstr* MI) const;
204 bool isNewValueStore(const MachineInstr* MI) const;
205 bool isNewValueStore(unsigned Opcode) const;
206 bool isNewValueJump(const MachineInstr* MI) const;
207 bool isNewValueJump(Opcode_t Opcode) const;
208 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
211 void immediateExtend(MachineInstr *MI) const;
212 bool isConstExtended(const MachineInstr *MI) const;
213 unsigned getSize(const MachineInstr *MI) const;
214 int getDotNewPredJumpOp(MachineInstr *MI,
215 const MachineBranchProbabilityInfo *MBPI) const;
216 unsigned getAddrMode(const MachineInstr* MI) const;
217 bool isOperandExtended(const MachineInstr *MI,
218 unsigned short OperandNum) const;
219 unsigned short getCExtOpNum(const MachineInstr *MI) const;
220 int getMinValue(const MachineInstr *MI) const;
221 int getMaxValue(const MachineInstr *MI) const;
222 bool NonExtEquivalentExists (const MachineInstr *MI) const;
223 short getNonExtOpcode(const MachineInstr *MI) const;
224 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
225 bool predOpcodeHasNot(const SmallVectorImpl<MachineOperand> &Cond) const;
226 bool isEndLoopN(Opcode_t Opcode) const;
227 bool getPredReg(const SmallVectorImpl<MachineOperand> &Cond,
228 unsigned &PredReg, unsigned &PredRegPos,
229 unsigned &PredRegFlags) const;
230 int getCondOpcode(int Opc, bool sense) const;