1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/MathExtras.h"
27 #define GET_INSTRINFO_CTOR
28 #include "HexagonGenInstrInfo.inc"
29 #include "HexagonGenDFAPacketizer.inc"
34 /// Constants for Hexagon instructions.
36 const int Hexagon_MEMW_OFFSET_MAX = 4095;
37 const int Hexagon_MEMW_OFFSET_MIN = 4096;
38 const int Hexagon_MEMD_OFFSET_MAX = 8191;
39 const int Hexagon_MEMD_OFFSET_MIN = 8192;
40 const int Hexagon_MEMH_OFFSET_MAX = 2047;
41 const int Hexagon_MEMH_OFFSET_MIN = 2048;
42 const int Hexagon_MEMB_OFFSET_MAX = 1023;
43 const int Hexagon_MEMB_OFFSET_MIN = 1024;
44 const int Hexagon_ADDI_OFFSET_MAX = 32767;
45 const int Hexagon_ADDI_OFFSET_MIN = 32768;
46 const int Hexagon_MEMD_AUTOINC_MAX = 56;
47 const int Hexagon_MEMD_AUTOINC_MIN = 64;
48 const int Hexagon_MEMW_AUTOINC_MAX = 28;
49 const int Hexagon_MEMW_AUTOINC_MIN = 32;
50 const int Hexagon_MEMH_AUTOINC_MAX = 14;
51 const int Hexagon_MEMH_AUTOINC_MIN = 16;
52 const int Hexagon_MEMB_AUTOINC_MAX = 7;
53 const int Hexagon_MEMB_AUTOINC_MIN = 8;
57 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59 RI(ST, *this), Subtarget(ST) {
63 /// isLoadFromStackSlot - If the specified machine instruction is a direct
64 /// load from a stack slot, return the virtual or physical register number of
65 /// the destination along with the FrameIndex of the loaded stack slot. If
66 /// not, return 0. This predicate must return 0 if the instruction has
67 /// any side effects other than loading from the stack slot.
68 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69 int &FrameIndex) const {
72 switch (MI->getOpcode()) {
78 if (MI->getOperand(2).isFI() &&
79 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
80 FrameIndex = MI->getOperand(2).getIndex();
81 return MI->getOperand(0).getReg();
93 /// isStoreToStackSlot - If the specified machine instruction is a direct
94 /// store to a stack slot, return the virtual or physical register number of
95 /// the source reg along with the FrameIndex of the loaded stack slot. If
96 /// not, return 0. This predicate must return 0 if the instruction has
97 /// any side effects other than storing to the stack slot.
98 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
99 int &FrameIndex) const {
100 switch (MI->getOpcode()) {
105 if (MI->getOperand(2).isFI() &&
106 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
107 FrameIndex = MI->getOperand(2).getIndex();
108 return MI->getOperand(0).getReg();
121 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
122 MachineBasicBlock *FBB,
123 const SmallVectorImpl<MachineOperand> &Cond,
126 int BOpc = Hexagon::JMP;
127 int BccOpc = Hexagon::JMP_c;
129 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
132 // Check if ReverseBranchCondition has asked to reverse this branch
133 // If we want to reverse the branch an odd number of times, we want
135 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
136 BccOpc = Hexagon::JMP_cNot;
142 // Due to a bug in TailMerging/CFG Optimization, we need to add a
143 // special case handling of a predicated jump followed by an
144 // unconditional jump. If not, Tail Merging and CFG Optimization go
145 // into an infinite loop.
146 MachineBasicBlock *NewTBB, *NewFBB;
147 SmallVector<MachineOperand, 4> Cond;
148 MachineInstr *Term = MBB.getFirstTerminator();
149 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
151 MachineBasicBlock *NextBB =
152 llvm::next(MachineFunction::iterator(&MBB));
153 if (NewTBB == NextBB) {
154 ReverseBranchCondition(Cond);
156 return InsertBranch(MBB, TBB, 0, Cond, DL);
159 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
162 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
167 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
168 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
174 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
175 MachineBasicBlock *&TBB,
176 MachineBasicBlock *&FBB,
177 SmallVectorImpl<MachineOperand> &Cond,
178 bool AllowModify) const {
181 // If the block has no terminators, it just falls into the block after it.
182 MachineBasicBlock::iterator I = MBB.end();
183 if (I == MBB.begin())
186 // A basic block may looks like this:
196 // It has two succs but does not have a terminator
197 // Don't know how to handle it.
202 } while (I != MBB.begin());
207 while (I->isDebugValue()) {
208 if (I == MBB.begin())
212 if (!isUnpredicatedTerminator(I))
215 // Get the last instruction in the block.
216 MachineInstr *LastInst = I;
218 // If there is only one terminator instruction, process it.
219 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
220 if (LastInst->getOpcode() == Hexagon::JMP) {
221 TBB = LastInst->getOperand(0).getMBB();
224 if (LastInst->getOpcode() == Hexagon::JMP_c) {
225 // Block ends with fall-through true condbranch.
226 TBB = LastInst->getOperand(1).getMBB();
227 Cond.push_back(LastInst->getOperand(0));
230 if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
231 // Block ends with fall-through false condbranch.
232 TBB = LastInst->getOperand(1).getMBB();
233 Cond.push_back(MachineOperand::CreateImm(0));
234 Cond.push_back(LastInst->getOperand(0));
237 // Otherwise, don't know what this is.
241 // Get the instruction before it if it's a terminator.
242 MachineInstr *SecondLastInst = I;
244 // If there are three terminators, we don't know what sort of block this is.
245 if (SecondLastInst && I != MBB.begin() &&
246 isUnpredicatedTerminator(--I))
249 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
250 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
251 (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
252 LastInst->getOpcode() == Hexagon::JMP) {
253 TBB = SecondLastInst->getOperand(1).getMBB();
254 Cond.push_back(SecondLastInst->getOperand(0));
255 FBB = LastInst->getOperand(0).getMBB();
259 // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
260 if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
261 LastInst->getOpcode() == Hexagon::JMP) {
262 TBB = SecondLastInst->getOperand(1).getMBB();
263 Cond.push_back(MachineOperand::CreateImm(0));
264 Cond.push_back(SecondLastInst->getOperand(0));
265 FBB = LastInst->getOperand(0).getMBB();
269 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
270 // executed, so remove it.
271 if (SecondLastInst->getOpcode() == Hexagon::JMP &&
272 LastInst->getOpcode() == Hexagon::JMP) {
273 TBB = SecondLastInst->getOperand(0).getMBB();
276 I->eraseFromParent();
280 // Otherwise, can't handle this.
285 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
286 int BOpc = Hexagon::JMP;
287 int BccOpc = Hexagon::JMP_c;
288 int BccOpcNot = Hexagon::JMP_cNot;
290 MachineBasicBlock::iterator I = MBB.end();
291 if (I == MBB.begin()) return 0;
293 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
294 I->getOpcode() != BccOpcNot)
297 // Remove the branch.
298 I->eraseFromParent();
302 if (I == MBB.begin()) return 1;
304 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
307 // Remove the branch.
308 I->eraseFromParent();
313 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
314 MachineBasicBlock::iterator I, DebugLoc DL,
315 unsigned DestReg, unsigned SrcReg,
316 bool KillSrc) const {
317 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
318 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
321 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
322 BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg);
325 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
326 // Map Pd = Ps to Pd = or(Ps, Ps).
327 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
328 DestReg).addReg(SrcReg).addReg(SrcReg);
331 if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) {
332 // We can have an overlap between single and double reg: r1:0 = r0.
333 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
335 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
336 Hexagon::subreg_hireg))).addImm(0);
338 // r1:0 = r1 or no overlap.
339 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
340 Hexagon::subreg_loreg))).addReg(SrcReg);
341 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
342 Hexagon::subreg_hireg))).addImm(0);
346 if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) {
347 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
351 llvm_unreachable("Unimplemented");
355 void HexagonInstrInfo::
356 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
357 unsigned SrcReg, bool isKill, int FI,
358 const TargetRegisterClass *RC,
359 const TargetRegisterInfo *TRI) const {
361 DebugLoc DL = MBB.findDebugLoc(I);
362 MachineFunction &MF = *MBB.getParent();
363 MachineFrameInfo &MFI = *MF.getFrameInfo();
364 unsigned Align = MFI.getObjectAlignment(FI);
366 MachineMemOperand *MMO =
367 MF.getMachineMemOperand(
368 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
369 MachineMemOperand::MOStore,
370 MFI.getObjectSize(FI),
373 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
374 BuildMI(MBB, I, DL, get(Hexagon::STriw))
375 .addFrameIndex(FI).addImm(0)
376 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
377 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
378 BuildMI(MBB, I, DL, get(Hexagon::STrid))
379 .addFrameIndex(FI).addImm(0)
380 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
381 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
382 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
383 .addFrameIndex(FI).addImm(0)
384 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
386 llvm_unreachable("Unimplemented");
391 void HexagonInstrInfo::storeRegToAddr(
392 MachineFunction &MF, unsigned SrcReg,
394 SmallVectorImpl<MachineOperand> &Addr,
395 const TargetRegisterClass *RC,
396 SmallVectorImpl<MachineInstr*> &NewMIs) const
398 llvm_unreachable("Unimplemented");
402 void HexagonInstrInfo::
403 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
404 unsigned DestReg, int FI,
405 const TargetRegisterClass *RC,
406 const TargetRegisterInfo *TRI) const {
407 DebugLoc DL = MBB.findDebugLoc(I);
408 MachineFunction &MF = *MBB.getParent();
409 MachineFrameInfo &MFI = *MF.getFrameInfo();
410 unsigned Align = MFI.getObjectAlignment(FI);
412 MachineMemOperand *MMO =
413 MF.getMachineMemOperand(
414 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
415 MachineMemOperand::MOLoad,
416 MFI.getObjectSize(FI),
419 if (RC == &Hexagon::IntRegsRegClass) {
420 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
421 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
422 } else if (RC == &Hexagon::DoubleRegsRegClass) {
423 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
424 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
425 } else if (RC == &Hexagon::PredRegsRegClass) {
426 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
427 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
429 llvm_unreachable("Can't store this register to stack slot");
434 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
435 SmallVectorImpl<MachineOperand> &Addr,
436 const TargetRegisterClass *RC,
437 SmallVectorImpl<MachineInstr*> &NewMIs) const {
438 llvm_unreachable("Unimplemented");
442 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
444 const SmallVectorImpl<unsigned> &Ops,
446 // Hexagon_TODO: Implement.
451 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
453 MachineRegisterInfo &RegInfo = MF->getRegInfo();
454 const TargetRegisterClass *TRC;
456 TRC = &Hexagon::PredRegsRegClass;
457 else if (VT == MVT::i32)
458 TRC = &Hexagon::IntRegsRegClass;
459 else if (VT == MVT::i64)
460 TRC = &Hexagon::DoubleRegsRegClass;
462 llvm_unreachable("Cannot handle this register class");
464 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
470 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
471 bool isPred = MI->getDesc().isPredicable();
476 const int Opc = MI->getOpcode();
480 return isInt<12>(MI->getOperand(1).getImm());
483 case Hexagon::STrid_indexed:
484 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
487 case Hexagon::STriw_indexed:
488 case Hexagon::STriw_nv_V4:
489 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
492 case Hexagon::STrih_indexed:
493 case Hexagon::STrih_nv_V4:
494 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
497 case Hexagon::STrib_indexed:
498 case Hexagon::STrib_nv_V4:
499 return isUInt<6>(MI->getOperand(1).getImm());
502 case Hexagon::LDrid_indexed:
503 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
506 case Hexagon::LDriw_indexed:
507 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
510 case Hexagon::LDriuh:
511 case Hexagon::LDrih_indexed:
512 case Hexagon::LDriuh_indexed:
513 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
516 case Hexagon::LDriub:
517 case Hexagon::LDrib_indexed:
518 case Hexagon::LDriub_indexed:
519 return isUInt<6>(MI->getOperand(2).getImm());
521 case Hexagon::POST_LDrid:
522 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
524 case Hexagon::POST_LDriw:
525 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
527 case Hexagon::POST_LDrih:
528 case Hexagon::POST_LDriuh:
529 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
531 case Hexagon::POST_LDrib:
532 case Hexagon::POST_LDriub:
533 return isInt<4>(MI->getOperand(3).getImm());
535 case Hexagon::STrib_imm_V4:
536 case Hexagon::STrih_imm_V4:
537 case Hexagon::STriw_imm_V4:
538 return (isUInt<6>(MI->getOperand(1).getImm()) &&
539 isInt<6>(MI->getOperand(2).getImm()));
541 case Hexagon::ADD_ri:
542 return isInt<8>(MI->getOperand(2).getImm());
550 return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
559 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
561 case Hexagon::TFR_cPt:
562 return Hexagon::TFR_cNotPt;
563 case Hexagon::TFR_cNotPt:
564 return Hexagon::TFR_cPt;
566 case Hexagon::TFRI_cPt:
567 return Hexagon::TFRI_cNotPt;
568 case Hexagon::TFRI_cNotPt:
569 return Hexagon::TFRI_cPt;
572 return Hexagon::JMP_cNot;
573 case Hexagon::JMP_cNot:
574 return Hexagon::JMP_c;
576 case Hexagon::ADD_ri_cPt:
577 return Hexagon::ADD_ri_cNotPt;
578 case Hexagon::ADD_ri_cNotPt:
579 return Hexagon::ADD_ri_cPt;
581 case Hexagon::ADD_rr_cPt:
582 return Hexagon::ADD_rr_cNotPt;
583 case Hexagon::ADD_rr_cNotPt:
584 return Hexagon::ADD_rr_cPt;
586 case Hexagon::XOR_rr_cPt:
587 return Hexagon::XOR_rr_cNotPt;
588 case Hexagon::XOR_rr_cNotPt:
589 return Hexagon::XOR_rr_cPt;
591 case Hexagon::AND_rr_cPt:
592 return Hexagon::AND_rr_cNotPt;
593 case Hexagon::AND_rr_cNotPt:
594 return Hexagon::AND_rr_cPt;
596 case Hexagon::OR_rr_cPt:
597 return Hexagon::OR_rr_cNotPt;
598 case Hexagon::OR_rr_cNotPt:
599 return Hexagon::OR_rr_cPt;
601 case Hexagon::SUB_rr_cPt:
602 return Hexagon::SUB_rr_cNotPt;
603 case Hexagon::SUB_rr_cNotPt:
604 return Hexagon::SUB_rr_cPt;
606 case Hexagon::COMBINE_rr_cPt:
607 return Hexagon::COMBINE_rr_cNotPt;
608 case Hexagon::COMBINE_rr_cNotPt:
609 return Hexagon::COMBINE_rr_cPt;
611 case Hexagon::ASLH_cPt_V4:
612 return Hexagon::ASLH_cNotPt_V4;
613 case Hexagon::ASLH_cNotPt_V4:
614 return Hexagon::ASLH_cPt_V4;
616 case Hexagon::ASRH_cPt_V4:
617 return Hexagon::ASRH_cNotPt_V4;
618 case Hexagon::ASRH_cNotPt_V4:
619 return Hexagon::ASRH_cPt_V4;
621 case Hexagon::SXTB_cPt_V4:
622 return Hexagon::SXTB_cNotPt_V4;
623 case Hexagon::SXTB_cNotPt_V4:
624 return Hexagon::SXTB_cPt_V4;
626 case Hexagon::SXTH_cPt_V4:
627 return Hexagon::SXTH_cNotPt_V4;
628 case Hexagon::SXTH_cNotPt_V4:
629 return Hexagon::SXTH_cPt_V4;
631 case Hexagon::ZXTB_cPt_V4:
632 return Hexagon::ZXTB_cNotPt_V4;
633 case Hexagon::ZXTB_cNotPt_V4:
634 return Hexagon::ZXTB_cPt_V4;
636 case Hexagon::ZXTH_cPt_V4:
637 return Hexagon::ZXTH_cNotPt_V4;
638 case Hexagon::ZXTH_cNotPt_V4:
639 return Hexagon::ZXTH_cPt_V4;
642 case Hexagon::JMPR_cPt:
643 return Hexagon::JMPR_cNotPt;
644 case Hexagon::JMPR_cNotPt:
645 return Hexagon::JMPR_cPt;
647 // V4 indexed+scaled load.
648 case Hexagon::LDrid_indexed_cPt_V4:
649 return Hexagon::LDrid_indexed_cNotPt_V4;
650 case Hexagon::LDrid_indexed_cNotPt_V4:
651 return Hexagon::LDrid_indexed_cPt_V4;
653 case Hexagon::LDrid_indexed_shl_cPt_V4:
654 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
655 case Hexagon::LDrid_indexed_shl_cNotPt_V4:
656 return Hexagon::LDrid_indexed_shl_cPt_V4;
658 case Hexagon::LDrib_indexed_cPt_V4:
659 return Hexagon::LDrib_indexed_cNotPt_V4;
660 case Hexagon::LDrib_indexed_cNotPt_V4:
661 return Hexagon::LDrib_indexed_cPt_V4;
663 case Hexagon::LDriub_indexed_cPt_V4:
664 return Hexagon::LDriub_indexed_cNotPt_V4;
665 case Hexagon::LDriub_indexed_cNotPt_V4:
666 return Hexagon::LDriub_indexed_cPt_V4;
668 case Hexagon::LDrib_indexed_shl_cPt_V4:
669 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
670 case Hexagon::LDrib_indexed_shl_cNotPt_V4:
671 return Hexagon::LDrib_indexed_shl_cPt_V4;
673 case Hexagon::LDriub_indexed_shl_cPt_V4:
674 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
675 case Hexagon::LDriub_indexed_shl_cNotPt_V4:
676 return Hexagon::LDriub_indexed_shl_cPt_V4;
678 case Hexagon::LDrih_indexed_cPt_V4:
679 return Hexagon::LDrih_indexed_cNotPt_V4;
680 case Hexagon::LDrih_indexed_cNotPt_V4:
681 return Hexagon::LDrih_indexed_cPt_V4;
683 case Hexagon::LDriuh_indexed_cPt_V4:
684 return Hexagon::LDriuh_indexed_cNotPt_V4;
685 case Hexagon::LDriuh_indexed_cNotPt_V4:
686 return Hexagon::LDriuh_indexed_cPt_V4;
688 case Hexagon::LDrih_indexed_shl_cPt_V4:
689 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
690 case Hexagon::LDrih_indexed_shl_cNotPt_V4:
691 return Hexagon::LDrih_indexed_shl_cPt_V4;
693 case Hexagon::LDriuh_indexed_shl_cPt_V4:
694 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
695 case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
696 return Hexagon::LDriuh_indexed_shl_cPt_V4;
698 case Hexagon::LDriw_indexed_cPt_V4:
699 return Hexagon::LDriw_indexed_cNotPt_V4;
700 case Hexagon::LDriw_indexed_cNotPt_V4:
701 return Hexagon::LDriw_indexed_cPt_V4;
703 case Hexagon::LDriw_indexed_shl_cPt_V4:
704 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
705 case Hexagon::LDriw_indexed_shl_cNotPt_V4:
706 return Hexagon::LDriw_indexed_shl_cPt_V4;
709 case Hexagon::POST_STbri_cPt:
710 return Hexagon::POST_STbri_cNotPt;
711 case Hexagon::POST_STbri_cNotPt:
712 return Hexagon::POST_STbri_cPt;
714 case Hexagon::STrib_cPt:
715 return Hexagon::STrib_cNotPt;
716 case Hexagon::STrib_cNotPt:
717 return Hexagon::STrib_cPt;
719 case Hexagon::STrib_indexed_cPt:
720 return Hexagon::STrib_indexed_cNotPt;
721 case Hexagon::STrib_indexed_cNotPt:
722 return Hexagon::STrib_indexed_cPt;
724 case Hexagon::STrib_imm_cPt_V4:
725 return Hexagon::STrib_imm_cNotPt_V4;
726 case Hexagon::STrib_imm_cNotPt_V4:
727 return Hexagon::STrib_imm_cPt_V4;
729 case Hexagon::STrib_indexed_shl_cPt_V4:
730 return Hexagon::STrib_indexed_shl_cNotPt_V4;
731 case Hexagon::STrib_indexed_shl_cNotPt_V4:
732 return Hexagon::STrib_indexed_shl_cPt_V4;
735 case Hexagon::POST_SThri_cPt:
736 return Hexagon::POST_SThri_cNotPt;
737 case Hexagon::POST_SThri_cNotPt:
738 return Hexagon::POST_SThri_cPt;
740 case Hexagon::STrih_cPt:
741 return Hexagon::STrih_cNotPt;
742 case Hexagon::STrih_cNotPt:
743 return Hexagon::STrih_cPt;
745 case Hexagon::STrih_indexed_cPt:
746 return Hexagon::STrih_indexed_cNotPt;
747 case Hexagon::STrih_indexed_cNotPt:
748 return Hexagon::STrih_indexed_cPt;
750 case Hexagon::STrih_imm_cPt_V4:
751 return Hexagon::STrih_imm_cNotPt_V4;
752 case Hexagon::STrih_imm_cNotPt_V4:
753 return Hexagon::STrih_imm_cPt_V4;
755 case Hexagon::STrih_indexed_shl_cPt_V4:
756 return Hexagon::STrih_indexed_shl_cNotPt_V4;
757 case Hexagon::STrih_indexed_shl_cNotPt_V4:
758 return Hexagon::STrih_indexed_shl_cPt_V4;
761 case Hexagon::POST_STwri_cPt:
762 return Hexagon::POST_STwri_cNotPt;
763 case Hexagon::POST_STwri_cNotPt:
764 return Hexagon::POST_STwri_cPt;
766 case Hexagon::STriw_cPt:
767 return Hexagon::STriw_cNotPt;
768 case Hexagon::STriw_cNotPt:
769 return Hexagon::STriw_cPt;
771 case Hexagon::STriw_indexed_cPt:
772 return Hexagon::STriw_indexed_cNotPt;
773 case Hexagon::STriw_indexed_cNotPt:
774 return Hexagon::STriw_indexed_cPt;
776 case Hexagon::STriw_indexed_shl_cPt_V4:
777 return Hexagon::STriw_indexed_shl_cNotPt_V4;
778 case Hexagon::STriw_indexed_shl_cNotPt_V4:
779 return Hexagon::STriw_indexed_shl_cPt_V4;
781 case Hexagon::STriw_imm_cPt_V4:
782 return Hexagon::STriw_imm_cNotPt_V4;
783 case Hexagon::STriw_imm_cNotPt_V4:
784 return Hexagon::STriw_imm_cPt_V4;
787 case Hexagon::POST_STdri_cPt:
788 return Hexagon::POST_STdri_cNotPt;
789 case Hexagon::POST_STdri_cNotPt:
790 return Hexagon::POST_STdri_cPt;
792 case Hexagon::STrid_cPt:
793 return Hexagon::STrid_cNotPt;
794 case Hexagon::STrid_cNotPt:
795 return Hexagon::STrid_cPt;
797 case Hexagon::STrid_indexed_cPt:
798 return Hexagon::STrid_indexed_cNotPt;
799 case Hexagon::STrid_indexed_cNotPt:
800 return Hexagon::STrid_indexed_cPt;
802 case Hexagon::STrid_indexed_shl_cPt_V4:
803 return Hexagon::STrid_indexed_shl_cNotPt_V4;
804 case Hexagon::STrid_indexed_shl_cNotPt_V4:
805 return Hexagon::STrid_indexed_shl_cPt_V4;
808 case Hexagon::LDrid_cPt:
809 return Hexagon::LDrid_cNotPt;
810 case Hexagon::LDrid_cNotPt:
811 return Hexagon::LDrid_cPt;
813 case Hexagon::LDriw_cPt:
814 return Hexagon::LDriw_cNotPt;
815 case Hexagon::LDriw_cNotPt:
816 return Hexagon::LDriw_cPt;
818 case Hexagon::LDrih_cPt:
819 return Hexagon::LDrih_cNotPt;
820 case Hexagon::LDrih_cNotPt:
821 return Hexagon::LDrih_cPt;
823 case Hexagon::LDriuh_cPt:
824 return Hexagon::LDriuh_cNotPt;
825 case Hexagon::LDriuh_cNotPt:
826 return Hexagon::LDriuh_cPt;
828 case Hexagon::LDrib_cPt:
829 return Hexagon::LDrib_cNotPt;
830 case Hexagon::LDrib_cNotPt:
831 return Hexagon::LDrib_cPt;
833 case Hexagon::LDriub_cPt:
834 return Hexagon::LDriub_cNotPt;
835 case Hexagon::LDriub_cNotPt:
836 return Hexagon::LDriub_cPt;
839 case Hexagon::LDrid_indexed_cPt:
840 return Hexagon::LDrid_indexed_cNotPt;
841 case Hexagon::LDrid_indexed_cNotPt:
842 return Hexagon::LDrid_indexed_cPt;
844 case Hexagon::LDriw_indexed_cPt:
845 return Hexagon::LDriw_indexed_cNotPt;
846 case Hexagon::LDriw_indexed_cNotPt:
847 return Hexagon::LDriw_indexed_cPt;
849 case Hexagon::LDrih_indexed_cPt:
850 return Hexagon::LDrih_indexed_cNotPt;
851 case Hexagon::LDrih_indexed_cNotPt:
852 return Hexagon::LDrih_indexed_cPt;
854 case Hexagon::LDriuh_indexed_cPt:
855 return Hexagon::LDriuh_indexed_cNotPt;
856 case Hexagon::LDriuh_indexed_cNotPt:
857 return Hexagon::LDriuh_indexed_cPt;
859 case Hexagon::LDrib_indexed_cPt:
860 return Hexagon::LDrib_indexed_cNotPt;
861 case Hexagon::LDrib_indexed_cNotPt:
862 return Hexagon::LDrib_indexed_cPt;
864 case Hexagon::LDriub_indexed_cPt:
865 return Hexagon::LDriub_indexed_cNotPt;
866 case Hexagon::LDriub_indexed_cNotPt:
867 return Hexagon::LDriub_indexed_cPt;
870 case Hexagon::POST_LDrid_cPt:
871 return Hexagon::POST_LDrid_cNotPt;
872 case Hexagon::POST_LDriw_cNotPt:
873 return Hexagon::POST_LDriw_cPt;
875 case Hexagon::POST_LDrih_cPt:
876 return Hexagon::POST_LDrih_cNotPt;
877 case Hexagon::POST_LDrih_cNotPt:
878 return Hexagon::POST_LDrih_cPt;
880 case Hexagon::POST_LDriuh_cPt:
881 return Hexagon::POST_LDriuh_cNotPt;
882 case Hexagon::POST_LDriuh_cNotPt:
883 return Hexagon::POST_LDriuh_cPt;
885 case Hexagon::POST_LDrib_cPt:
886 return Hexagon::POST_LDrib_cNotPt;
887 case Hexagon::POST_LDrib_cNotPt:
888 return Hexagon::POST_LDrib_cPt;
890 case Hexagon::POST_LDriub_cPt:
891 return Hexagon::POST_LDriub_cNotPt;
892 case Hexagon::POST_LDriub_cNotPt:
893 return Hexagon::POST_LDriub_cPt;
896 case Hexagon::DEALLOC_RET_cPt_V4:
897 return Hexagon::DEALLOC_RET_cNotPt_V4;
898 case Hexagon::DEALLOC_RET_cNotPt_V4:
899 return Hexagon::DEALLOC_RET_cPt_V4;
902 // JMPEQ_ri - with -1.
903 case Hexagon::JMP_EQriPtneg_nv_V4:
904 return Hexagon::JMP_EQriNotPtneg_nv_V4;
905 case Hexagon::JMP_EQriNotPtneg_nv_V4:
906 return Hexagon::JMP_EQriPtneg_nv_V4;
908 case Hexagon::JMP_EQriPntneg_nv_V4:
909 return Hexagon::JMP_EQriNotPntneg_nv_V4;
910 case Hexagon::JMP_EQriNotPntneg_nv_V4:
911 return Hexagon::JMP_EQriPntneg_nv_V4;
914 case Hexagon::JMP_EQriPt_nv_V4:
915 return Hexagon::JMP_EQriNotPt_nv_V4;
916 case Hexagon::JMP_EQriNotPt_nv_V4:
917 return Hexagon::JMP_EQriPt_nv_V4;
919 case Hexagon::JMP_EQriPnt_nv_V4:
920 return Hexagon::JMP_EQriNotPnt_nv_V4;
921 case Hexagon::JMP_EQriNotPnt_nv_V4:
922 return Hexagon::JMP_EQriPnt_nv_V4;
925 case Hexagon::JMP_EQrrPt_nv_V4:
926 return Hexagon::JMP_EQrrNotPt_nv_V4;
927 case Hexagon::JMP_EQrrNotPt_nv_V4:
928 return Hexagon::JMP_EQrrPt_nv_V4;
930 case Hexagon::JMP_EQrrPnt_nv_V4:
931 return Hexagon::JMP_EQrrNotPnt_nv_V4;
932 case Hexagon::JMP_EQrrNotPnt_nv_V4:
933 return Hexagon::JMP_EQrrPnt_nv_V4;
935 // JMPGT_ri - with -1.
936 case Hexagon::JMP_GTriPtneg_nv_V4:
937 return Hexagon::JMP_GTriNotPtneg_nv_V4;
938 case Hexagon::JMP_GTriNotPtneg_nv_V4:
939 return Hexagon::JMP_GTriPtneg_nv_V4;
941 case Hexagon::JMP_GTriPntneg_nv_V4:
942 return Hexagon::JMP_GTriNotPntneg_nv_V4;
943 case Hexagon::JMP_GTriNotPntneg_nv_V4:
944 return Hexagon::JMP_GTriPntneg_nv_V4;
947 case Hexagon::JMP_GTriPt_nv_V4:
948 return Hexagon::JMP_GTriNotPt_nv_V4;
949 case Hexagon::JMP_GTriNotPt_nv_V4:
950 return Hexagon::JMP_GTriPt_nv_V4;
952 case Hexagon::JMP_GTriPnt_nv_V4:
953 return Hexagon::JMP_GTriNotPnt_nv_V4;
954 case Hexagon::JMP_GTriNotPnt_nv_V4:
955 return Hexagon::JMP_GTriPnt_nv_V4;
958 case Hexagon::JMP_GTrrPt_nv_V4:
959 return Hexagon::JMP_GTrrNotPt_nv_V4;
960 case Hexagon::JMP_GTrrNotPt_nv_V4:
961 return Hexagon::JMP_GTrrPt_nv_V4;
963 case Hexagon::JMP_GTrrPnt_nv_V4:
964 return Hexagon::JMP_GTrrNotPnt_nv_V4;
965 case Hexagon::JMP_GTrrNotPnt_nv_V4:
966 return Hexagon::JMP_GTrrPnt_nv_V4;
969 case Hexagon::JMP_GTrrdnPt_nv_V4:
970 return Hexagon::JMP_GTrrdnNotPt_nv_V4;
971 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
972 return Hexagon::JMP_GTrrdnPt_nv_V4;
974 case Hexagon::JMP_GTrrdnPnt_nv_V4:
975 return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
976 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
977 return Hexagon::JMP_GTrrdnPnt_nv_V4;
980 case Hexagon::JMP_GTUriPt_nv_V4:
981 return Hexagon::JMP_GTUriNotPt_nv_V4;
982 case Hexagon::JMP_GTUriNotPt_nv_V4:
983 return Hexagon::JMP_GTUriPt_nv_V4;
985 case Hexagon::JMP_GTUriPnt_nv_V4:
986 return Hexagon::JMP_GTUriNotPnt_nv_V4;
987 case Hexagon::JMP_GTUriNotPnt_nv_V4:
988 return Hexagon::JMP_GTUriPnt_nv_V4;
991 case Hexagon::JMP_GTUrrPt_nv_V4:
992 return Hexagon::JMP_GTUrrNotPt_nv_V4;
993 case Hexagon::JMP_GTUrrNotPt_nv_V4:
994 return Hexagon::JMP_GTUrrPt_nv_V4;
996 case Hexagon::JMP_GTUrrPnt_nv_V4:
997 return Hexagon::JMP_GTUrrNotPnt_nv_V4;
998 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
999 return Hexagon::JMP_GTUrrPnt_nv_V4;
1002 case Hexagon::JMP_GTUrrdnPt_nv_V4:
1003 return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1004 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1005 return Hexagon::JMP_GTUrrdnPt_nv_V4;
1007 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1008 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1009 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1010 return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1013 llvm_unreachable("Unexpected predicated instruction");
1018 int HexagonInstrInfo::
1019 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1022 return !invertPredicate ? Hexagon::TFR_cPt :
1023 Hexagon::TFR_cNotPt;
1025 return !invertPredicate ? Hexagon::TFRI_cPt :
1026 Hexagon::TFRI_cNotPt;
1028 return !invertPredicate ? Hexagon::JMP_c :
1030 case Hexagon::ADD_ri:
1031 return !invertPredicate ? Hexagon::ADD_ri_cPt :
1032 Hexagon::ADD_ri_cNotPt;
1033 case Hexagon::ADD_rr:
1034 return !invertPredicate ? Hexagon::ADD_rr_cPt :
1035 Hexagon::ADD_rr_cNotPt;
1036 case Hexagon::XOR_rr:
1037 return !invertPredicate ? Hexagon::XOR_rr_cPt :
1038 Hexagon::XOR_rr_cNotPt;
1039 case Hexagon::AND_rr:
1040 return !invertPredicate ? Hexagon::AND_rr_cPt :
1041 Hexagon::AND_rr_cNotPt;
1042 case Hexagon::OR_rr:
1043 return !invertPredicate ? Hexagon::OR_rr_cPt :
1044 Hexagon::OR_rr_cNotPt;
1045 case Hexagon::SUB_rr:
1046 return !invertPredicate ? Hexagon::SUB_rr_cPt :
1047 Hexagon::SUB_rr_cNotPt;
1048 case Hexagon::COMBINE_rr:
1049 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1050 Hexagon::COMBINE_rr_cNotPt;
1052 return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1053 Hexagon::ASLH_cNotPt_V4;
1055 return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1056 Hexagon::ASRH_cNotPt_V4;
1058 return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1059 Hexagon::SXTB_cNotPt_V4;
1061 return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1062 Hexagon::SXTH_cNotPt_V4;
1064 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1065 Hexagon::ZXTB_cNotPt_V4;
1067 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1068 Hexagon::ZXTH_cNotPt_V4;
1071 return !invertPredicate ? Hexagon::JMPR_cPt :
1072 Hexagon::JMPR_cNotPt;
1074 // V4 indexed+scaled load.
1075 case Hexagon::LDrid_indexed_V4:
1076 return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 :
1077 Hexagon::LDrid_indexed_cNotPt_V4;
1078 case Hexagon::LDrid_indexed_shl_V4:
1079 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1080 Hexagon::LDrid_indexed_shl_cNotPt_V4;
1081 case Hexagon::LDrib_indexed_V4:
1082 return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 :
1083 Hexagon::LDrib_indexed_cNotPt_V4;
1084 case Hexagon::LDriub_indexed_V4:
1085 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1086 Hexagon::LDriub_indexed_cNotPt_V4;
1087 case Hexagon::LDriub_ae_indexed_V4:
1088 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1089 Hexagon::LDriub_indexed_cNotPt_V4;
1090 case Hexagon::LDrib_indexed_shl_V4:
1091 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1092 Hexagon::LDrib_indexed_shl_cNotPt_V4;
1093 case Hexagon::LDriub_indexed_shl_V4:
1094 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1095 Hexagon::LDriub_indexed_shl_cNotPt_V4;
1096 case Hexagon::LDriub_ae_indexed_shl_V4:
1097 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1098 Hexagon::LDriub_indexed_shl_cNotPt_V4;
1099 case Hexagon::LDrih_indexed_V4:
1100 return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 :
1101 Hexagon::LDrih_indexed_cNotPt_V4;
1102 case Hexagon::LDriuh_indexed_V4:
1103 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1104 Hexagon::LDriuh_indexed_cNotPt_V4;
1105 case Hexagon::LDriuh_ae_indexed_V4:
1106 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1107 Hexagon::LDriuh_indexed_cNotPt_V4;
1108 case Hexagon::LDrih_indexed_shl_V4:
1109 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1110 Hexagon::LDrih_indexed_shl_cNotPt_V4;
1111 case Hexagon::LDriuh_indexed_shl_V4:
1112 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1113 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1114 case Hexagon::LDriuh_ae_indexed_shl_V4:
1115 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1116 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1117 case Hexagon::LDriw_indexed_V4:
1118 return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 :
1119 Hexagon::LDriw_indexed_cNotPt_V4;
1120 case Hexagon::LDriw_indexed_shl_V4:
1121 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
1122 Hexagon::LDriw_indexed_shl_cNotPt_V4;
1124 case Hexagon::POST_STbri:
1125 return !invertPredicate ? Hexagon::POST_STbri_cPt :
1126 Hexagon::POST_STbri_cNotPt;
1127 case Hexagon::STrib:
1128 return !invertPredicate ? Hexagon::STrib_cPt :
1129 Hexagon::STrib_cNotPt;
1130 case Hexagon::STrib_indexed:
1131 return !invertPredicate ? Hexagon::STrib_indexed_cPt :
1132 Hexagon::STrib_indexed_cNotPt;
1133 case Hexagon::STrib_imm_V4:
1134 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
1135 Hexagon::STrib_imm_cNotPt_V4;
1136 case Hexagon::STrib_indexed_shl_V4:
1137 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
1138 Hexagon::STrib_indexed_shl_cNotPt_V4;
1140 case Hexagon::POST_SThri:
1141 return !invertPredicate ? Hexagon::POST_SThri_cPt :
1142 Hexagon::POST_SThri_cNotPt;
1143 case Hexagon::STrih:
1144 return !invertPredicate ? Hexagon::STrih_cPt :
1145 Hexagon::STrih_cNotPt;
1146 case Hexagon::STrih_indexed:
1147 return !invertPredicate ? Hexagon::STrih_indexed_cPt :
1148 Hexagon::STrih_indexed_cNotPt;
1149 case Hexagon::STrih_imm_V4:
1150 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
1151 Hexagon::STrih_imm_cNotPt_V4;
1152 case Hexagon::STrih_indexed_shl_V4:
1153 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
1154 Hexagon::STrih_indexed_shl_cNotPt_V4;
1156 case Hexagon::POST_STwri:
1157 return !invertPredicate ? Hexagon::POST_STwri_cPt :
1158 Hexagon::POST_STwri_cNotPt;
1159 case Hexagon::STriw:
1160 return !invertPredicate ? Hexagon::STriw_cPt :
1161 Hexagon::STriw_cNotPt;
1162 case Hexagon::STriw_indexed:
1163 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
1164 Hexagon::STriw_indexed_cNotPt;
1165 case Hexagon::STriw_indexed_shl_V4:
1166 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
1167 Hexagon::STriw_indexed_shl_cNotPt_V4;
1168 case Hexagon::STriw_imm_V4:
1169 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
1170 Hexagon::STriw_imm_cNotPt_V4;
1172 case Hexagon::POST_STdri:
1173 return !invertPredicate ? Hexagon::POST_STdri_cPt :
1174 Hexagon::POST_STdri_cNotPt;
1175 case Hexagon::STrid:
1176 return !invertPredicate ? Hexagon::STrid_cPt :
1177 Hexagon::STrid_cNotPt;
1178 case Hexagon::STrid_indexed:
1179 return !invertPredicate ? Hexagon::STrid_indexed_cPt :
1180 Hexagon::STrid_indexed_cNotPt;
1181 case Hexagon::STrid_indexed_shl_V4:
1182 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
1183 Hexagon::STrid_indexed_shl_cNotPt_V4;
1185 case Hexagon::LDrid:
1186 return !invertPredicate ? Hexagon::LDrid_cPt :
1187 Hexagon::LDrid_cNotPt;
1188 case Hexagon::LDriw:
1189 return !invertPredicate ? Hexagon::LDriw_cPt :
1190 Hexagon::LDriw_cNotPt;
1191 case Hexagon::LDrih:
1192 return !invertPredicate ? Hexagon::LDrih_cPt :
1193 Hexagon::LDrih_cNotPt;
1194 case Hexagon::LDriuh:
1195 return !invertPredicate ? Hexagon::LDriuh_cPt :
1196 Hexagon::LDriuh_cNotPt;
1197 case Hexagon::LDrib:
1198 return !invertPredicate ? Hexagon::LDrib_cPt :
1199 Hexagon::LDrib_cNotPt;
1200 case Hexagon::LDriub:
1201 return !invertPredicate ? Hexagon::LDriub_cPt :
1202 Hexagon::LDriub_cNotPt;
1204 case Hexagon::LDrid_indexed:
1205 return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
1206 Hexagon::LDrid_indexed_cNotPt;
1207 case Hexagon::LDriw_indexed:
1208 return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
1209 Hexagon::LDriw_indexed_cNotPt;
1210 case Hexagon::LDrih_indexed:
1211 return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
1212 Hexagon::LDrih_indexed_cNotPt;
1213 case Hexagon::LDriuh_indexed:
1214 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
1215 Hexagon::LDriuh_indexed_cNotPt;
1216 case Hexagon::LDrib_indexed:
1217 return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
1218 Hexagon::LDrib_indexed_cNotPt;
1219 case Hexagon::LDriub_indexed:
1220 return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
1221 Hexagon::LDriub_indexed_cNotPt;
1222 // Post Increment Load.
1223 case Hexagon::POST_LDrid:
1224 return !invertPredicate ? Hexagon::POST_LDrid_cPt :
1225 Hexagon::POST_LDrid_cNotPt;
1226 case Hexagon::POST_LDriw:
1227 return !invertPredicate ? Hexagon::POST_LDriw_cPt :
1228 Hexagon::POST_LDriw_cNotPt;
1229 case Hexagon::POST_LDrih:
1230 return !invertPredicate ? Hexagon::POST_LDrih_cPt :
1231 Hexagon::POST_LDrih_cNotPt;
1232 case Hexagon::POST_LDriuh:
1233 return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
1234 Hexagon::POST_LDriuh_cNotPt;
1235 case Hexagon::POST_LDrib:
1236 return !invertPredicate ? Hexagon::POST_LDrib_cPt :
1237 Hexagon::POST_LDrib_cNotPt;
1238 case Hexagon::POST_LDriub:
1239 return !invertPredicate ? Hexagon::POST_LDriub_cPt :
1240 Hexagon::POST_LDriub_cNotPt;
1242 case Hexagon::DEALLOC_RET_V4:
1243 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
1244 Hexagon::DEALLOC_RET_cNotPt_V4;
1246 llvm_unreachable("Unexpected predicable instruction");
1250 bool HexagonInstrInfo::
1251 PredicateInstruction(MachineInstr *MI,
1252 const SmallVectorImpl<MachineOperand> &Cond) const {
1253 int Opc = MI->getOpcode();
1254 assert (isPredicable(MI) && "Expected predicable instruction");
1255 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
1256 (Cond[0].getImm() == 0));
1257 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
1259 // This assumes that the predicate is always the first operand
1260 // in the set of inputs.
1262 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
1264 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) {
1265 MachineOperand MO = MI->getOperand(oper);
1266 if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) {
1271 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
1272 MO.isImplicit(), MO.isKill(),
1273 MO.isDead(), MO.isUndef(),
1275 } else if (MO.isImm()) {
1276 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
1278 llvm_unreachable("Unexpected operand type");
1282 int regPos = invertJump ? 1 : 0;
1283 MachineOperand PredMO = Cond[regPos];
1284 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
1285 PredMO.isImplicit(), PredMO.isKill(),
1286 PredMO.isDead(), PredMO.isUndef(),
1295 isProfitableToIfCvt(MachineBasicBlock &MBB,
1297 unsigned ExtraPredCycles,
1298 const BranchProbability &Probability) const {
1305 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1306 unsigned NumTCycles,
1307 unsigned ExtraTCycles,
1308 MachineBasicBlock &FMBB,
1309 unsigned NumFCycles,
1310 unsigned ExtraFCycles,
1311 const BranchProbability &Probability) const {
1316 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1317 const uint64_t F = MI->getDesc().TSFlags;
1319 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1324 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1325 std::vector<MachineOperand> &Pred) const {
1326 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1327 MachineOperand MO = MI->getOperand(oper);
1328 if (MO.isReg() && MO.isDef()) {
1329 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1330 if (RC == &Hexagon::PredRegsRegClass) {
1342 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1343 const SmallVectorImpl<MachineOperand> &Pred2) const {
1350 // We indicate that we want to reverse the branch by
1351 // inserting a 0 at the beginning of the Cond vector.
1353 bool HexagonInstrInfo::
1354 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1355 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1356 Cond.erase(Cond.begin());
1358 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1364 bool HexagonInstrInfo::
1365 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1366 const BranchProbability &Probability) const {
1367 return (NumInstrs <= 4);
1370 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1371 switch (MI->getOpcode()) {
1372 case Hexagon::DEALLOC_RET_V4 :
1373 case Hexagon::DEALLOC_RET_cPt_V4 :
1374 case Hexagon::DEALLOC_RET_cNotPt_V4 :
1375 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
1376 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
1377 case Hexagon::DEALLOC_RET_cdnPt_V4 :
1378 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
1385 bool HexagonInstrInfo::
1386 isValidOffset(const int Opcode, const int Offset) const {
1387 // This function is to check whether the "Offset" is in the correct range of
1388 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1389 // inserted to calculate the final address. Due to this reason, the function
1390 // assumes that the "Offset" has correct alignment.
1394 case Hexagon::LDriw:
1395 case Hexagon::STriw:
1396 assert((Offset % 4 == 0) && "Offset has incorrect alignment");
1397 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1398 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1400 case Hexagon::LDrid:
1401 case Hexagon::STrid:
1402 assert((Offset % 8 == 0) && "Offset has incorrect alignment");
1403 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1404 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1406 case Hexagon::LDrih:
1407 case Hexagon::LDriuh:
1408 case Hexagon::STrih:
1409 assert((Offset % 2 == 0) && "Offset has incorrect alignment");
1410 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1411 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1413 case Hexagon::LDrib:
1414 case Hexagon::STrib:
1415 case Hexagon::LDriub:
1416 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1417 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1419 case Hexagon::ADD_ri:
1420 case Hexagon::TFR_FI:
1421 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1422 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1424 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
1425 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
1426 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
1427 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
1428 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
1429 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
1430 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
1431 case Hexagon::MEMw_ADDSUBi_MEM_V4 :
1432 case Hexagon::MEMw_ADDi_MEM_V4 :
1433 case Hexagon::MEMw_SUBi_MEM_V4 :
1434 case Hexagon::MEMw_ADDr_MEM_V4 :
1435 case Hexagon::MEMw_SUBr_MEM_V4 :
1436 case Hexagon::MEMw_ANDr_MEM_V4 :
1437 case Hexagon::MEMw_ORr_MEM_V4 :
1438 assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
1439 return (0 <= Offset && Offset <= 255);
1441 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
1442 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
1443 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
1444 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
1445 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
1446 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
1447 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
1448 case Hexagon::MEMh_ADDSUBi_MEM_V4 :
1449 case Hexagon::MEMh_ADDi_MEM_V4 :
1450 case Hexagon::MEMh_SUBi_MEM_V4 :
1451 case Hexagon::MEMh_ADDr_MEM_V4 :
1452 case Hexagon::MEMh_SUBr_MEM_V4 :
1453 case Hexagon::MEMh_ANDr_MEM_V4 :
1454 case Hexagon::MEMh_ORr_MEM_V4 :
1455 assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
1456 return (0 <= Offset && Offset <= 127);
1458 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
1459 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
1460 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
1461 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
1462 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
1463 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
1464 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
1465 case Hexagon::MEMb_ADDSUBi_MEM_V4 :
1466 case Hexagon::MEMb_ADDi_MEM_V4 :
1467 case Hexagon::MEMb_SUBi_MEM_V4 :
1468 case Hexagon::MEMb_ADDr_MEM_V4 :
1469 case Hexagon::MEMb_SUBr_MEM_V4 :
1470 case Hexagon::MEMb_ANDr_MEM_V4 :
1471 case Hexagon::MEMb_ORr_MEM_V4 :
1472 return (0 <= Offset && Offset <= 63);
1474 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1475 // any size. Later pass knows how to handle it.
1476 case Hexagon::STriw_pred:
1477 case Hexagon::LDriw_pred:
1480 // INLINEASM is very special.
1481 case Hexagon::INLINEASM:
1485 llvm_unreachable("No offset range is defined for this opcode. "
1486 "Please define it in the above switch statement!");
1491 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1493 bool HexagonInstrInfo::
1494 isValidAutoIncImm(const EVT VT, const int Offset) const {
1496 if (VT == MVT::i64) {
1497 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1498 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1499 (Offset & 0x7) == 0);
1501 if (VT == MVT::i32) {
1502 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1503 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1504 (Offset & 0x3) == 0);
1506 if (VT == MVT::i16) {
1507 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1508 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1509 (Offset & 0x1) == 0);
1511 if (VT == MVT::i8) {
1512 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1513 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1515 llvm_unreachable("Not an auto-inc opc!");
1519 bool HexagonInstrInfo::
1520 isMemOp(const MachineInstr *MI) const {
1521 switch (MI->getOpcode())
1523 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
1524 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
1525 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
1526 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
1527 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
1528 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
1529 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
1530 case Hexagon::MEMw_ADDSUBi_MEM_V4 :
1531 case Hexagon::MEMw_ADDi_MEM_V4 :
1532 case Hexagon::MEMw_SUBi_MEM_V4 :
1533 case Hexagon::MEMw_ADDr_MEM_V4 :
1534 case Hexagon::MEMw_SUBr_MEM_V4 :
1535 case Hexagon::MEMw_ANDr_MEM_V4 :
1536 case Hexagon::MEMw_ORr_MEM_V4 :
1537 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
1538 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
1539 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
1540 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
1541 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
1542 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
1543 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
1544 case Hexagon::MEMh_ADDSUBi_MEM_V4 :
1545 case Hexagon::MEMh_ADDi_MEM_V4 :
1546 case Hexagon::MEMh_SUBi_MEM_V4 :
1547 case Hexagon::MEMh_ADDr_MEM_V4 :
1548 case Hexagon::MEMh_SUBr_MEM_V4 :
1549 case Hexagon::MEMh_ANDr_MEM_V4 :
1550 case Hexagon::MEMh_ORr_MEM_V4 :
1551 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
1552 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
1553 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
1554 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
1555 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
1556 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
1557 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
1558 case Hexagon::MEMb_ADDSUBi_MEM_V4 :
1559 case Hexagon::MEMb_ADDi_MEM_V4 :
1560 case Hexagon::MEMb_SUBi_MEM_V4 :
1561 case Hexagon::MEMb_ADDr_MEM_V4 :
1562 case Hexagon::MEMb_SUBr_MEM_V4 :
1563 case Hexagon::MEMb_ANDr_MEM_V4 :
1564 case Hexagon::MEMb_ORr_MEM_V4 :
1571 bool HexagonInstrInfo::
1572 isSpillPredRegOp(const MachineInstr *MI) const {
1573 switch (MI->getOpcode())
1575 case Hexagon::STriw_pred :
1576 case Hexagon::LDriw_pred :
1583 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1584 const HexagonRegisterInfo& QRI = getRegisterInfo();
1585 switch (MI->getOpcode())
1587 case Hexagon::ADD_ri_cPt:
1588 case Hexagon::ADD_ri_cNotPt:
1589 case Hexagon::ADD_rr_cPt:
1590 case Hexagon::ADD_rr_cNotPt:
1591 case Hexagon::XOR_rr_cPt:
1592 case Hexagon::XOR_rr_cNotPt:
1593 case Hexagon::AND_rr_cPt:
1594 case Hexagon::AND_rr_cNotPt:
1595 case Hexagon::OR_rr_cPt:
1596 case Hexagon::OR_rr_cNotPt:
1597 case Hexagon::SUB_rr_cPt:
1598 case Hexagon::SUB_rr_cNotPt:
1599 case Hexagon::COMBINE_rr_cPt:
1600 case Hexagon::COMBINE_rr_cNotPt:
1602 case Hexagon::ASLH_cPt_V4:
1603 case Hexagon::ASLH_cNotPt_V4:
1604 case Hexagon::ASRH_cPt_V4:
1605 case Hexagon::ASRH_cNotPt_V4:
1606 case Hexagon::SXTB_cPt_V4:
1607 case Hexagon::SXTB_cNotPt_V4:
1608 case Hexagon::SXTH_cPt_V4:
1609 case Hexagon::SXTH_cNotPt_V4:
1610 case Hexagon::ZXTB_cPt_V4:
1611 case Hexagon::ZXTB_cNotPt_V4:
1612 case Hexagon::ZXTH_cPt_V4:
1613 case Hexagon::ZXTH_cNotPt_V4:
1614 return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1622 bool HexagonInstrInfo::
1623 isConditionalLoad (const MachineInstr* MI) const {
1624 const HexagonRegisterInfo& QRI = getRegisterInfo();
1625 switch (MI->getOpcode())
1627 case Hexagon::LDrid_cPt :
1628 case Hexagon::LDrid_cNotPt :
1629 case Hexagon::LDrid_indexed_cPt :
1630 case Hexagon::LDrid_indexed_cNotPt :
1631 case Hexagon::LDriw_cPt :
1632 case Hexagon::LDriw_cNotPt :
1633 case Hexagon::LDriw_indexed_cPt :
1634 case Hexagon::LDriw_indexed_cNotPt :
1635 case Hexagon::LDrih_cPt :
1636 case Hexagon::LDrih_cNotPt :
1637 case Hexagon::LDrih_indexed_cPt :
1638 case Hexagon::LDrih_indexed_cNotPt :
1639 case Hexagon::LDrib_cPt :
1640 case Hexagon::LDrib_cNotPt :
1641 case Hexagon::LDrib_indexed_cPt :
1642 case Hexagon::LDrib_indexed_cNotPt :
1643 case Hexagon::LDriuh_cPt :
1644 case Hexagon::LDriuh_cNotPt :
1645 case Hexagon::LDriuh_indexed_cPt :
1646 case Hexagon::LDriuh_indexed_cNotPt :
1647 case Hexagon::LDriub_cPt :
1648 case Hexagon::LDriub_cNotPt :
1649 case Hexagon::LDriub_indexed_cPt :
1650 case Hexagon::LDriub_indexed_cNotPt :
1652 case Hexagon::POST_LDrid_cPt :
1653 case Hexagon::POST_LDrid_cNotPt :
1654 case Hexagon::POST_LDriw_cPt :
1655 case Hexagon::POST_LDriw_cNotPt :
1656 case Hexagon::POST_LDrih_cPt :
1657 case Hexagon::POST_LDrih_cNotPt :
1658 case Hexagon::POST_LDrib_cPt :
1659 case Hexagon::POST_LDrib_cNotPt :
1660 case Hexagon::POST_LDriuh_cPt :
1661 case Hexagon::POST_LDriuh_cNotPt :
1662 case Hexagon::POST_LDriub_cPt :
1663 case Hexagon::POST_LDriub_cNotPt :
1664 return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1665 case Hexagon::LDrid_indexed_cPt_V4 :
1666 case Hexagon::LDrid_indexed_cNotPt_V4 :
1667 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1668 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1669 case Hexagon::LDrib_indexed_cPt_V4 :
1670 case Hexagon::LDrib_indexed_cNotPt_V4 :
1671 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1672 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1673 case Hexagon::LDriub_indexed_cPt_V4 :
1674 case Hexagon::LDriub_indexed_cNotPt_V4 :
1675 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1676 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1677 case Hexagon::LDrih_indexed_cPt_V4 :
1678 case Hexagon::LDrih_indexed_cNotPt_V4 :
1679 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1680 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1681 case Hexagon::LDriuh_indexed_cPt_V4 :
1682 case Hexagon::LDriuh_indexed_cNotPt_V4 :
1683 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1684 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1685 case Hexagon::LDriw_indexed_cPt_V4 :
1686 case Hexagon::LDriw_indexed_cNotPt_V4 :
1687 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1688 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1689 return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1695 DFAPacketizer *HexagonInstrInfo::
1696 CreateTargetScheduleState(const TargetMachine *TM,
1697 const ScheduleDAG *DAG) const {
1698 const InstrItineraryData *II = TM->getInstrItineraryData();
1699 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
1702 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1703 const MachineBasicBlock *MBB,
1704 const MachineFunction &MF) const {
1705 // Debug info is never a scheduling boundary. It's necessary to be explicit
1706 // due to the special treatment of IT instructions below, otherwise a
1707 // dbg_value followed by an IT will result in the IT instruction being
1708 // considered a scheduling hazard, which is wrong. It should be the actual
1709 // instruction preceding the dbg_value instruction(s), just like it is
1710 // when debug info is not present.
1711 if (MI->isDebugValue())
1714 // Terminators and labels can't be scheduled around.
1715 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())