1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 // Return true when the given node fits in a positive half word.
26 bool isPositiveHalfWord(SDNode *N);
28 namespace HexagonISD {
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 CONST32_GP, // For marking data present in GP.
40 CMPICC, // Compare two GPR operands, set icc.
41 CMPFCC, // Compare two FP operands, set fcc.
42 BRICC, // Branch to dest on icc condition
43 BRFCC, // Branch to dest on fcc condition
44 SELECT_ICC, // Select between two values using the current ICC flags.
45 SELECT_FCC, // Select between two values using the current FCC flags.
47 Hi, Lo, // Hi/Lo operations, typically on a global address.
49 FTOI, // FP to Int within a FP register.
50 ITOF, // Int to FP within a FP register.
52 CALL, // A call instruction.
53 RET_FLAG, // Return with a flag operand.
55 BARRIER, // Memory barrier.
75 class HexagonTargetLowering : public TargetLowering {
76 int VarArgsFrameOffset; // Frame offset to start of varargs area.
78 bool CanReturnSmallStruct(const Function* CalleeFn,
79 unsigned& RetSize) const;
82 const TargetMachine &TM;
83 explicit HexagonTargetLowering(const TargetMachine &targetmachine);
85 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
86 /// for tail call optimization. Targets which want to do tail call
87 /// optimization should implement this function.
89 IsEligibleForTailCallOptimization(SDValue Callee,
90 CallingConv::ID CalleeCC,
92 bool isCalleeStructRet,
93 bool isCallerStructRet,
95 SmallVectorImpl<ISD::OutputArg> &Outs,
96 const SmallVectorImpl<SDValue> &OutVals,
97 const SmallVectorImpl<ISD::InputArg> &Ins,
98 SelectionDAG& DAG) const;
100 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
101 bool isTruncateFree(EVT VT1, EVT VT2) const override;
103 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
105 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
107 const char *getTargetNodeName(unsigned Opcode) const override;
108 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerFormalArguments(SDValue Chain,
114 CallingConv::ID CallConv, bool isVarArg,
115 const SmallVectorImpl<ISD::InputArg> &Ins,
116 SDLoc dl, SelectionDAG &DAG,
117 SmallVectorImpl<SDValue> &InVals) const override;
118 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
122 SmallVectorImpl<SDValue> &InVals) const override;
124 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
125 CallingConv::ID CallConv, bool isVarArg,
126 const SmallVectorImpl<ISD::InputArg> &Ins,
127 SDLoc dl, SelectionDAG &DAG,
128 SmallVectorImpl<SDValue> &InVals,
129 const SmallVectorImpl<SDValue> &OutVals,
130 SDValue Callee) const;
132 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
134 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerReturn(SDValue Chain,
137 CallingConv::ID CallConv, bool isVarArg,
138 const SmallVectorImpl<ISD::OutputArg> &Outs,
139 const SmallVectorImpl<SDValue> &OutVals,
140 SDLoc dl, SelectionDAG &DAG) const override;
143 EmitInstrWithCustomInserter(MachineInstr *MI,
144 MachineBasicBlock *BB) const override;
146 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
148 EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
152 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
155 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
156 SDValue &Base, SDValue &Offset,
157 ISD::MemIndexedMode &AM,
158 SelectionDAG &DAG) const override;
160 std::pair<unsigned, const TargetRegisterClass*>
161 getRegForInlineAsmConstraint(const std::string &Constraint,
162 MVT VT) const override;
165 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
166 /// isLegalAddressingMode - Return true if the addressing mode represented
167 /// by AM is legal for this target, for a load/store of the specified type.
168 /// The type may be VoidTy, in which case only return true if the addressing
169 /// mode is legal for a load/store of any legal type.
170 /// TODO: Handle pre/postinc as well.
171 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
172 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
174 /// isLegalICmpImmediate - Return true if the specified immediate is legal
175 /// icmp immediate, that is the target has icmp instructions which can
176 /// compare a register against the immediate without having to materialize
177 /// the immediate into a register.
178 bool isLegalICmpImmediate(int64_t Imm) const override;
180 } // end namespace llvm
182 #endif // Hexagon_ISELLOWERING_H