1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace HexagonISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 CONST32_GP, // For marking data present in GP.
36 CMPICC, // Compare two GPR operands, set icc.
37 CMPFCC, // Compare two FP operands, set fcc.
38 BRICC, // Branch to dest on icc condition
39 BRFCC, // Branch to dest on fcc condition
40 SELECT_ICC, // Select between two values using the current ICC flags.
41 SELECT_FCC, // Select between two values using the current FCC flags.
43 Hi, Lo, // Hi/Lo operations, typically on a global address.
45 FTOI, // FP to Int within a FP register.
46 ITOF, // Int to FP within a FP register.
48 CALL, // A call instruction.
49 RET_FLAG, // Return with a flag operand.
51 BARRIER, // Memory barrier.
71 class HexagonTargetLowering : public TargetLowering {
72 int VarArgsFrameOffset; // Frame offset to start of varargs area.
74 bool CanReturnSmallStruct(const Function* CalleeFn,
75 unsigned& RetSize) const;
78 const TargetMachine &TM;
79 explicit HexagonTargetLowering(const TargetMachine &targetmachine);
81 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
82 /// for tail call optimization. Targets which want to do tail call
83 /// optimization should implement this function.
85 IsEligibleForTailCallOptimization(SDValue Callee,
86 CallingConv::ID CalleeCC,
88 bool isCalleeStructRet,
89 bool isCallerStructRet,
91 SmallVectorImpl<ISD::OutputArg> &Outs,
92 const SmallVectorImpl<SDValue> &OutVals,
93 const SmallVectorImpl<ISD::InputArg> &Ins,
94 SelectionDAG& DAG) const;
96 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
97 bool isTruncateFree(EVT VT1, EVT VT2) const override;
99 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
101 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
103 const char *getTargetNodeName(unsigned Opcode) const override;
104 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerFormalArguments(SDValue Chain,
110 CallingConv::ID CallConv, bool isVarArg,
111 const SmallVectorImpl<ISD::InputArg> &Ins,
112 SDLoc dl, SelectionDAG &DAG,
113 SmallVectorImpl<SDValue> &InVals) const override;
114 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
118 SmallVectorImpl<SDValue> &InVals) const override;
120 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
121 CallingConv::ID CallConv, bool isVarArg,
122 const SmallVectorImpl<ISD::InputArg> &Ins,
123 SDLoc dl, SelectionDAG &DAG,
124 SmallVectorImpl<SDValue> &InVals,
125 const SmallVectorImpl<SDValue> &OutVals,
126 SDValue Callee) const;
128 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
130 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerReturn(SDValue Chain,
133 CallingConv::ID CallConv, bool isVarArg,
134 const SmallVectorImpl<ISD::OutputArg> &Outs,
135 const SmallVectorImpl<SDValue> &OutVals,
136 SDLoc dl, SelectionDAG &DAG) const override;
139 EmitInstrWithCustomInserter(MachineInstr *MI,
140 MachineBasicBlock *BB) const override;
142 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
144 EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
148 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
151 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
152 SDValue &Base, SDValue &Offset,
153 ISD::MemIndexedMode &AM,
154 SelectionDAG &DAG) const override;
156 std::pair<unsigned, const TargetRegisterClass*>
157 getRegForInlineAsmConstraint(const std::string &Constraint,
158 MVT VT) const override;
161 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
162 /// isLegalAddressingMode - Return true if the addressing mode represented
163 /// by AM is legal for this target, for a load/store of the specified type.
164 /// The type may be VoidTy, in which case only return true if the addressing
165 /// mode is legal for a load/store of any legal type.
166 /// TODO: Handle pre/postinc as well.
167 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
168 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
170 /// isLegalICmpImmediate - Return true if the specified immediate is legal
171 /// icmp immediate, that is the target has icmp instructions which can
172 /// compare a register against the immediate without having to materialize
173 /// the immediate into a register.
174 bool isLegalICmpImmediate(int64_t Imm) const override;
176 } // end namespace llvm
178 #endif // Hexagon_ISELLOWERING_H