1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 // Return true when the given node fits in a positive half word.
26 bool isPositiveHalfWord(SDNode *N);
28 namespace HexagonISD {
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 CONST32_GP, // For marking data present in GP.
44 CMPICC, // Compare two GPR operands, set icc.
45 CMPFCC, // Compare two FP operands, set fcc.
46 BRICC, // Branch to dest on icc condition
47 BRFCC, // Branch to dest on fcc condition
48 SELECT_ICC, // Select between two values using the current ICC flags.
49 SELECT_FCC, // Select between two values using the current FCC flags.
51 Hi, Lo, // Hi/Lo operations, typically on a global address.
53 FTOI, // FP to Int within a FP register.
54 ITOF, // Int to FP within a FP register.
56 CALLv3, // A V3+ call instruction.
57 CALLv3nr, // A V3+ call instruction that doesn't return.
60 RET_FLAG, // Return with a flag operand.
62 BARRIER, // Memory barrier
93 class HexagonSubtarget;
95 class HexagonTargetLowering : public TargetLowering {
96 int VarArgsFrameOffset; // Frame offset to start of varargs area.
98 bool CanReturnSmallStruct(const Function* CalleeFn,
99 unsigned& RetSize) const;
102 const HexagonSubtarget *Subtarget;
103 explicit HexagonTargetLowering(const TargetMachine &TM,
104 const HexagonSubtarget &Subtarget);
106 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
107 /// for tail call optimization. Targets which want to do tail call
108 /// optimization should implement this function.
110 IsEligibleForTailCallOptimization(SDValue Callee,
111 CallingConv::ID CalleeCC,
113 bool isCalleeStructRet,
114 bool isCallerStructRet,
116 SmallVectorImpl<ISD::OutputArg> &Outs,
117 const SmallVectorImpl<SDValue> &OutVals,
118 const SmallVectorImpl<ISD::InputArg> &Ins,
119 SelectionDAG& DAG) const;
121 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
122 bool isTruncateFree(EVT VT1, EVT VT2) const override;
124 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
126 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
128 const char *getTargetNodeName(unsigned Opcode) const override;
129 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerFormalArguments(SDValue Chain,
135 CallingConv::ID CallConv, bool isVarArg,
136 const SmallVectorImpl<ISD::InputArg> &Ins,
137 SDLoc dl, SelectionDAG &DAG,
138 SmallVectorImpl<SDValue> &InVals) const override;
139 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
143 SmallVectorImpl<SDValue> &InVals) const override;
145 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
146 CallingConv::ID CallConv, bool isVarArg,
147 const SmallVectorImpl<ISD::InputArg> &Ins,
148 SDLoc dl, SelectionDAG &DAG,
149 SmallVectorImpl<SDValue> &InVals,
150 const SmallVectorImpl<SDValue> &OutVals,
151 SDValue Callee) const;
153 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
154 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
155 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerReturn(SDValue Chain,
158 CallingConv::ID CallConv, bool isVarArg,
159 const SmallVectorImpl<ISD::OutputArg> &Outs,
160 const SmallVectorImpl<SDValue> &OutVals,
161 SDLoc dl, SelectionDAG &DAG) const override;
164 EmitInstrWithCustomInserter(MachineInstr *MI,
165 MachineBasicBlock *BB) const override;
167 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
168 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
169 EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
173 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
176 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
177 SDValue &Base, SDValue &Offset,
178 ISD::MemIndexedMode &AM,
179 SelectionDAG &DAG) const override;
181 std::pair<unsigned, const TargetRegisterClass *>
182 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
183 const std::string &Constraint,
184 MVT VT) const override;
186 unsigned getInlineAsmMemConstraint(
187 const std::string &ConstraintCode) const override {
188 // FIXME: Map different constraints differently.
189 return InlineAsm::Constraint_m;
193 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
194 /// isLegalAddressingMode - Return true if the addressing mode represented
195 /// by AM is legal for this target, for a load/store of the specified type.
196 /// The type may be VoidTy, in which case only return true if the addressing
197 /// mode is legal for a load/store of any legal type.
198 /// TODO: Handle pre/postinc as well.
199 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
200 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
202 /// isLegalICmpImmediate - Return true if the specified immediate is legal
203 /// icmp immediate, that is the target has icmp instructions which can
204 /// compare a register against the immediate without having to materialize
205 /// the immediate into a register.
206 bool isLegalICmpImmediate(int64_t Imm) const override;
208 } // end namespace llvm
210 #endif // Hexagon_ISELLOWERING_H