1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 // Return true when the given node fits in a positive half word.
26 bool isPositiveHalfWord(SDNode *N);
28 namespace HexagonISD {
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 CONST32_GP, // For marking data present in GP.
44 CMPICC, // Compare two GPR operands, set icc.
45 CMPFCC, // Compare two FP operands, set fcc.
46 BRICC, // Branch to dest on icc condition
47 BRFCC, // Branch to dest on fcc condition
48 SELECT_ICC, // Select between two values using the current ICC flags.
49 SELECT_FCC, // Select between two values using the current FCC flags.
51 Hi, Lo, // Hi/Lo operations, typically on a global address.
53 FTOI, // FP to Int within a FP register.
54 ITOF, // Int to FP within a FP register.
56 CALLv3, // A V3+ call instruction.
57 CALLv3nr, // A V3+ call instruction that doesn't return.
60 RET_FLAG, // Return with a flag operand.
61 BR_JT, // Branch through jump table.
62 BARRIER, // Memory barrier.
105 class HexagonSubtarget;
107 class HexagonTargetLowering : public TargetLowering {
108 int VarArgsFrameOffset; // Frame offset to start of varargs area.
110 bool CanReturnSmallStruct(const Function* CalleeFn,
111 unsigned& RetSize) const;
113 void promoteLdStType(EVT VT, EVT PromotedLdStVT);
116 const HexagonSubtarget *Subtarget;
117 explicit HexagonTargetLowering(const TargetMachine &TM,
118 const HexagonSubtarget &Subtarget);
120 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
121 /// for tail call optimization. Targets which want to do tail call
122 /// optimization should implement this function.
124 IsEligibleForTailCallOptimization(SDValue Callee,
125 CallingConv::ID CalleeCC,
127 bool isCalleeStructRet,
128 bool isCallerStructRet,
130 SmallVectorImpl<ISD::OutputArg> &Outs,
131 const SmallVectorImpl<SDValue> &OutVals,
132 const SmallVectorImpl<ISD::InputArg> &Ins,
133 SelectionDAG& DAG) const;
135 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
136 bool isTruncateFree(EVT VT1, EVT VT2) const override;
138 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
140 // Should we expand the build vector with shuffles?
141 bool shouldExpandBuildVectorWithShuffles(EVT VT,
142 unsigned DefinedValues) const override;
144 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
145 const char *getTargetNodeName(unsigned Opcode) const override;
146 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
148 SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
149 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
150 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
151 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
152 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
153 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
154 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
155 SDValue LowerFormalArguments(SDValue Chain,
156 CallingConv::ID CallConv, bool isVarArg,
157 const SmallVectorImpl<ISD::InputArg> &Ins,
158 SDLoc dl, SelectionDAG &DAG,
159 SmallVectorImpl<SDValue> &InVals) const override;
160 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
161 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
163 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
164 SmallVectorImpl<SDValue> &InVals) const override;
166 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
167 CallingConv::ID CallConv, bool isVarArg,
168 const SmallVectorImpl<ISD::InputArg> &Ins,
169 SDLoc dl, SelectionDAG &DAG,
170 SmallVectorImpl<SDValue> &InVals,
171 const SmallVectorImpl<SDValue> &OutVals,
172 SDValue Callee) const;
174 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
175 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
176 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
177 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
178 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
179 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
180 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
182 SDValue LowerReturn(SDValue Chain,
183 CallingConv::ID CallConv, bool isVarArg,
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
185 const SmallVectorImpl<SDValue> &OutVals,
186 SDLoc dl, SelectionDAG &DAG) const override;
189 EmitInstrWithCustomInserter(MachineInstr *MI,
190 MachineBasicBlock *BB) const override;
192 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
193 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
194 EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
198 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
201 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
202 SDValue &Base, SDValue &Offset,
203 ISD::MemIndexedMode &AM,
204 SelectionDAG &DAG) const override;
206 std::pair<unsigned, const TargetRegisterClass *>
207 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
208 const std::string &Constraint,
209 MVT VT) const override;
211 unsigned getInlineAsmMemConstraint(
212 const std::string &ConstraintCode) const override {
213 if (ConstraintCode == "o")
214 return InlineAsm::Constraint_o;
215 else if (ConstraintCode == "v")
216 return InlineAsm::Constraint_v;
217 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
221 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
222 /// isLegalAddressingMode - Return true if the addressing mode represented
223 /// by AM is legal for this target, for a load/store of the specified type.
224 /// The type may be VoidTy, in which case only return true if the addressing
225 /// mode is legal for a load/store of any legal type.
226 /// TODO: Handle pre/postinc as well.
227 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
228 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
230 /// isLegalICmpImmediate - Return true if the specified immediate is legal
231 /// icmp immediate, that is the target has icmp instructions which can
232 /// compare a register against the immediate without having to materialize
233 /// the immediate into a register.
234 bool isLegalICmpImmediate(int64_t Imm) const override;
236 } // end namespace llvm
238 #endif // Hexagon_ISELLOWERING_H