1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 // Return true when the given node fits in a positive half word.
26 bool isPositiveHalfWord(SDNode *N);
28 namespace HexagonISD {
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 CONST32_GP, // For marking data present in GP.
40 CMPICC, // Compare two GPR operands, set icc.
41 CMPFCC, // Compare two FP operands, set fcc.
42 BRICC, // Branch to dest on icc condition
43 BRFCC, // Branch to dest on fcc condition
44 SELECT_ICC, // Select between two values using the current ICC flags.
45 SELECT_FCC, // Select between two values using the current FCC flags.
47 Hi, Lo, // Hi/Lo operations, typically on a global address.
49 FTOI, // FP to Int within a FP register.
50 ITOF, // Int to FP within a FP register.
52 CALLv3, // A V3+ call instruction.
53 CALLv3nr, // A V3+ call instruction that doesn't return.
56 RET_FLAG, // Return with a flag operand.
58 BARRIER, // Memory barrier
81 class HexagonSubtarget;
83 class HexagonTargetLowering : public TargetLowering {
84 int VarArgsFrameOffset; // Frame offset to start of varargs area.
86 bool CanReturnSmallStruct(const Function* CalleeFn,
87 unsigned& RetSize) const;
90 const HexagonSubtarget *Subtarget;
91 explicit HexagonTargetLowering(const TargetMachine &TM,
92 const HexagonSubtarget &Subtarget);
94 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
95 /// for tail call optimization. Targets which want to do tail call
96 /// optimization should implement this function.
98 IsEligibleForTailCallOptimization(SDValue Callee,
99 CallingConv::ID CalleeCC,
101 bool isCalleeStructRet,
102 bool isCallerStructRet,
104 SmallVectorImpl<ISD::OutputArg> &Outs,
105 const SmallVectorImpl<SDValue> &OutVals,
106 const SmallVectorImpl<ISD::InputArg> &Ins,
107 SelectionDAG& DAG) const;
109 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
110 bool isTruncateFree(EVT VT1, EVT VT2) const override;
112 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
114 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
116 const char *getTargetNodeName(unsigned Opcode) const override;
117 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
118 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerFormalArguments(SDValue Chain,
123 CallingConv::ID CallConv, bool isVarArg,
124 const SmallVectorImpl<ISD::InputArg> &Ins,
125 SDLoc dl, SelectionDAG &DAG,
126 SmallVectorImpl<SDValue> &InVals) const override;
127 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
131 SmallVectorImpl<SDValue> &InVals) const override;
133 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
134 CallingConv::ID CallConv, bool isVarArg,
135 const SmallVectorImpl<ISD::InputArg> &Ins,
136 SDLoc dl, SelectionDAG &DAG,
137 SmallVectorImpl<SDValue> &InVals,
138 const SmallVectorImpl<SDValue> &OutVals,
139 SDValue Callee) const;
141 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
143 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
145 SDValue LowerReturn(SDValue Chain,
146 CallingConv::ID CallConv, bool isVarArg,
147 const SmallVectorImpl<ISD::OutputArg> &Outs,
148 const SmallVectorImpl<SDValue> &OutVals,
149 SDLoc dl, SelectionDAG &DAG) const override;
152 EmitInstrWithCustomInserter(MachineInstr *MI,
153 MachineBasicBlock *BB) const override;
155 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
157 EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
161 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
164 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
165 SDValue &Base, SDValue &Offset,
166 ISD::MemIndexedMode &AM,
167 SelectionDAG &DAG) const override;
169 std::pair<unsigned, const TargetRegisterClass *>
170 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
171 const std::string &Constraint,
172 MVT VT) const override;
175 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
176 /// isLegalAddressingMode - Return true if the addressing mode represented
177 /// by AM is legal for this target, for a load/store of the specified type.
178 /// The type may be VoidTy, in which case only return true if the addressing
179 /// mode is legal for a load/store of any legal type.
180 /// TODO: Handle pre/postinc as well.
181 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
182 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
184 /// isLegalICmpImmediate - Return true if the specified immediate is legal
185 /// icmp immediate, that is the target has icmp instructions which can
186 /// compare a register against the immediate without having to materialize
187 /// the immediate into a register.
188 bool isLegalICmpImmediate(int64_t Imm) const override;
190 } // end namespace llvm
192 #endif // Hexagon_ISELLOWERING_H