1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "mcasmparser"
13 #include "HexagonRegisterInfo.h"
14 #include "HexagonTargetStreamer.h"
15 #include "MCTargetDesc/HexagonBaseInfo.h"
16 #include "MCTargetDesc/HexagonMCELFStreamer.h"
17 #include "MCTargetDesc/HexagonMCChecker.h"
18 #include "MCTargetDesc/HexagonMCExpr.h"
19 #include "MCTargetDesc/HexagonMCShuffler.h"
20 #include "MCTargetDesc/HexagonMCTargetDesc.h"
21 #include "MCTargetDesc/HexagonMCAsmInfo.h"
22 #include "MCTargetDesc/HexagonShuffler.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCELFStreamer.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCStreamer.h"
35 #include "llvm/MC/MCSectionELF.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/MC/MCTargetAsmParser.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ELF.h"
41 #include "llvm/Support/SourceMgr.h"
42 #include "llvm/Support/MemoryBuffer.h"
43 #include "llvm/Support/TargetRegistry.h"
44 #include "llvm/Support/raw_ostream.h"
49 static cl::opt<bool> EnableFutureRegs("mfuture-regs",
50 cl::desc("Enable future registers"));
52 static cl::opt<bool> WarnMissingParenthesis("mwarn-missing-parenthesis",
53 cl::desc("Warn for missing parenthesis around predicate registers"),
55 static cl::opt<bool> ErrorMissingParenthesis("merror-missing-parenthesis",
56 cl::desc("Error for missing parenthesis around predicate registers"),
58 static cl::opt<bool> WarnSignedMismatch("mwarn-sign-mismatch",
59 cl::desc("Warn for mismatching a signed and unsigned value"),
61 static cl::opt<bool> WarnNoncontigiousRegister("mwarn-noncontigious-register",
62 cl::desc("Warn for register names that arent contigious"),
64 static cl::opt<bool> ErrorNoncontigiousRegister("merror-noncontigious-register",
65 cl::desc("Error for register names that aren't contigious"),
70 struct HexagonOperand;
72 class HexagonAsmParser : public MCTargetAsmParser {
74 HexagonTargetStreamer &getTargetStreamer() {
75 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
76 return static_cast<HexagonTargetStreamer &>(TS);
80 MCAssembler *Assembler;
81 MCInstrInfo const &MCII;
85 MCAsmParser &getParser() const { return Parser; }
86 MCAssembler *getAssembler() const { return Assembler; }
87 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
89 bool equalIsAsmAssignment() override { return false; }
90 bool isLabel(AsmToken &Token) override;
92 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
93 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
94 bool ParseDirectiveFalign(unsigned Size, SMLoc L);
96 virtual bool ParseRegister(unsigned &RegNo,
98 SMLoc &EndLoc) override;
99 bool ParseDirectiveSubsection(SMLoc L);
100 bool ParseDirectiveValue(unsigned Size, SMLoc L);
101 bool ParseDirectiveComm(bool IsLocal, SMLoc L);
102 bool RegisterMatchesArch(unsigned MatchNum) const;
104 bool matchBundleOptions();
105 bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);
106 bool finishBundle(SMLoc IDLoc, MCStreamer &Out);
107 void canonicalizeImmediates(MCInst &MCI);
108 bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
109 OperandVector &InstOperands, uint64_t &ErrorInfo,
110 bool MatchingInlineAsm, bool &MustExtend);
112 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
113 OperandVector &Operands, MCStreamer &Out,
114 uint64_t &ErrorInfo, bool MatchingInlineAsm) override;
116 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override;
117 void OutOfRange(SMLoc IDLoc, long long Val, long long Max);
118 int processInstruction(MCInst &Inst, OperandVector const &Operands,
119 SMLoc IDLoc, bool &MustExtend);
121 // Check if we have an assembler and, if so, set the ELF e_header flags.
122 void chksetELFHeaderEFlags(unsigned flags) {
124 getAssembler()->setELFHeaderEFlags(flags);
127 /// @name Auto-generated Match Functions
130 #define GET_ASSEMBLER_HEADER
131 #include "HexagonGenAsmMatcher.inc"
136 HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
137 const MCInstrInfo &MII, const MCTargetOptions &Options)
138 : MCTargetAsmParser(Options, _STI), Parser(_Parser),
139 MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
140 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
142 MCAsmParserExtension::Initialize(_Parser);
145 // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
146 if (!Parser.getStreamer().hasRawTextSupport()) {
147 MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
148 Assembler = &MES->getAssembler();
152 bool mustExtend(OperandVector &Operands);
153 bool splitIdentifier(OperandVector &Operands);
154 bool parseOperand(OperandVector &Operands);
155 bool parseInstruction(OperandVector &Operands);
156 bool implicitExpressionLocation(OperandVector &Operands);
157 bool parseExpressionOrOperand(OperandVector &Operands);
158 bool parseExpression(MCExpr const *& Expr);
159 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
160 SMLoc NameLoc, OperandVector &Operands) override
162 llvm_unreachable("Unimplemented");
164 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
165 AsmToken ID, OperandVector &Operands) override;
167 virtual bool ParseDirective(AsmToken DirectiveID) override;
170 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
172 struct HexagonOperand : public MCParsedAsmOperand {
173 enum KindTy { Token, Immediate, Register } Kind;
175 SMLoc StartLoc, EndLoc;
192 OperandVector *SubInsts;
201 HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
204 HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() {
206 StartLoc = o.StartLoc;
221 /// getStartLoc - Get the location of the first token of this operand.
222 SMLoc getStartLoc() const { return StartLoc; }
224 /// getEndLoc - Get the location of the last token of this operand.
225 SMLoc getEndLoc() const { return EndLoc; }
227 unsigned getReg() const {
228 assert(Kind == Register && "Invalid access!");
232 const MCExpr *getImm() const {
233 assert(Kind == Immediate && "Invalid access!");
237 bool isToken() const { return Kind == Token; }
238 bool isImm() const { return Kind == Immediate; }
239 bool isMem() const { llvm_unreachable("No isMem"); }
240 bool isReg() const { return Kind == Register; }
242 bool CheckImmRange(int immBits, int zeroBits, bool isSigned,
243 bool isRelocatable, bool Extendable) const {
244 if (Kind == Immediate) {
245 const MCExpr *myMCExpr = getImm();
246 if (Imm.MustExtend && !Extendable)
249 if (myMCExpr->evaluateAsAbsolute(Res)) {
250 int bits = immBits + zeroBits;
251 // Field bit range is zerobits + bits
252 // zeroBits must be 0
253 if (Res & ((1 << zeroBits) - 1))
256 if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1)))
262 return ((uint64_t)Res < (uint64_t)(1ULL << bits)) ? true : false;
264 const int64_t high_bit_set = 1ULL << 63;
265 const uint64_t mask = (high_bit_set >> (63 - bits));
266 return (((uint64_t)Res & mask) == mask) ? true : false;
269 } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable)
271 else if (myMCExpr->getKind() == MCExpr::Binary ||
272 myMCExpr->getKind() == MCExpr::Unary)
278 bool isf32Ext() const { return false; }
279 bool iss32Imm() const { return CheckImmRange(32, 0, true, true, false); }
280 bool iss8Imm() const { return CheckImmRange(8, 0, true, false, false); }
281 bool iss8Imm64() const { return CheckImmRange(8, 0, true, true, false); }
282 bool iss7Imm() const { return CheckImmRange(7, 0, true, false, false); }
283 bool iss6Imm() const { return CheckImmRange(6, 0, true, false, false); }
284 bool iss4Imm() const { return CheckImmRange(4, 0, true, false, false); }
285 bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); }
286 bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
287 bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
288 bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
289 bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); }
290 bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); }
291 bool iss3Imm() const { return CheckImmRange(3, 0, true, false, false); }
293 bool isu64Imm() const { return CheckImmRange(64, 0, false, true, true); }
294 bool isu32Imm() const { return CheckImmRange(32, 0, false, true, false); }
295 bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); }
296 bool isu16Imm() const { return CheckImmRange(16, 0, false, true, false); }
297 bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); }
298 bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); }
299 bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); }
300 bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); }
301 bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); }
302 bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
303 bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); }
304 bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); }
305 bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); }
306 bool isu10Imm() const { return CheckImmRange(10, 0, false, false, false); }
307 bool isu9Imm() const { return CheckImmRange(9, 0, false, false, false); }
308 bool isu8Imm() const { return CheckImmRange(8, 0, false, false, false); }
309 bool isu7Imm() const { return CheckImmRange(7, 0, false, false, false); }
310 bool isu6Imm() const { return CheckImmRange(6, 0, false, false, false); }
311 bool isu5Imm() const { return CheckImmRange(5, 0, false, false, false); }
312 bool isu4Imm() const { return CheckImmRange(4, 0, false, false, false); }
313 bool isu3Imm() const { return CheckImmRange(3, 0, false, false, false); }
314 bool isu2Imm() const { return CheckImmRange(2, 0, false, false, false); }
315 bool isu1Imm() const { return CheckImmRange(1, 0, false, false, false); }
317 bool ism6Imm() const { return CheckImmRange(6, 0, false, false, false); }
318 bool isn8Imm() const { return CheckImmRange(8, 0, false, false, false); }
320 bool iss16Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); }
321 bool iss12Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); }
322 bool iss10Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); }
323 bool iss9Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); }
324 bool iss8Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); }
325 bool iss7Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); }
326 bool iss6Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); }
327 bool iss11_0Ext() const {
328 return CheckImmRange(11 + 26, 0, true, true, true);
330 bool iss11_1Ext() const {
331 return CheckImmRange(11 + 26, 1, true, true, true);
333 bool iss11_2Ext() const {
334 return CheckImmRange(11 + 26, 2, true, true, true);
336 bool iss11_3Ext() const {
337 return CheckImmRange(11 + 26, 3, true, true, true);
340 bool isu6Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
341 bool isu7Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); }
342 bool isu8Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); }
343 bool isu9Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); }
344 bool isu10Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); }
345 bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
346 bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); }
347 bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); }
348 bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); }
349 bool isu32MustExt() const { return isImm() && Imm.MustExtend; }
351 void addRegOperands(MCInst &Inst, unsigned N) const {
352 assert(N == 1 && "Invalid number of operands!");
353 Inst.addOperand(MCOperand::createReg(getReg()));
356 void addImmOperands(MCInst &Inst, unsigned N) const {
357 assert(N == 1 && "Invalid number of operands!");
358 Inst.addOperand(MCOperand::createExpr(getImm()));
361 void addSignedImmOperands(MCInst &Inst, unsigned N) const {
362 assert(N == 1 && "Invalid number of operands!");
363 MCExpr const *Expr = getImm();
365 if (!Expr->evaluateAsAbsolute(Value)) {
366 Inst.addOperand(MCOperand::createExpr(Expr));
369 int64_t Extended = SignExtend64 (Value, 32);
370 if ((Extended < 0) == (Value < 0)) {
371 Inst.addOperand(MCOperand::createExpr(Expr));
374 // Flip bit 33 to signal signed unsigned mismatch
375 Extended ^= 0x100000000;
376 Inst.addOperand(MCOperand::createImm(Extended));
379 void addf32ExtOperands(MCInst &Inst, unsigned N) const {
380 addImmOperands(Inst, N);
383 void adds32ImmOperands(MCInst &Inst, unsigned N) const {
384 addSignedImmOperands(Inst, N);
386 void adds8ImmOperands(MCInst &Inst, unsigned N) const {
387 addSignedImmOperands(Inst, N);
389 void adds8Imm64Operands(MCInst &Inst, unsigned N) const {
390 addSignedImmOperands(Inst, N);
392 void adds6ImmOperands(MCInst &Inst, unsigned N) const {
393 addSignedImmOperands(Inst, N);
395 void adds4ImmOperands(MCInst &Inst, unsigned N) const {
396 addSignedImmOperands(Inst, N);
398 void adds4_0ImmOperands(MCInst &Inst, unsigned N) const {
399 addSignedImmOperands(Inst, N);
401 void adds4_1ImmOperands(MCInst &Inst, unsigned N) const {
402 addSignedImmOperands(Inst, N);
404 void adds4_2ImmOperands(MCInst &Inst, unsigned N) const {
405 addSignedImmOperands(Inst, N);
407 void adds4_3ImmOperands(MCInst &Inst, unsigned N) const {
408 addSignedImmOperands(Inst, N);
410 void adds3ImmOperands(MCInst &Inst, unsigned N) const {
411 addSignedImmOperands(Inst, N);
414 void addu64ImmOperands(MCInst &Inst, unsigned N) const {
415 addImmOperands(Inst, N);
417 void addu32ImmOperands(MCInst &Inst, unsigned N) const {
418 addImmOperands(Inst, N);
420 void addu26_6ImmOperands(MCInst &Inst, unsigned N) const {
421 addImmOperands(Inst, N);
423 void addu16ImmOperands(MCInst &Inst, unsigned N) const {
424 addImmOperands(Inst, N);
426 void addu16_0ImmOperands(MCInst &Inst, unsigned N) const {
427 addImmOperands(Inst, N);
429 void addu16_1ImmOperands(MCInst &Inst, unsigned N) const {
430 addImmOperands(Inst, N);
432 void addu16_2ImmOperands(MCInst &Inst, unsigned N) const {
433 addImmOperands(Inst, N);
435 void addu16_3ImmOperands(MCInst &Inst, unsigned N) const {
436 addImmOperands(Inst, N);
438 void addu11_3ImmOperands(MCInst &Inst, unsigned N) const {
439 addImmOperands(Inst, N);
441 void addu10ImmOperands(MCInst &Inst, unsigned N) const {
442 addImmOperands(Inst, N);
444 void addu9ImmOperands(MCInst &Inst, unsigned N) const {
445 addImmOperands(Inst, N);
447 void addu8ImmOperands(MCInst &Inst, unsigned N) const {
448 addImmOperands(Inst, N);
450 void addu7ImmOperands(MCInst &Inst, unsigned N) const {
451 addImmOperands(Inst, N);
453 void addu6ImmOperands(MCInst &Inst, unsigned N) const {
454 addImmOperands(Inst, N);
456 void addu6_0ImmOperands(MCInst &Inst, unsigned N) const {
457 addImmOperands(Inst, N);
459 void addu6_1ImmOperands(MCInst &Inst, unsigned N) const {
460 addImmOperands(Inst, N);
462 void addu6_2ImmOperands(MCInst &Inst, unsigned N) const {
463 addImmOperands(Inst, N);
465 void addu6_3ImmOperands(MCInst &Inst, unsigned N) const {
466 addImmOperands(Inst, N);
468 void addu5ImmOperands(MCInst &Inst, unsigned N) const {
469 addImmOperands(Inst, N);
471 void addu4ImmOperands(MCInst &Inst, unsigned N) const {
472 addImmOperands(Inst, N);
474 void addu3ImmOperands(MCInst &Inst, unsigned N) const {
475 addImmOperands(Inst, N);
477 void addu2ImmOperands(MCInst &Inst, unsigned N) const {
478 addImmOperands(Inst, N);
480 void addu1ImmOperands(MCInst &Inst, unsigned N) const {
481 addImmOperands(Inst, N);
484 void addm6ImmOperands(MCInst &Inst, unsigned N) const {
485 addImmOperands(Inst, N);
487 void addn8ImmOperands(MCInst &Inst, unsigned N) const {
488 addImmOperands(Inst, N);
491 void adds16ExtOperands(MCInst &Inst, unsigned N) const {
492 addSignedImmOperands(Inst, N);
494 void adds12ExtOperands(MCInst &Inst, unsigned N) const {
495 addSignedImmOperands(Inst, N);
497 void adds10ExtOperands(MCInst &Inst, unsigned N) const {
498 addSignedImmOperands(Inst, N);
500 void adds9ExtOperands(MCInst &Inst, unsigned N) const {
501 addSignedImmOperands(Inst, N);
503 void adds8ExtOperands(MCInst &Inst, unsigned N) const {
504 addSignedImmOperands(Inst, N);
506 void adds6ExtOperands(MCInst &Inst, unsigned N) const {
507 addSignedImmOperands(Inst, N);
509 void adds11_0ExtOperands(MCInst &Inst, unsigned N) const {
510 addSignedImmOperands(Inst, N);
512 void adds11_1ExtOperands(MCInst &Inst, unsigned N) const {
513 addSignedImmOperands(Inst, N);
515 void adds11_2ExtOperands(MCInst &Inst, unsigned N) const {
516 addSignedImmOperands(Inst, N);
518 void adds11_3ExtOperands(MCInst &Inst, unsigned N) const {
519 addSignedImmOperands(Inst, N);
522 void addu6ExtOperands(MCInst &Inst, unsigned N) const {
523 addImmOperands(Inst, N);
525 void addu7ExtOperands(MCInst &Inst, unsigned N) const {
526 addImmOperands(Inst, N);
528 void addu8ExtOperands(MCInst &Inst, unsigned N) const {
529 addImmOperands(Inst, N);
531 void addu9ExtOperands(MCInst &Inst, unsigned N) const {
532 addImmOperands(Inst, N);
534 void addu10ExtOperands(MCInst &Inst, unsigned N) const {
535 addImmOperands(Inst, N);
537 void addu6_0ExtOperands(MCInst &Inst, unsigned N) const {
538 addImmOperands(Inst, N);
540 void addu6_1ExtOperands(MCInst &Inst, unsigned N) const {
541 addImmOperands(Inst, N);
543 void addu6_2ExtOperands(MCInst &Inst, unsigned N) const {
544 addImmOperands(Inst, N);
546 void addu6_3ExtOperands(MCInst &Inst, unsigned N) const {
547 addImmOperands(Inst, N);
549 void addu32MustExtOperands(MCInst &Inst, unsigned N) const {
550 addImmOperands(Inst, N);
553 void adds4_6ImmOperands(MCInst &Inst, unsigned N) const {
554 assert(N == 1 && "Invalid number of operands!");
555 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
556 Inst.addOperand(MCOperand::createImm(CE->getValue() << 6));
559 void adds3_6ImmOperands(MCInst &Inst, unsigned N) const {
560 assert(N == 1 && "Invalid number of operands!");
561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
562 Inst.addOperand(MCOperand::createImm(CE->getValue() << 6));
565 StringRef getToken() const {
566 assert(Kind == Token && "Invalid access!");
567 return StringRef(Tok.Data, Tok.Length);
570 virtual void print(raw_ostream &OS) const;
572 static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) {
573 HexagonOperand *Op = new HexagonOperand(Token);
574 Op->Tok.Data = Str.data();
575 Op->Tok.Length = Str.size();
578 return std::unique_ptr<HexagonOperand>(Op);
581 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S,
583 HexagonOperand *Op = new HexagonOperand(Register);
584 Op->Reg.RegNum = RegNum;
587 return std::unique_ptr<HexagonOperand>(Op);
590 static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S,
592 HexagonOperand *Op = new HexagonOperand(Immediate);
594 Op->Imm.MustExtend = false;
597 return std::unique_ptr<HexagonOperand>(Op);
601 } // end anonymous namespace.
603 void HexagonOperand::print(raw_ostream &OS) const {
606 getImm()->print(OS, nullptr);
610 OS << getReg() << ">";
613 OS << "'" << getToken() << "'";
618 /// @name Auto-generated Match Functions
619 static unsigned MatchRegisterName(StringRef Name);
621 bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
622 DEBUG(dbgs() << "Bundle:");
623 DEBUG(MCB.dump_pretty(dbgs()));
624 DEBUG(dbgs() << "--\n");
626 // Check the bundle for errors.
627 const MCRegisterInfo *RI = getContext().getRegisterInfo();
628 HexagonMCChecker Check(MCII, getSTI(), MCB, MCB, *RI);
630 bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(),
634 while (Check.getNextErrInfo() == true) {
635 unsigned Reg = Check.getErrRegister();
636 Twine R(RI->getName(Reg));
638 uint64_t Err = Check.getError();
639 if (Err != HexagonMCErrInfo::CHECK_SUCCESS) {
640 if (HexagonMCErrInfo::CHECK_ERROR_BRANCHES & Err)
642 "unconditional branch cannot precede another branch in packet");
644 if (HexagonMCErrInfo::CHECK_ERROR_NEWP & Err ||
645 HexagonMCErrInfo::CHECK_ERROR_NEWV & Err)
646 Error(IDLoc, "register `" + R +
647 "' used with `.new' "
648 "but not validly modified in the same packet");
650 if (HexagonMCErrInfo::CHECK_ERROR_REGISTERS & Err)
651 Error(IDLoc, "register `" + R + "' modified more than once");
653 if (HexagonMCErrInfo::CHECK_ERROR_READONLY & Err)
654 Error(IDLoc, "cannot write to read-only register `" + R + "'");
656 if (HexagonMCErrInfo::CHECK_ERROR_LOOP & Err)
657 Error(IDLoc, "loop-setup and some branch instructions "
658 "cannot be in the same packet");
660 if (HexagonMCErrInfo::CHECK_ERROR_ENDLOOP & Err) {
661 Twine N(HexagonMCInstrInfo::isInnerLoop(MCB) ? '0' : '1');
662 Error(IDLoc, "packet marked with `:endloop" + N + "' " +
663 "cannot contain instructions that modify register " +
667 if (HexagonMCErrInfo::CHECK_ERROR_SOLO & Err)
669 "instruction cannot appear in packet with other instructions");
671 if (HexagonMCErrInfo::CHECK_ERROR_NOSLOTS & Err)
672 Error(IDLoc, "too many slots used in packet");
674 if (Err & HexagonMCErrInfo::CHECK_ERROR_SHUFFLE) {
675 uint64_t Erm = Check.getShuffleError();
677 if (HexagonShuffler::SHUFFLE_ERROR_INVALID == Erm)
678 Error(IDLoc, "invalid instruction packet");
679 else if (HexagonShuffler::SHUFFLE_ERROR_STORES == Erm)
680 Error(IDLoc, "invalid instruction packet: too many stores");
681 else if (HexagonShuffler::SHUFFLE_ERROR_LOADS == Erm)
682 Error(IDLoc, "invalid instruction packet: too many loads");
683 else if (HexagonShuffler::SHUFFLE_ERROR_BRANCHES == Erm)
684 Error(IDLoc, "too many branches in packet");
685 else if (HexagonShuffler::SHUFFLE_ERROR_NOSLOTS == Erm)
686 Error(IDLoc, "invalid instruction packet: out of slots");
687 else if (HexagonShuffler::SHUFFLE_ERROR_SLOTS == Erm)
688 Error(IDLoc, "invalid instruction packet: slot error");
689 else if (HexagonShuffler::SHUFFLE_ERROR_ERRATA2 == Erm)
690 Error(IDLoc, "v60 packet violation");
691 else if (HexagonShuffler::SHUFFLE_ERROR_STORE_LOAD_CONFLICT == Erm)
692 Error(IDLoc, "slot 0 instruction does not allow slot 1 store");
694 Error(IDLoc, "unknown error in instruction packet");
698 unsigned Warn = Check.getWarning();
699 if (Warn != HexagonMCErrInfo::CHECK_SUCCESS) {
700 if (HexagonMCErrInfo::CHECK_WARN_CURRENT & Warn)
701 Warning(IDLoc, "register `" + R + "' used with `.cur' "
702 "but not used in the same packet");
703 else if (HexagonMCErrInfo::CHECK_WARN_TEMPORARY & Warn)
704 Warning(IDLoc, "register `" + R + "' used with `.tmp' "
705 "but not used in the same packet");
711 if (HexagonMCInstrInfo::bundleSize(MCB) == 0) {
712 assert(!HexagonMCInstrInfo::isInnerLoop(MCB));
713 assert(!HexagonMCInstrInfo::isOuterLoop(MCB));
714 // Empty packets are valid yet aren't emitted
717 Out.EmitInstruction(MCB, getSTI());
719 // If compounding and duplexing didn't reduce the size below
720 // 4 or less we have a packet that is too big.
721 if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {
722 Error(IDLoc, "invalid instruction packet: out of slots");
723 return true; // Error
727 return false; // No error
730 bool HexagonAsmParser::matchBundleOptions() {
731 MCAsmParser &Parser = getParser();
732 MCAsmLexer &Lexer = getLexer();
734 if (!Parser.getTok().is(AsmToken::Colon))
737 StringRef Option = Parser.getTok().getString();
738 if (Option.compare_lower("endloop0") == 0)
739 HexagonMCInstrInfo::setInnerLoop(MCB);
740 else if (Option.compare_lower("endloop1") == 0)
741 HexagonMCInstrInfo::setOuterLoop(MCB);
742 else if (Option.compare_lower("mem_noshuf") == 0)
743 HexagonMCInstrInfo::setMemReorderDisabled(MCB);
744 else if (Option.compare_lower("mem_shuf") == 0)
745 HexagonMCInstrInfo::setMemStoreReorderEnabled(MCB);
752 // For instruction aliases, immediates are generated rather than
753 // MCConstantExpr. Convert them for uniform MCExpr.
754 // Also check for signed/unsigned mismatches and warn
755 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
757 NewInst.setOpcode(MCI.getOpcode());
758 for (MCOperand &I : MCI)
760 int64_t Value (I.getImm());
761 if ((Value & 0x100000000) != (Value & 0x80000000)) {
762 // Detect flipped bit 33 wrt bit 32 and signal warning
763 Value ^= 0x100000000;
764 if (WarnSignedMismatch)
765 Warning (MCI.getLoc(), "Signed/Unsigned mismatch");
767 NewInst.addOperand(MCOperand::createExpr(
768 MCConstantExpr::create(Value, getContext())));
771 NewInst.addOperand(I);
775 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
776 OperandVector &InstOperands,
778 bool MatchingInlineAsm,
780 // Perform matching with tablegen asmmatcher generated function
782 MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);
783 if (result == Match_Success) {
785 MustExtend = mustExtend(InstOperands);
786 canonicalizeImmediates(MCI);
787 result = processInstruction(MCI, InstOperands, IDLoc, MustExtend);
789 DEBUG(dbgs() << "Insn:");
790 DEBUG(MCI.dump_pretty(dbgs()));
791 DEBUG(dbgs() << "\n\n");
796 // Create instruction operand for bundle instruction
797 // Break this into a separate function Code here is less readable
798 // Think about how to get an instruction error to report correctly.
799 // SMLoc will return the "{"
805 case Match_MissingFeature:
806 return Error(IDLoc, "invalid instruction");
807 case Match_MnemonicFail:
808 return Error(IDLoc, "unrecognized instruction");
809 case Match_InvalidOperand:
810 SMLoc ErrorLoc = IDLoc;
811 if (ErrorInfo != ~0U) {
812 if (ErrorInfo >= InstOperands.size())
813 return Error(IDLoc, "too few operands for instruction");
815 ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get()))
817 if (ErrorLoc == SMLoc())
820 return Error(ErrorLoc, "invalid operand for instruction");
822 llvm_unreachable("Implement any new match types added!");
825 bool HexagonAsmParser::mustExtend(OperandVector &Operands) {
827 for (std::unique_ptr<MCParsedAsmOperand> &i : Operands)
829 if (static_cast<HexagonOperand *>(i.get())->Imm.MustExtend)
831 // Multiple extenders should have been filtered by iss9Ext et. al.
832 assert(Count < 2 && "Multiple extenders");
836 bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
837 OperandVector &Operands,
840 bool MatchingInlineAsm) {
843 MCB.addOperand(MCOperand::createImm(0));
845 HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]);
846 if (FirstOperand.isToken() && FirstOperand.getToken() == "{") {
847 assert(Operands.size() == 1 && "Brackets should be by themselves");
849 getParser().Error(IDLoc, "Already in a packet");
855 if (FirstOperand.isToken() && FirstOperand.getToken() == "}") {
856 assert(Operands.size() == 1 && "Brackets should be by themselves");
858 getParser().Error(IDLoc, "Not in a packet");
862 if (matchBundleOptions())
864 return finishBundle(IDLoc, Out);
866 MCInst *SubInst = new (getParser().getContext()) MCInst;
867 bool MustExtend = false;
868 if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
869 MatchingInlineAsm, MustExtend))
871 HexagonMCInstrInfo::extendIfNeeded(
872 getParser().getContext(), MCII, MCB, *SubInst,
873 HexagonMCInstrInfo::isExtended(MCII, *SubInst) || MustExtend);
874 MCB.addOperand(MCOperand::createInst(SubInst));
876 return finishBundle(IDLoc, Out);
880 /// ParseDirective parses the Hexagon specific directives
881 bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
882 StringRef IDVal = DirectiveID.getIdentifier();
883 if ((IDVal.lower() == ".word") || (IDVal.lower() == ".4byte"))
884 return ParseDirectiveValue(4, DirectiveID.getLoc());
885 if (IDVal.lower() == ".short" || IDVal.lower() == ".hword" ||
886 IDVal.lower() == ".half")
887 return ParseDirectiveValue(2, DirectiveID.getLoc());
888 if (IDVal.lower() == ".falign")
889 return ParseDirectiveFalign(256, DirectiveID.getLoc());
890 if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon"))
891 return ParseDirectiveComm(true, DirectiveID.getLoc());
892 if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common"))
893 return ParseDirectiveComm(false, DirectiveID.getLoc());
894 if (IDVal.lower() == ".subsection")
895 return ParseDirectiveSubsection(DirectiveID.getLoc());
899 bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) {
900 const MCExpr *Subsection = 0;
903 assert((getLexer().isNot(AsmToken::EndOfStatement)) &&
904 "Invalid subsection directive");
905 getParser().parseExpression(Subsection);
907 if (!Subsection->evaluateAsAbsolute(Res))
908 return Error(L, "Cannot evaluate subsection number");
910 if (getLexer().isNot(AsmToken::EndOfStatement))
911 return TokError("unexpected token in directive");
913 // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the
914 // negative subsections together and in the same order but at the opposite
915 // end of the section. Only legacy hexagon-gcc created assembly code
916 // used negative subsections.
917 if ((Res < 0) && (Res > -8193))
918 Subsection = MCConstantExpr::create(8192 + Res, this->getContext());
920 getStreamer().SubSection(Subsection);
924 /// ::= .falign [expression]
925 bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) {
927 int64_t MaxBytesToFill = 15;
929 // if there is an arguement
930 if (getLexer().isNot(AsmToken::EndOfStatement)) {
934 // Make sure we have a number (false is returned if expression is a number)
935 if (getParser().parseExpression(Value) == false) {
936 // Make sure this is a number that is in range
937 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value);
938 uint64_t IntValue = MCE->getValue();
939 if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue))
940 return Error(ExprLoc, "literal value out of range (256) for falign");
941 MaxBytesToFill = IntValue;
944 return Error(ExprLoc, "not a valid expression for falign directive");
948 getTargetStreamer().emitFAlign(16, MaxBytesToFill);
954 /// ::= .word [ expression (, expression)* ]
955 bool HexagonAsmParser::ParseDirectiveValue(unsigned Size, SMLoc L) {
956 if (getLexer().isNot(AsmToken::EndOfStatement)) {
961 if (getParser().parseExpression(Value))
964 // Special case constant expressions to match code generator.
965 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value)) {
966 assert(Size <= 8 && "Invalid size");
967 uint64_t IntValue = MCE->getValue();
968 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
969 return Error(ExprLoc, "literal value out of range for directive");
970 getStreamer().EmitIntValue(IntValue, Size);
972 getStreamer().EmitValue(Value, Size);
974 if (getLexer().is(AsmToken::EndOfStatement))
977 // FIXME: Improve diagnostic.
978 if (getLexer().isNot(AsmToken::Comma))
979 return TokError("unexpected token in directive");
988 // This is largely a copy of AsmParser's ParseDirectiveComm extended to
989 // accept a 3rd argument, AccessAlignment which indicates the smallest
990 // memory access made to the symbol, expressed in bytes. If no
991 // AccessAlignment is specified it defaults to the Alignment Value.
993 // .lcomm Symbol, Length, Alignment, AccessAlignment
994 bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
995 // FIXME: need better way to detect if AsmStreamer (upstream removed
997 if (getStreamer().hasRawTextSupport())
998 return true; // Only object file output requires special treatment.
1001 if (getParser().parseIdentifier(Name))
1002 return TokError("expected identifier in directive");
1003 // Handle the identifier as the key symbol.
1004 MCSymbol *Sym = getContext().getOrCreateSymbol(Name);
1006 if (getLexer().isNot(AsmToken::Comma))
1007 return TokError("unexpected token in directive");
1011 SMLoc SizeLoc = getLexer().getLoc();
1012 if (getParser().parseAbsoluteExpression(Size))
1015 int64_t ByteAlignment = 1;
1016 SMLoc ByteAlignmentLoc;
1017 if (getLexer().is(AsmToken::Comma)) {
1019 ByteAlignmentLoc = getLexer().getLoc();
1020 if (getParser().parseAbsoluteExpression(ByteAlignment))
1022 if (!isPowerOf2_64(ByteAlignment))
1023 return Error(ByteAlignmentLoc, "alignment must be a power of 2");
1026 int64_t AccessAlignment = 0;
1027 if (getLexer().is(AsmToken::Comma)) {
1028 // The optional access argument specifies the size of the smallest memory
1029 // access to be made to the symbol, expressed in bytes.
1030 SMLoc AccessAlignmentLoc;
1032 AccessAlignmentLoc = getLexer().getLoc();
1033 if (getParser().parseAbsoluteExpression(AccessAlignment))
1036 if (!isPowerOf2_64(AccessAlignment))
1037 return Error(AccessAlignmentLoc, "access alignment must be a power of 2");
1040 if (getLexer().isNot(AsmToken::EndOfStatement))
1041 return TokError("unexpected token in '.comm' or '.lcomm' directive");
1045 // NOTE: a size of zero for a .comm should create a undefined symbol
1046 // but a size of .lcomm creates a bss symbol of size zero.
1048 return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't "
1049 "be less than zero");
1051 // NOTE: The alignment in the directive is a power of 2 value, the assembler
1052 // may internally end up wanting an alignment in bytes.
1053 // FIXME: Diagnose overflow.
1054 if (ByteAlignment < 0)
1055 return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive "
1056 "alignment, can't be less than zero");
1058 if (!Sym->isUndefined())
1059 return Error(Loc, "invalid symbol redefinition");
1061 HexagonMCELFStreamer &HexagonELFStreamer =
1062 static_cast<HexagonMCELFStreamer &>(getStreamer());
1064 HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment,
1069 HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment,
1074 // validate register against architecture
1075 bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
1079 // extern "C" void LLVMInitializeHexagonAsmLexer();
1081 /// Force static initialization.
1082 extern "C" void LLVMInitializeHexagonAsmParser() {
1083 RegisterMCAsmParser<HexagonAsmParser> X(TheHexagonTarget);
1086 #define GET_MATCHER_IMPLEMENTATION
1087 #define GET_REGISTER_MATCHER
1088 #include "HexagonGenAsmMatcher.inc"
1091 bool previousEqual(OperandVector &Operands, size_t Index, StringRef String) {
1092 if (Index >= Operands.size())
1094 MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1];
1095 if (!Operand.isToken())
1097 return static_cast<HexagonOperand &>(Operand).getToken().equals_lower(String);
1099 bool previousIsLoop(OperandVector &Operands, size_t Index) {
1100 return previousEqual(Operands, Index, "loop0") ||
1101 previousEqual(Operands, Index, "loop1") ||
1102 previousEqual(Operands, Index, "sp1loop0") ||
1103 previousEqual(Operands, Index, "sp2loop0") ||
1104 previousEqual(Operands, Index, "sp3loop0");
1108 bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {
1109 AsmToken const &Token = getParser().getTok();
1110 StringRef String = Token.getString();
1111 SMLoc Loc = Token.getLoc();
1114 std::pair<StringRef, StringRef> HeadTail = String.split('.');
1115 if (!HeadTail.first.empty())
1116 Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc));
1117 if (!HeadTail.second.empty())
1118 Operands.push_back(HexagonOperand::CreateToken(
1119 String.substr(HeadTail.first.size(), 1), Loc));
1120 String = HeadTail.second;
1121 } while (!String.empty());
1125 bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
1129 MCAsmLexer &Lexer = getLexer();
1130 if (!ParseRegister(Register, Begin, End)) {
1131 if (!ErrorMissingParenthesis)
1139 if (previousEqual(Operands, 0, "if")) {
1140 if (WarnMissingParenthesis)
1141 Warning (Begin, "Missing parenthesis around predicate register");
1142 static char const *LParen = "(";
1143 static char const *RParen = ")";
1144 Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));
1145 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
1146 AsmToken MaybeDotNew = Lexer.getTok();
1147 if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
1148 MaybeDotNew.getString().equals_lower(".new"))
1149 splitIdentifier(Operands);
1150 Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
1153 if (previousEqual(Operands, 0, "!") &&
1154 previousEqual(Operands, 1, "if")) {
1155 if (WarnMissingParenthesis)
1156 Warning (Begin, "Missing parenthesis around predicate register");
1157 static char const *LParen = "(";
1158 static char const *RParen = ")";
1159 Operands.insert(Operands.end () - 1,
1160 HexagonOperand::CreateToken(LParen, Begin));
1161 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
1162 AsmToken MaybeDotNew = Lexer.getTok();
1163 if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
1164 MaybeDotNew.getString().equals_lower(".new"))
1165 splitIdentifier(Operands);
1166 Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
1171 Operands.push_back(HexagonOperand::CreateReg(
1172 Register, Begin, End));
1175 return splitIdentifier(Operands);
1178 bool HexagonAsmParser::isLabel(AsmToken &Token) {
1179 MCAsmLexer &Lexer = getLexer();
1180 AsmToken const &Second = Lexer.getTok();
1181 AsmToken Third = Lexer.peekTok();
1182 StringRef String = Token.getString();
1183 if (Token.is(AsmToken::TokenKind::LCurly) ||
1184 Token.is(AsmToken::TokenKind::RCurly))
1186 if (!Token.is(AsmToken::TokenKind::Identifier))
1188 if (!MatchRegisterName(String.lower()))
1191 assert(Second.is(AsmToken::Colon));
1192 StringRef Raw (String.data(), Third.getString().data() - String.data() +
1193 Third.getString().size());
1194 std::string Collapsed = Raw;
1195 Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace),
1197 StringRef Whole = Collapsed;
1198 std::pair<StringRef, StringRef> DotSplit = Whole.split('.');
1199 if (!MatchRegisterName(DotSplit.first.lower()))
1204 bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) {
1205 if (!Contigious && ErrorNoncontigiousRegister) {
1206 Error(Loc, "Register name is not contigious");
1209 if (!Contigious && WarnNoncontigiousRegister)
1210 Warning(Loc, "Register name is not contigious");
1214 bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1215 MCAsmLexer &Lexer = getLexer();
1216 StartLoc = getLexer().getLoc();
1217 SmallVector<AsmToken, 5> Lookahead;
1218 StringRef RawString(Lexer.getTok().getString().data(), 0);
1219 bool Again = Lexer.is(AsmToken::Identifier);
1220 bool NeededWorkaround = false;
1222 AsmToken const &Token = Lexer.getTok();
1223 RawString = StringRef(RawString.data(),
1224 Token.getString().data() - RawString.data () +
1225 Token.getString().size());
1226 Lookahead.push_back(Token);
1228 bool Contigious = Lexer.getTok().getString().data() ==
1229 Lookahead.back().getString().data() +
1230 Lookahead.back().getString().size();
1231 bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||
1232 Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
1233 Lexer.is(AsmToken::Colon);
1234 bool Workaround = Lexer.is(AsmToken::Colon) ||
1235 Lookahead.back().is(AsmToken::Colon);
1236 Again = (Contigious && Type) || (Workaround && Type);
1237 NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));
1239 std::string Collapsed = RawString;
1240 Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace),
1242 StringRef FullString = Collapsed;
1243 std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
1244 unsigned DotReg = MatchRegisterName(DotSplit.first.lower());
1245 if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1246 if (DotSplit.second.empty()) {
1248 EndLoc = Lexer.getLoc();
1249 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1254 size_t First = RawString.find('.');
1255 StringRef DotString (RawString.data() + First, RawString.size() - First);
1256 Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString));
1257 EndLoc = Lexer.getLoc();
1258 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1263 std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
1264 unsigned ColonReg = MatchRegisterName(ColonSplit.first.lower());
1265 if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1266 Lexer.UnLex(Lookahead.back());
1267 Lookahead.pop_back();
1268 Lexer.UnLex(Lookahead.back());
1269 Lookahead.pop_back();
1271 EndLoc = Lexer.getLoc();
1272 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1276 while (!Lookahead.empty()) {
1277 Lexer.UnLex(Lookahead.back());
1278 Lookahead.pop_back();
1283 bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) {
1284 if (previousEqual(Operands, 0, "call"))
1286 if (previousEqual(Operands, 0, "jump"))
1287 if (!getLexer().getTok().is(AsmToken::Colon))
1289 if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1))
1291 if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") &&
1292 (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t")))
1297 bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {
1298 llvm::SmallVector<AsmToken, 4> Tokens;
1299 MCAsmLexer &Lexer = getLexer();
1301 static char const * Comma = ",";
1303 Tokens.emplace_back (Lexer.getTok());
1305 switch (Tokens.back().getKind())
1307 case AsmToken::TokenKind::Hash:
1308 if (Tokens.size () > 1)
1309 if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) {
1310 Tokens.insert(Tokens.end() - 2,
1311 AsmToken(AsmToken::TokenKind::Comma, Comma));
1315 case AsmToken::TokenKind::RCurly:
1316 case AsmToken::TokenKind::EndOfStatement:
1317 case AsmToken::TokenKind::Eof:
1324 while (!Tokens.empty()) {
1325 Lexer.UnLex(Tokens.back());
1328 return getParser().parseExpression(Expr);
1331 bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
1332 if (implicitExpressionLocation(Operands)) {
1333 MCAsmParser &Parser = getParser();
1334 SMLoc Loc = Parser.getLexer().getLoc();
1335 std::unique_ptr<HexagonOperand> Expr =
1336 HexagonOperand::CreateImm(nullptr, Loc, Loc);
1337 MCExpr const *& Val = Expr->Imm.Val;
1338 Operands.push_back(std::move(Expr));
1339 return parseExpression(Val);
1341 return parseOperand(Operands);
1344 /// Parse an instruction.
1345 bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
1346 MCAsmParser &Parser = getParser();
1347 MCAsmLexer &Lexer = getLexer();
1349 AsmToken const &Token = Parser.getTok();
1350 switch (Token.getKind()) {
1351 case AsmToken::EndOfStatement: {
1355 case AsmToken::LCurly: {
1356 if (!Operands.empty())
1359 HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1363 case AsmToken::RCurly: {
1364 if (Operands.empty()) {
1366 HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1371 case AsmToken::Comma: {
1375 case AsmToken::EqualEqual:
1376 case AsmToken::ExclaimEqual:
1377 case AsmToken::GreaterEqual:
1378 case AsmToken::GreaterGreater:
1379 case AsmToken::LessEqual:
1380 case AsmToken::LessLess: {
1381 Operands.push_back(HexagonOperand::CreateToken(
1382 Token.getString().substr(0, 1), Token.getLoc()));
1383 Operands.push_back(HexagonOperand::CreateToken(
1384 Token.getString().substr(1, 1), Token.getLoc()));
1388 case AsmToken::Hash: {
1389 bool MustNotExtend = false;
1390 bool ImplicitExpression = implicitExpressionLocation(Operands);
1391 std::unique_ptr<HexagonOperand> Expr = HexagonOperand::CreateImm(
1392 nullptr, Lexer.getLoc(), Lexer.getLoc());
1393 if (!ImplicitExpression)
1395 HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1397 bool MustExtend = false;
1398 bool HiOnly = false;
1399 bool LoOnly = false;
1400 if (Lexer.is(AsmToken::Hash)) {
1403 } else if (ImplicitExpression)
1404 MustNotExtend = true;
1405 AsmToken const &Token = Parser.getTok();
1406 if (Token.is(AsmToken::Identifier)) {
1407 StringRef String = Token.getString();
1408 AsmToken IDToken = Token;
1409 if (String.lower() == "hi") {
1411 } else if (String.lower() == "lo") {
1414 if (HiOnly || LoOnly) {
1415 AsmToken LParen = Lexer.peekTok();
1416 if (!LParen.is(AsmToken::LParen)) {
1424 if (parseExpression(Expr->Imm.Val))
1427 MCContext &Context = Parser.getContext();
1428 assert(Expr->Imm.Val != nullptr);
1429 if (Expr->Imm.Val->evaluateAsAbsolute(Value)) {
1431 Expr->Imm.Val = MCBinaryExpr::createLShr(
1432 Expr->Imm.Val, MCConstantExpr::create(16, Context), Context);
1433 if (HiOnly || LoOnly)
1434 Expr->Imm.Val = MCBinaryExpr::createAnd(
1435 Expr->Imm.Val, MCConstantExpr::create(0xffff, Context), Context);
1438 Expr->Imm.Val = HexagonNoExtendOperand::Create(Expr->Imm.Val, Context);
1439 Expr->Imm.MustExtend = MustExtend;
1440 Operands.push_back(std::move(Expr));
1446 if (parseExpressionOrOperand(Operands))
1451 bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1454 OperandVector &Operands) {
1455 getLexer().UnLex(ID);
1456 return parseInstruction(Operands);
1460 MCInst makeCombineInst(int opCode, MCOperand &Rdd,
1461 MCOperand &MO1, MCOperand &MO2) {
1463 TmpInst.setOpcode(opCode);
1464 TmpInst.addOperand(Rdd);
1465 TmpInst.addOperand(MO1);
1466 TmpInst.addOperand(MO2);
1472 // Define this matcher function after the auto-generated include so we
1473 // have the match class enum definitions.
1474 unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1476 HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp);
1481 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0
1483 : Match_InvalidOperand;
1487 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1
1489 : Match_InvalidOperand;
1491 case MCK__MINUS_1: {
1493 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == -1
1495 : Match_InvalidOperand;
1498 if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) {
1499 StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length);
1500 if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind)
1501 return Match_Success;
1502 if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind)
1503 return Match_Success;
1506 DEBUG(dbgs() << "Unmatched Operand:");
1508 DEBUG(dbgs() << "\n");
1510 return Match_InvalidOperand;
1513 void HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
1514 std::stringstream errStr;
1515 errStr << "value " << Val << "(0x" << std::hex << Val << std::dec
1516 << ") out of range: ";
1518 errStr << "0-" << Max;
1520 errStr << Max << "-" << (-Max - 1);
1521 Error(IDLoc, errStr.str().c_str());
1524 int HexagonAsmParser::processInstruction(MCInst &Inst,
1525 OperandVector const &Operands,
1526 SMLoc IDLoc, bool &MustExtend) {
1527 MCContext &Context = getParser().getContext();
1528 const MCRegisterInfo *RI = getContext().getRegisterInfo();
1529 std::string r = "r";
1530 std::string v = "v";
1531 std::string Colon = ":";
1533 bool is32bit = false; // used to distinguish between CONST32 and CONST64
1534 switch (Inst.getOpcode()) {
1538 case Hexagon::M4_mpyrr_addr:
1539 case Hexagon::S4_addi_asl_ri:
1540 case Hexagon::S4_addi_lsr_ri:
1541 case Hexagon::S4_andi_asl_ri:
1542 case Hexagon::S4_andi_lsr_ri:
1543 case Hexagon::S4_ori_asl_ri:
1544 case Hexagon::S4_ori_lsr_ri:
1545 case Hexagon::S4_or_andix:
1546 case Hexagon::S4_subi_asl_ri:
1547 case Hexagon::S4_subi_lsr_ri: {
1548 MCOperand &Ry = Inst.getOperand(0);
1549 MCOperand &src = Inst.getOperand(2);
1550 if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg()))
1551 return Match_InvalidOperand;
1555 case Hexagon::C2_cmpgei: {
1556 MCOperand &MO = Inst.getOperand(2);
1557 MO.setExpr(MCBinaryExpr::createSub(
1558 MO.getExpr(), MCConstantExpr::create(1, Context), Context));
1559 Inst.setOpcode(Hexagon::C2_cmpgti);
1563 case Hexagon::C2_cmpgeui: {
1564 MCOperand &MO = Inst.getOperand(2);
1566 bool Success = MO.getExpr()->evaluateAsAbsolute(Value);
1568 assert(Success && "Assured by matcher");
1571 MCOperand &Pd = Inst.getOperand(0);
1572 MCOperand &Rt = Inst.getOperand(1);
1573 TmpInst.setOpcode(Hexagon::C2_cmpeq);
1574 TmpInst.addOperand(Pd);
1575 TmpInst.addOperand(Rt);
1576 TmpInst.addOperand(Rt);
1579 MO.setExpr(MCBinaryExpr::createSub(
1580 MO.getExpr(), MCConstantExpr::create(1, Context), Context));
1581 Inst.setOpcode(Hexagon::C2_cmpgtui);
1585 case Hexagon::J2_loop1r:
1586 case Hexagon::J2_loop1i:
1587 case Hexagon::J2_loop0r:
1588 case Hexagon::J2_loop0i: {
1589 MCOperand &MO = Inst.getOperand(0);
1590 // Loop has different opcodes for extended vs not extended, but we should
1591 // not use the other opcode as it is a legacy artifact of TD files.
1593 if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1594 // if the the operand can fit within a 7:2 field
1595 if (Value < (1 << 8) && Value >= -(1 << 8)) {
1596 SMLoc myLoc = Operands[2]->getStartLoc();
1597 // # is left in startLoc in the case of ##
1598 // If '##' found then force extension.
1599 if (*myLoc.getPointer() == '#') {
1604 // If immediate and out of 7:2 range.
1611 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1612 case Hexagon::A2_tfrp: {
1613 MCOperand &MO = Inst.getOperand(1);
1614 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1615 std::string R1 = r + llvm::utostr_32(RegPairNum + 1);
1617 MO.setReg(MatchRegisterName(Reg1));
1618 // Add a new operand for the second register in the pair.
1619 std::string R2 = r + llvm::utostr_32(RegPairNum);
1621 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
1622 Inst.setOpcode(Hexagon::A2_combinew);
1626 case Hexagon::A2_tfrpt:
1627 case Hexagon::A2_tfrpf: {
1628 MCOperand &MO = Inst.getOperand(2);
1629 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1630 std::string R1 = r + llvm::utostr_32(RegPairNum + 1);
1632 MO.setReg(MatchRegisterName(Reg1));
1633 // Add a new operand for the second register in the pair.
1634 std::string R2 = r + llvm::utostr_32(RegPairNum);
1636 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
1637 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
1638 ? Hexagon::C2_ccombinewt
1639 : Hexagon::C2_ccombinewf);
1642 case Hexagon::A2_tfrptnew:
1643 case Hexagon::A2_tfrpfnew: {
1644 MCOperand &MO = Inst.getOperand(2);
1645 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1646 std::string R1 = r + llvm::utostr_32(RegPairNum + 1);
1648 MO.setReg(MatchRegisterName(Reg1));
1649 // Add a new operand for the second register in the pair.
1650 std::string R2 = r + llvm::utostr_32(RegPairNum);
1652 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
1653 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
1654 ? Hexagon::C2_ccombinewnewt
1655 : Hexagon::C2_ccombinewnewf);
1659 // Translate a "$Rx = CONST32(#imm)" to "$Rx = memw(gp+#LABEL) "
1660 case Hexagon::CONST32:
1661 case Hexagon::CONST32_Float_Real:
1662 case Hexagon::CONST32_Int_Real:
1663 case Hexagon::FCONST32_nsdata:
1665 // Translate a "$Rx:y = CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "
1666 case Hexagon::CONST64_Float_Real:
1667 case Hexagon::CONST64_Int_Real:
1669 // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
1670 if (!Parser.getStreamer().hasRawTextSupport()) {
1671 MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
1672 MCOperand &MO_1 = Inst.getOperand(1);
1673 MCOperand &MO_0 = Inst.getOperand(0);
1675 // push section onto section stack
1678 std::string myCharStr;
1679 MCSectionELF *mySection;
1681 // check if this as an immediate or a symbol
1683 bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value);
1685 // Create a new section - one for each constant
1686 // Some or all of the zeros are replaced with the given immediate.
1688 std::string myImmStr = utohexstr(static_cast<uint32_t>(Value));
1689 myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000")
1690 .drop_back(myImmStr.size())
1694 std::string myImmStr = utohexstr(Value);
1695 myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000")
1696 .drop_back(myImmStr.size())
1701 mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1702 ELF::SHF_ALLOC | ELF::SHF_WRITE);
1703 } else if (MO_1.isExpr()) {
1704 // .lita - for expressions
1705 myCharStr = ".lita";
1706 mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1707 ELF::SHF_ALLOC | ELF::SHF_WRITE);
1709 llvm_unreachable("unexpected type of machine operand!");
1711 MES->SwitchSection(mySection);
1712 unsigned byteSize = is32bit ? 4 : 8;
1713 getStreamer().EmitCodeAlignment(byteSize, byteSize);
1717 // for symbols, get rid of prepended ".gnu.linkonce.lx."
1719 // emit symbol if needed
1721 Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16));
1722 if (Sym->isUndefined()) {
1723 getStreamer().EmitLabel(Sym);
1724 getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
1725 getStreamer().EmitIntValue(Value, byteSize);
1727 } else if (MO_1.isExpr()) {
1728 const char *StringStart = 0;
1729 const char *StringEnd = 0;
1730 if (*Operands[4]->getStartLoc().getPointer() == '#') {
1731 StringStart = Operands[5]->getStartLoc().getPointer();
1732 StringEnd = Operands[6]->getStartLoc().getPointer();
1733 } else { // no pound
1734 StringStart = Operands[4]->getStartLoc().getPointer();
1735 StringEnd = Operands[5]->getStartLoc().getPointer();
1738 unsigned size = StringEnd - StringStart;
1739 std::string DotConst = ".CONST_";
1740 Sym = getContext().getOrCreateSymbol(DotConst +
1741 StringRef(StringStart, size));
1743 if (Sym->isUndefined()) {
1744 // case where symbol is not yet defined: emit symbol
1745 getStreamer().EmitLabel(Sym);
1746 getStreamer().EmitSymbolAttribute(Sym, MCSA_Local);
1747 getStreamer().EmitValue(MO_1.getExpr(), 4);
1750 llvm_unreachable("unexpected type of machine operand!");
1756 if (is32bit) // 32 bit
1757 TmpInst.setOpcode(Hexagon::L2_loadrigp);
1759 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
1761 TmpInst.addOperand(MO_0);
1763 MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext())));
1769 // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)"
1770 case Hexagon::A2_tfrpi: {
1771 MCOperand &Rdd = Inst.getOperand(0);
1772 MCOperand &MO = Inst.getOperand(1);
1774 int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0;
1775 MCOperand imm(MCOperand::createExpr(MCConstantExpr::create(sVal, Context)));
1776 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO);
1780 // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)"
1781 case Hexagon::TFRI64_V4: {
1782 MCOperand &Rdd = Inst.getOperand(0);
1783 MCOperand &MO = Inst.getOperand(1);
1785 if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1786 unsigned long long u64 = Value;
1787 signed int s8 = (u64 >> 32) & 0xFFFFFFFF;
1788 if (s8 < -128 || s8 > 127)
1789 OutOfRange(IDLoc, s8, -128);
1790 MCOperand imm(MCOperand::createExpr(
1791 MCConstantExpr::create(s8, Context))); // upper 32
1792 MCOperand imm2(MCOperand::createExpr(
1793 MCConstantExpr::create(u64 & 0xFFFFFFFF, Context))); // lower 32
1794 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
1796 MCOperand imm(MCOperand::createExpr(
1797 MCConstantExpr::create(0, Context))); // upper 32
1798 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO);
1803 // Handle $Rdd = combine(##imm, #imm)"
1804 case Hexagon::TFRI64_V2_ext: {
1805 MCOperand &Rdd = Inst.getOperand(0);
1806 MCOperand &MO1 = Inst.getOperand(1);
1807 MCOperand &MO2 = Inst.getOperand(2);
1809 if (MO2.getExpr()->evaluateAsAbsolute(Value)) {
1811 if (s8 < -128 || s8 > 127)
1812 OutOfRange(IDLoc, s8, -128);
1814 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);
1818 // Handle $Rdd = combine(#imm, ##imm)"
1819 case Hexagon::A4_combineii: {
1820 MCOperand &Rdd = Inst.getOperand(0);
1821 MCOperand &MO1 = Inst.getOperand(1);
1823 if (MO1.getExpr()->evaluateAsAbsolute(Value)) {
1825 if (s8 < -128 || s8 > 127)
1826 OutOfRange(IDLoc, s8, -128);
1828 MCOperand &MO2 = Inst.getOperand(2);
1829 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);
1833 case Hexagon::S2_tableidxb_goodsyntax: {
1834 Inst.setOpcode(Hexagon::S2_tableidxb);
1838 case Hexagon::S2_tableidxh_goodsyntax: {
1840 MCOperand &Rx = Inst.getOperand(0);
1841 MCOperand &_dst_ = Inst.getOperand(1);
1842 MCOperand &Rs = Inst.getOperand(2);
1843 MCOperand &Imm4 = Inst.getOperand(3);
1844 MCOperand &Imm6 = Inst.getOperand(4);
1845 Imm6.setExpr(MCBinaryExpr::createSub(
1846 Imm6.getExpr(), MCConstantExpr::create(1, Context), Context));
1847 TmpInst.setOpcode(Hexagon::S2_tableidxh);
1848 TmpInst.addOperand(Rx);
1849 TmpInst.addOperand(_dst_);
1850 TmpInst.addOperand(Rs);
1851 TmpInst.addOperand(Imm4);
1852 TmpInst.addOperand(Imm6);
1857 case Hexagon::S2_tableidxw_goodsyntax: {
1859 MCOperand &Rx = Inst.getOperand(0);
1860 MCOperand &_dst_ = Inst.getOperand(1);
1861 MCOperand &Rs = Inst.getOperand(2);
1862 MCOperand &Imm4 = Inst.getOperand(3);
1863 MCOperand &Imm6 = Inst.getOperand(4);
1864 Imm6.setExpr(MCBinaryExpr::createSub(
1865 Imm6.getExpr(), MCConstantExpr::create(2, Context), Context));
1866 TmpInst.setOpcode(Hexagon::S2_tableidxw);
1867 TmpInst.addOperand(Rx);
1868 TmpInst.addOperand(_dst_);
1869 TmpInst.addOperand(Rs);
1870 TmpInst.addOperand(Imm4);
1871 TmpInst.addOperand(Imm6);
1876 case Hexagon::S2_tableidxd_goodsyntax: {
1878 MCOperand &Rx = Inst.getOperand(0);
1879 MCOperand &_dst_ = Inst.getOperand(1);
1880 MCOperand &Rs = Inst.getOperand(2);
1881 MCOperand &Imm4 = Inst.getOperand(3);
1882 MCOperand &Imm6 = Inst.getOperand(4);
1883 Imm6.setExpr(MCBinaryExpr::createSub(
1884 Imm6.getExpr(), MCConstantExpr::create(3, Context), Context));
1885 TmpInst.setOpcode(Hexagon::S2_tableidxd);
1886 TmpInst.addOperand(Rx);
1887 TmpInst.addOperand(_dst_);
1888 TmpInst.addOperand(Rs);
1889 TmpInst.addOperand(Imm4);
1890 TmpInst.addOperand(Imm6);
1895 case Hexagon::M2_mpyui: {
1896 Inst.setOpcode(Hexagon::M2_mpyi);
1899 case Hexagon::M2_mpysmi: {
1901 MCOperand &Rd = Inst.getOperand(0);
1902 MCOperand &Rs = Inst.getOperand(1);
1903 MCOperand &Imm = Inst.getOperand(2);
1905 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1909 if (Value < 0 && Value > -256) {
1910 Imm.setExpr(MCConstantExpr::create(Value * -1, Context));
1911 TmpInst.setOpcode(Hexagon::M2_mpysin);
1912 } else if (Value < 256 && Value >= 0)
1913 TmpInst.setOpcode(Hexagon::M2_mpysip);
1915 return Match_InvalidOperand;
1918 TmpInst.setOpcode(Hexagon::M2_mpysip);
1920 return Match_InvalidOperand;
1922 TmpInst.addOperand(Rd);
1923 TmpInst.addOperand(Rs);
1924 TmpInst.addOperand(Imm);
1929 case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
1930 MCOperand &Imm = Inst.getOperand(2);
1933 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1936 if (Value == 0) { // convert to $Rd = $Rs
1937 TmpInst.setOpcode(Hexagon::A2_tfr);
1938 MCOperand &Rd = Inst.getOperand(0);
1939 MCOperand &Rs = Inst.getOperand(1);
1940 TmpInst.addOperand(Rd);
1941 TmpInst.addOperand(Rs);
1943 Imm.setExpr(MCBinaryExpr::createSub(
1944 Imm.getExpr(), MCConstantExpr::create(1, Context), Context));
1945 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
1946 MCOperand &Rd = Inst.getOperand(0);
1947 MCOperand &Rs = Inst.getOperand(1);
1948 TmpInst.addOperand(Rd);
1949 TmpInst.addOperand(Rs);
1950 TmpInst.addOperand(Imm);
1956 case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
1957 MCOperand &Rdd = Inst.getOperand(0);
1958 MCOperand &Rss = Inst.getOperand(1);
1959 MCOperand &Imm = Inst.getOperand(2);
1961 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1964 if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1])
1966 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1967 std::string R1 = r + llvm::utostr_32(RegPairNum + 1);
1969 Rss.setReg(MatchRegisterName(Reg1));
1970 // Add a new operand for the second register in the pair.
1971 std::string R2 = r + llvm::utostr_32(RegPairNum);
1973 TmpInst.setOpcode(Hexagon::A2_combinew);
1974 TmpInst.addOperand(Rdd);
1975 TmpInst.addOperand(Rss);
1976 TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
1979 Imm.setExpr(MCBinaryExpr::createSub(
1980 Imm.getExpr(), MCConstantExpr::create(1, Context), Context));
1981 Inst.setOpcode(Hexagon::S2_asr_i_p_rnd);
1986 case Hexagon::A4_boundscheck: {
1987 MCOperand &Rs = Inst.getOperand(1);
1988 unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1989 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1990 Inst.setOpcode(Hexagon::A4_boundscheck_hi);
1992 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
1993 StringRef RegPair = Name;
1994 Rs.setReg(MatchRegisterName(RegPair));
1996 Inst.setOpcode(Hexagon::A4_boundscheck_lo);
1998 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);
1999 StringRef RegPair = Name;
2000 Rs.setReg(MatchRegisterName(RegPair));
2005 case Hexagon::A2_addsp: {
2006 MCOperand &Rs = Inst.getOperand(1);
2007 unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
2008 if (RegNum & 1) { // Odd mapped to raw:hi
2009 Inst.setOpcode(Hexagon::A2_addsph);
2011 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
2012 StringRef RegPair = Name;
2013 Rs.setReg(MatchRegisterName(RegPair));
2014 } else { // Even mapped raw:lo
2015 Inst.setOpcode(Hexagon::A2_addspl);
2017 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);
2018 StringRef RegPair = Name;
2019 Rs.setReg(MatchRegisterName(RegPair));
2024 case Hexagon::M2_vrcmpys_s1: {
2025 MCOperand &Rt = Inst.getOperand(2);
2026 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2027 if (RegNum & 1) { // Odd mapped to sat:raw:hi
2028 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
2030 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
2031 StringRef RegPair = Name;
2032 Rt.setReg(MatchRegisterName(RegPair));
2033 } else { // Even mapped sat:raw:lo
2034 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
2036 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);
2037 StringRef RegPair = Name;
2038 Rt.setReg(MatchRegisterName(RegPair));
2043 case Hexagon::M2_vrcmpys_acc_s1: {
2045 MCOperand &Rxx = Inst.getOperand(0);
2046 MCOperand &Rss = Inst.getOperand(2);
2047 MCOperand &Rt = Inst.getOperand(3);
2048 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2049 if (RegNum & 1) { // Odd mapped to sat:raw:hi
2050 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
2052 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
2053 StringRef RegPair = Name;
2054 Rt.setReg(MatchRegisterName(RegPair));
2055 } else { // Even mapped sat:raw:lo
2056 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
2058 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);
2059 StringRef RegPair = Name;
2060 Rt.setReg(MatchRegisterName(RegPair));
2062 // Registers are in different positions
2063 TmpInst.addOperand(Rxx);
2064 TmpInst.addOperand(Rxx);
2065 TmpInst.addOperand(Rss);
2066 TmpInst.addOperand(Rt);
2071 case Hexagon::M2_vrcmpys_s1rp: {
2072 MCOperand &Rt = Inst.getOperand(2);
2073 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2074 if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi
2075 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
2077 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
2078 StringRef RegPair = Name;
2079 Rt.setReg(MatchRegisterName(RegPair));
2080 } else { // Even mapped rnd:sat:raw:lo
2081 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
2083 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);
2084 StringRef RegPair = Name;
2085 Rt.setReg(MatchRegisterName(RegPair));
2090 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
2091 MCOperand &Imm = Inst.getOperand(2);
2093 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
2097 Inst.setOpcode(Hexagon::S2_vsathub);
2099 Imm.setExpr(MCBinaryExpr::createSub(
2100 Imm.getExpr(), MCConstantExpr::create(1, Context), Context));
2101 Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
2106 case Hexagon::S5_vasrhrnd_goodsyntax: {
2107 MCOperand &Rdd = Inst.getOperand(0);
2108 MCOperand &Rss = Inst.getOperand(1);
2109 MCOperand &Imm = Inst.getOperand(2);
2111 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
2116 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
2117 std::string R1 = r + llvm::utostr_32(RegPairNum + 1);
2119 Rss.setReg(MatchRegisterName(Reg1));
2120 // Add a new operand for the second register in the pair.
2121 std::string R2 = r + llvm::utostr_32(RegPairNum);
2123 TmpInst.setOpcode(Hexagon::A2_combinew);
2124 TmpInst.addOperand(Rdd);
2125 TmpInst.addOperand(Rss);
2126 TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
2129 Imm.setExpr(MCBinaryExpr::createSub(
2130 Imm.getExpr(), MCConstantExpr::create(1, Context), Context));
2131 Inst.setOpcode(Hexagon::S5_vasrhrnd);
2136 case Hexagon::A2_not: {
2138 MCOperand &Rd = Inst.getOperand(0);
2139 MCOperand &Rs = Inst.getOperand(1);
2140 TmpInst.setOpcode(Hexagon::A2_subri);
2141 TmpInst.addOperand(Rd);
2143 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
2144 TmpInst.addOperand(Rs);
2150 return Match_Success;