1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "mcasmparser"
13 #include "HexagonRegisterInfo.h"
14 #include "HexagonTargetStreamer.h"
15 #include "MCTargetDesc/HexagonBaseInfo.h"
16 #include "MCTargetDesc/HexagonMCELFStreamer.h"
17 #include "MCTargetDesc/HexagonMCChecker.h"
18 #include "MCTargetDesc/HexagonMCExpr.h"
19 #include "MCTargetDesc/HexagonMCShuffler.h"
20 #include "MCTargetDesc/HexagonMCTargetDesc.h"
21 #include "MCTargetDesc/HexagonMCAsmInfo.h"
22 #include "MCTargetDesc/HexagonShuffler.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCELFStreamer.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCStreamer.h"
35 #include "llvm/MC/MCSectionELF.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/MC/MCTargetAsmParser.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ELF.h"
41 #include "llvm/Support/SourceMgr.h"
42 #include "llvm/Support/MemoryBuffer.h"
43 #include "llvm/Support/TargetRegistry.h"
44 #include "llvm/Support/raw_ostream.h"
49 static cl::opt<bool> EnableFutureRegs("mfuture-regs",
50 cl::desc("Enable future registers"));
52 static cl::opt<bool> WarnMissingParenthesis("mwarn-missing-parenthesis",
53 cl::desc("Warn for missing parenthesis around predicate registers"),
55 static cl::opt<bool> ErrorMissingParenthesis("merror-missing-parenthesis",
56 cl::desc("Error for missing parenthesis around predicate registers"),
58 static cl::opt<bool> WarnSignedMismatch("mwarn-sign-mismatch",
59 cl::desc("Warn for mismatching a signed and unsigned value"),
61 static cl::opt<bool> WarnNoncontigiousRegister("mwarn-noncontigious-register",
62 cl::desc("Warn for register names that arent contigious"),
64 static cl::opt<bool> ErrorNoncontigiousRegister("merror-noncontigious-register",
65 cl::desc("Error for register names that aren't contigious"),
70 struct HexagonOperand;
72 class HexagonAsmParser : public MCTargetAsmParser {
74 HexagonTargetStreamer &getTargetStreamer() {
75 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
76 return static_cast<HexagonTargetStreamer &>(TS);
81 MCAssembler *Assembler;
82 MCInstrInfo const &MCII;
86 MCAsmParser &getParser() const { return Parser; }
87 MCAssembler *getAssembler() const { return Assembler; }
88 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
90 bool equalIsAsmAssignment() override { return false; }
91 bool isLabel(AsmToken &Token) override;
93 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
94 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
95 bool ParseDirectiveFalign(unsigned Size, SMLoc L);
97 virtual bool ParseRegister(unsigned &RegNo,
99 SMLoc &EndLoc) override;
100 bool ParseDirectiveSubsection(SMLoc L);
101 bool ParseDirectiveValue(unsigned Size, SMLoc L);
102 bool ParseDirectiveComm(bool IsLocal, SMLoc L);
103 bool RegisterMatchesArch(unsigned MatchNum) const;
105 bool matchBundleOptions();
106 bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);
107 bool finishBundle(SMLoc IDLoc, MCStreamer &Out);
108 void canonicalizeImmediates(MCInst &MCI);
109 bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
110 OperandVector &InstOperands, uint64_t &ErrorInfo,
111 bool MatchingInlineAsm, bool &MustExtend);
113 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
114 OperandVector &Operands, MCStreamer &Out,
115 uint64_t &ErrorInfo, bool MatchingInlineAsm) override;
117 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override;
118 void OutOfRange(SMLoc IDLoc, long long Val, long long Max);
119 int processInstruction(MCInst &Inst, OperandVector const &Operands,
120 SMLoc IDLoc, bool &MustExtend);
122 // Check if we have an assembler and, if so, set the ELF e_header flags.
123 void chksetELFHeaderEFlags(unsigned flags) {
125 getAssembler()->setELFHeaderEFlags(flags);
128 /// @name Auto-generated Match Functions
131 #define GET_ASSEMBLER_HEADER
132 #include "HexagonGenAsmMatcher.inc"
137 HexagonAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
138 const MCInstrInfo &MII, const MCTargetOptions &Options)
139 : MCTargetAsmParser(Options), STI(_STI), Parser(_Parser),
140 MCII (MII), InBrackets(false) {
141 MCB.setOpcode(Hexagon::BUNDLE);
142 setAvailableFeatures(
143 ComputeAvailableFeatures(_STI.getFeatureBits()));
145 MCAsmParserExtension::Initialize(_Parser);
148 // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
149 if (!Parser.getStreamer().hasRawTextSupport()) {
150 MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
151 Assembler = &MES->getAssembler();
155 bool mustExtend(OperandVector &Operands);
156 bool splitIdentifier(OperandVector &Operands);
157 bool parseOperand(OperandVector &Operands);
158 bool parseInstruction(OperandVector &Operands);
159 bool implicitExpressionLocation(OperandVector &Operands);
160 bool parseExpressionOrOperand(OperandVector &Operands);
161 bool parseExpression(MCExpr const *& Expr);
162 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
163 SMLoc NameLoc, OperandVector &Operands) override
165 llvm_unreachable("Unimplemented");
167 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
168 AsmToken ID, OperandVector &Operands) override;
170 virtual bool ParseDirective(AsmToken DirectiveID) override;
173 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
175 struct HexagonOperand : public MCParsedAsmOperand {
176 enum KindTy { Token, Immediate, Register } Kind;
178 SMLoc StartLoc, EndLoc;
195 OperandVector *SubInsts;
204 HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
207 HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() {
209 StartLoc = o.StartLoc;
224 /// getStartLoc - Get the location of the first token of this operand.
225 SMLoc getStartLoc() const { return StartLoc; }
227 /// getEndLoc - Get the location of the last token of this operand.
228 SMLoc getEndLoc() const { return EndLoc; }
230 unsigned getReg() const {
231 assert(Kind == Register && "Invalid access!");
235 const MCExpr *getImm() const {
236 assert(Kind == Immediate && "Invalid access!");
240 bool isToken() const { return Kind == Token; }
241 bool isImm() const { return Kind == Immediate; }
242 bool isMem() const { llvm_unreachable("No isMem"); }
243 bool isReg() const { return Kind == Register; }
245 bool CheckImmRange(int immBits, int zeroBits, bool isSigned,
246 bool isRelocatable, bool Extendable) const {
247 if (Kind == Immediate) {
248 const MCExpr *myMCExpr = getImm();
249 if (Imm.MustExtend && !Extendable)
252 if (myMCExpr->evaluateAsAbsolute(Res)) {
253 int bits = immBits + zeroBits;
254 // Field bit range is zerobits + bits
255 // zeroBits must be 0
256 if (Res & ((1 << zeroBits) - 1))
259 if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1)))
265 return ((uint64_t)Res < (uint64_t)(1ULL << bits)) ? true : false;
267 const int64_t high_bit_set = 1ULL << 63;
268 const uint64_t mask = (high_bit_set >> (63 - bits));
269 return (((uint64_t)Res & mask) == mask) ? true : false;
272 } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable)
274 else if (myMCExpr->getKind() == MCExpr::Binary ||
275 myMCExpr->getKind() == MCExpr::Unary)
281 bool isf32Ext() const { return false; }
282 bool iss32Imm() const { return CheckImmRange(32, 0, true, true, false); }
283 bool iss8Imm() const { return CheckImmRange(8, 0, true, false, false); }
284 bool iss8Imm64() const { return CheckImmRange(8, 0, true, true, false); }
285 bool iss7Imm() const { return CheckImmRange(7, 0, true, false, false); }
286 bool iss6Imm() const { return CheckImmRange(6, 0, true, false, false); }
287 bool iss4Imm() const { return CheckImmRange(4, 0, true, false, false); }
288 bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); }
289 bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
290 bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
291 bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
292 bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); }
293 bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); }
294 bool iss3Imm() const { return CheckImmRange(3, 0, true, false, false); }
296 bool isu64Imm() const { return CheckImmRange(64, 0, false, true, true); }
297 bool isu32Imm() const { return CheckImmRange(32, 0, false, true, false); }
298 bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); }
299 bool isu16Imm() const { return CheckImmRange(16, 0, false, true, false); }
300 bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); }
301 bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); }
302 bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); }
303 bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); }
304 bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); }
305 bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
306 bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); }
307 bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); }
308 bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); }
309 bool isu10Imm() const { return CheckImmRange(10, 0, false, false, false); }
310 bool isu9Imm() const { return CheckImmRange(9, 0, false, false, false); }
311 bool isu8Imm() const { return CheckImmRange(8, 0, false, false, false); }
312 bool isu7Imm() const { return CheckImmRange(7, 0, false, false, false); }
313 bool isu6Imm() const { return CheckImmRange(6, 0, false, false, false); }
314 bool isu5Imm() const { return CheckImmRange(5, 0, false, false, false); }
315 bool isu4Imm() const { return CheckImmRange(4, 0, false, false, false); }
316 bool isu3Imm() const { return CheckImmRange(3, 0, false, false, false); }
317 bool isu2Imm() const { return CheckImmRange(2, 0, false, false, false); }
318 bool isu1Imm() const { return CheckImmRange(1, 0, false, false, false); }
320 bool ism6Imm() const { return CheckImmRange(6, 0, false, false, false); }
321 bool isn8Imm() const { return CheckImmRange(8, 0, false, false, false); }
323 bool iss16Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); }
324 bool iss12Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); }
325 bool iss10Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); }
326 bool iss9Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); }
327 bool iss8Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); }
328 bool iss7Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); }
329 bool iss6Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); }
330 bool iss11_0Ext() const {
331 return CheckImmRange(11 + 26, 0, true, true, true);
333 bool iss11_1Ext() const {
334 return CheckImmRange(11 + 26, 1, true, true, true);
336 bool iss11_2Ext() const {
337 return CheckImmRange(11 + 26, 2, true, true, true);
339 bool iss11_3Ext() const {
340 return CheckImmRange(11 + 26, 3, true, true, true);
343 bool isu6Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
344 bool isu7Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); }
345 bool isu8Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); }
346 bool isu9Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); }
347 bool isu10Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); }
348 bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
349 bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); }
350 bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); }
351 bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); }
352 bool isu32MustExt() const { return isImm() && Imm.MustExtend; }
354 void addRegOperands(MCInst &Inst, unsigned N) const {
355 assert(N == 1 && "Invalid number of operands!");
356 Inst.addOperand(MCOperand::createReg(getReg()));
359 void addImmOperands(MCInst &Inst, unsigned N) const {
360 assert(N == 1 && "Invalid number of operands!");
361 Inst.addOperand(MCOperand::createExpr(getImm()));
364 void addSignedImmOperands(MCInst &Inst, unsigned N) const {
365 assert(N == 1 && "Invalid number of operands!");
366 MCExpr const *Expr = getImm();
368 if (!Expr->evaluateAsAbsolute(Value)) {
369 Inst.addOperand(MCOperand::createExpr(Expr));
372 int64_t Extended = SignExtend64 (Value, 32);
373 if ((Extended < 0) == (Value < 0)) {
374 Inst.addOperand(MCOperand::createExpr(Expr));
377 // Flip bit 33 to signal signed unsigned mismatch
378 Extended ^= 0x100000000;
379 Inst.addOperand(MCOperand::createImm(Extended));
382 void addf32ExtOperands(MCInst &Inst, unsigned N) const {
383 addImmOperands(Inst, N);
386 void adds32ImmOperands(MCInst &Inst, unsigned N) const {
387 addSignedImmOperands(Inst, N);
389 void adds8ImmOperands(MCInst &Inst, unsigned N) const {
390 addSignedImmOperands(Inst, N);
392 void adds8Imm64Operands(MCInst &Inst, unsigned N) const {
393 addSignedImmOperands(Inst, N);
395 void adds6ImmOperands(MCInst &Inst, unsigned N) const {
396 addSignedImmOperands(Inst, N);
398 void adds4ImmOperands(MCInst &Inst, unsigned N) const {
399 addSignedImmOperands(Inst, N);
401 void adds4_0ImmOperands(MCInst &Inst, unsigned N) const {
402 addSignedImmOperands(Inst, N);
404 void adds4_1ImmOperands(MCInst &Inst, unsigned N) const {
405 addSignedImmOperands(Inst, N);
407 void adds4_2ImmOperands(MCInst &Inst, unsigned N) const {
408 addSignedImmOperands(Inst, N);
410 void adds4_3ImmOperands(MCInst &Inst, unsigned N) const {
411 addSignedImmOperands(Inst, N);
413 void adds3ImmOperands(MCInst &Inst, unsigned N) const {
414 addSignedImmOperands(Inst, N);
417 void addu64ImmOperands(MCInst &Inst, unsigned N) const {
418 addImmOperands(Inst, N);
420 void addu32ImmOperands(MCInst &Inst, unsigned N) const {
421 addImmOperands(Inst, N);
423 void addu26_6ImmOperands(MCInst &Inst, unsigned N) const {
424 addImmOperands(Inst, N);
426 void addu16ImmOperands(MCInst &Inst, unsigned N) const {
427 addImmOperands(Inst, N);
429 void addu16_0ImmOperands(MCInst &Inst, unsigned N) const {
430 addImmOperands(Inst, N);
432 void addu16_1ImmOperands(MCInst &Inst, unsigned N) const {
433 addImmOperands(Inst, N);
435 void addu16_2ImmOperands(MCInst &Inst, unsigned N) const {
436 addImmOperands(Inst, N);
438 void addu16_3ImmOperands(MCInst &Inst, unsigned N) const {
439 addImmOperands(Inst, N);
441 void addu11_3ImmOperands(MCInst &Inst, unsigned N) const {
442 addImmOperands(Inst, N);
444 void addu10ImmOperands(MCInst &Inst, unsigned N) const {
445 addImmOperands(Inst, N);
447 void addu9ImmOperands(MCInst &Inst, unsigned N) const {
448 addImmOperands(Inst, N);
450 void addu8ImmOperands(MCInst &Inst, unsigned N) const {
451 addImmOperands(Inst, N);
453 void addu7ImmOperands(MCInst &Inst, unsigned N) const {
454 addImmOperands(Inst, N);
456 void addu6ImmOperands(MCInst &Inst, unsigned N) const {
457 addImmOperands(Inst, N);
459 void addu6_0ImmOperands(MCInst &Inst, unsigned N) const {
460 addImmOperands(Inst, N);
462 void addu6_1ImmOperands(MCInst &Inst, unsigned N) const {
463 addImmOperands(Inst, N);
465 void addu6_2ImmOperands(MCInst &Inst, unsigned N) const {
466 addImmOperands(Inst, N);
468 void addu6_3ImmOperands(MCInst &Inst, unsigned N) const {
469 addImmOperands(Inst, N);
471 void addu5ImmOperands(MCInst &Inst, unsigned N) const {
472 addImmOperands(Inst, N);
474 void addu4ImmOperands(MCInst &Inst, unsigned N) const {
475 addImmOperands(Inst, N);
477 void addu3ImmOperands(MCInst &Inst, unsigned N) const {
478 addImmOperands(Inst, N);
480 void addu2ImmOperands(MCInst &Inst, unsigned N) const {
481 addImmOperands(Inst, N);
483 void addu1ImmOperands(MCInst &Inst, unsigned N) const {
484 addImmOperands(Inst, N);
487 void addm6ImmOperands(MCInst &Inst, unsigned N) const {
488 addImmOperands(Inst, N);
490 void addn8ImmOperands(MCInst &Inst, unsigned N) const {
491 addImmOperands(Inst, N);
494 void adds16ExtOperands(MCInst &Inst, unsigned N) const {
495 addSignedImmOperands(Inst, N);
497 void adds12ExtOperands(MCInst &Inst, unsigned N) const {
498 addSignedImmOperands(Inst, N);
500 void adds10ExtOperands(MCInst &Inst, unsigned N) const {
501 addSignedImmOperands(Inst, N);
503 void adds9ExtOperands(MCInst &Inst, unsigned N) const {
504 addSignedImmOperands(Inst, N);
506 void adds8ExtOperands(MCInst &Inst, unsigned N) const {
507 addSignedImmOperands(Inst, N);
509 void adds6ExtOperands(MCInst &Inst, unsigned N) const {
510 addSignedImmOperands(Inst, N);
512 void adds11_0ExtOperands(MCInst &Inst, unsigned N) const {
513 addSignedImmOperands(Inst, N);
515 void adds11_1ExtOperands(MCInst &Inst, unsigned N) const {
516 addSignedImmOperands(Inst, N);
518 void adds11_2ExtOperands(MCInst &Inst, unsigned N) const {
519 addSignedImmOperands(Inst, N);
521 void adds11_3ExtOperands(MCInst &Inst, unsigned N) const {
522 addSignedImmOperands(Inst, N);
525 void addu6ExtOperands(MCInst &Inst, unsigned N) const {
526 addImmOperands(Inst, N);
528 void addu7ExtOperands(MCInst &Inst, unsigned N) const {
529 addImmOperands(Inst, N);
531 void addu8ExtOperands(MCInst &Inst, unsigned N) const {
532 addImmOperands(Inst, N);
534 void addu9ExtOperands(MCInst &Inst, unsigned N) const {
535 addImmOperands(Inst, N);
537 void addu10ExtOperands(MCInst &Inst, unsigned N) const {
538 addImmOperands(Inst, N);
540 void addu6_0ExtOperands(MCInst &Inst, unsigned N) const {
541 addImmOperands(Inst, N);
543 void addu6_1ExtOperands(MCInst &Inst, unsigned N) const {
544 addImmOperands(Inst, N);
546 void addu6_2ExtOperands(MCInst &Inst, unsigned N) const {
547 addImmOperands(Inst, N);
549 void addu6_3ExtOperands(MCInst &Inst, unsigned N) const {
550 addImmOperands(Inst, N);
552 void addu32MustExtOperands(MCInst &Inst, unsigned N) const {
553 addImmOperands(Inst, N);
556 void adds4_6ImmOperands(MCInst &Inst, unsigned N) const {
557 assert(N == 1 && "Invalid number of operands!");
558 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
559 Inst.addOperand(MCOperand::createImm(CE->getValue() << 6));
562 void adds3_6ImmOperands(MCInst &Inst, unsigned N) const {
563 assert(N == 1 && "Invalid number of operands!");
564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
565 Inst.addOperand(MCOperand::createImm(CE->getValue() << 6));
568 StringRef getToken() const {
569 assert(Kind == Token && "Invalid access!");
570 return StringRef(Tok.Data, Tok.Length);
573 virtual void print(raw_ostream &OS) const;
575 static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) {
576 HexagonOperand *Op = new HexagonOperand(Token);
577 Op->Tok.Data = Str.data();
578 Op->Tok.Length = Str.size();
581 return std::unique_ptr<HexagonOperand>(Op);
584 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S,
586 HexagonOperand *Op = new HexagonOperand(Register);
587 Op->Reg.RegNum = RegNum;
590 return std::unique_ptr<HexagonOperand>(Op);
593 static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S,
595 HexagonOperand *Op = new HexagonOperand(Immediate);
597 Op->Imm.MustExtend = false;
600 return std::unique_ptr<HexagonOperand>(Op);
604 } // end anonymous namespace.
606 void HexagonOperand::print(raw_ostream &OS) const {
609 getImm()->print(OS, nullptr);
613 OS << getReg() << ">";
616 OS << "'" << getToken() << "'";
621 /// @name Auto-generated Match Functions
622 static unsigned MatchRegisterName(StringRef Name);
624 bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
625 DEBUG(dbgs() << "Bundle:");
626 DEBUG(MCB.dump_pretty(dbgs()));
627 DEBUG(dbgs() << "--\n");
629 // Check the bundle for errors.
630 const MCRegisterInfo *RI = getContext().getRegisterInfo();
631 HexagonMCChecker Check(MCII, STI, MCB, MCB, *RI);
633 bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, STI, getContext(),
636 while (Check.getNextErrInfo() == true) {
637 unsigned Reg = Check.getErrRegister();
638 Twine R(RI->getName(Reg));
640 uint64_t Err = Check.getError();
641 if (Err != HexagonMCErrInfo::CHECK_SUCCESS) {
642 if (HexagonMCErrInfo::CHECK_ERROR_BRANCHES & Err)
644 "unconditional branch cannot precede another branch in packet");
646 if (HexagonMCErrInfo::CHECK_ERROR_NEWP & Err ||
647 HexagonMCErrInfo::CHECK_ERROR_NEWV & Err)
648 Error(IDLoc, "register `" + R +
649 "' used with `.new' "
650 "but not validly modified in the same packet");
652 if (HexagonMCErrInfo::CHECK_ERROR_REGISTERS & Err)
653 Error(IDLoc, "register `" + R + "' modified more than once");
655 if (HexagonMCErrInfo::CHECK_ERROR_READONLY & Err)
656 Error(IDLoc, "cannot write to read-only register `" + R + "'");
658 if (HexagonMCErrInfo::CHECK_ERROR_LOOP & Err)
659 Error(IDLoc, "loop-setup and some branch instructions "
660 "cannot be in the same packet");
662 if (HexagonMCErrInfo::CHECK_ERROR_ENDLOOP & Err) {
663 Twine N(HexagonMCInstrInfo::isInnerLoop(MCB) ? '0' : '1');
664 Error(IDLoc, "packet marked with `:endloop" + N + "' " +
665 "cannot contain instructions that modify register " +
669 if (HexagonMCErrInfo::CHECK_ERROR_SOLO & Err)
671 "instruction cannot appear in packet with other instructions");
673 if (HexagonMCErrInfo::CHECK_ERROR_NOSLOTS & Err)
674 Error(IDLoc, "too many slots used in packet");
676 if (Err & HexagonMCErrInfo::CHECK_ERROR_SHUFFLE) {
677 uint64_t Erm = Check.getShuffleError();
679 if (HexagonShuffler::SHUFFLE_ERROR_INVALID == Erm)
680 Error(IDLoc, "invalid instruction packet");
681 else if (HexagonShuffler::SHUFFLE_ERROR_STORES == Erm)
682 Error(IDLoc, "invalid instruction packet: too many stores");
683 else if (HexagonShuffler::SHUFFLE_ERROR_LOADS == Erm)
684 Error(IDLoc, "invalid instruction packet: too many loads");
685 else if (HexagonShuffler::SHUFFLE_ERROR_BRANCHES == Erm)
686 Error(IDLoc, "too many branches in packet");
687 else if (HexagonShuffler::SHUFFLE_ERROR_NOSLOTS == Erm)
688 Error(IDLoc, "invalid instruction packet: out of slots");
689 else if (HexagonShuffler::SHUFFLE_ERROR_SLOTS == Erm)
690 Error(IDLoc, "invalid instruction packet: slot error");
691 else if (HexagonShuffler::SHUFFLE_ERROR_ERRATA2 == Erm)
692 Error(IDLoc, "v60 packet violation");
693 else if (HexagonShuffler::SHUFFLE_ERROR_STORE_LOAD_CONFLICT == Erm)
694 Error(IDLoc, "slot 0 instruction does not allow slot 1 store");
696 Error(IDLoc, "unknown error in instruction packet");
700 unsigned Warn = Check.getWarning();
701 if (Warn != HexagonMCErrInfo::CHECK_SUCCESS) {
702 if (HexagonMCErrInfo::CHECK_WARN_CURRENT & Warn)
703 Warning(IDLoc, "register `" + R + "' used with `.cur' "
704 "but not used in the same packet");
705 else if (HexagonMCErrInfo::CHECK_WARN_TEMPORARY & Warn)
706 Warning(IDLoc, "register `" + R + "' used with `.tmp' "
707 "but not used in the same packet");
713 if (HexagonMCInstrInfo::bundleSize(MCB) == 0) {
714 assert(!HexagonMCInstrInfo::isInnerLoop(MCB));
715 assert(!HexagonMCInstrInfo::isOuterLoop(MCB));
716 // Empty packets are valid yet aren't emitted
719 Out.EmitInstruction(MCB, STI);
721 // If compounding and duplexing didn't reduce the size below
722 // 4 or less we have a packet that is too big.
723 if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {
724 Error(IDLoc, "invalid instruction packet: out of slots");
725 return true; // Error
729 return false; // No error
732 bool HexagonAsmParser::matchBundleOptions() {
733 MCAsmParser &Parser = getParser();
734 MCAsmLexer &Lexer = getLexer();
736 if (!Parser.getTok().is(AsmToken::Colon))
739 StringRef Option = Parser.getTok().getString();
740 if (Option.compare_lower("endloop0") == 0)
741 HexagonMCInstrInfo::setInnerLoop(MCB);
742 else if (Option.compare_lower("endloop1") == 0)
743 HexagonMCInstrInfo::setOuterLoop(MCB);
744 else if (Option.compare_lower("mem_noshuf") == 0)
745 HexagonMCInstrInfo::setMemReorderDisabled(MCB);
746 else if (Option.compare_lower("mem_shuf") == 0)
747 HexagonMCInstrInfo::setMemStoreReorderEnabled(MCB);
754 // For instruction aliases, immediates are generated rather than
755 // MCConstantExpr. Convert them for uniform MCExpr.
756 // Also check for signed/unsigned mismatches and warn
757 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
759 NewInst.setOpcode(MCI.getOpcode());
760 for (MCOperand &I : MCI)
762 int64_t Value (I.getImm());
763 if ((Value & 0x100000000) != (Value & 0x80000000)) {
764 // Detect flipped bit 33 wrt bit 32 and signal warning
765 Value ^= 0x100000000;
766 if (WarnSignedMismatch)
767 Warning (MCI.getLoc(), "Signed/Unsigned mismatch");
769 NewInst.addOperand(MCOperand::createExpr(
770 MCConstantExpr::create(Value, getContext())));
773 NewInst.addOperand(I);
777 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
778 OperandVector &InstOperands,
780 bool MatchingInlineAsm,
782 // Perform matching with tablegen asmmatcher generated function
784 MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);
785 if (result == Match_Success) {
787 MustExtend = mustExtend(InstOperands);
788 canonicalizeImmediates(MCI);
789 result = processInstruction(MCI, InstOperands, IDLoc, MustExtend);
791 DEBUG(dbgs() << "Insn:");
792 DEBUG(MCI.dump_pretty(dbgs()));
793 DEBUG(dbgs() << "\n\n");
798 // Create instruction operand for bundle instruction
799 // Break this into a separate function Code here is less readable
800 // Think about how to get an instruction error to report correctly.
801 // SMLoc will return the "{"
807 case Match_MissingFeature:
808 return Error(IDLoc, "invalid instruction");
809 case Match_MnemonicFail:
810 return Error(IDLoc, "unrecognized instruction");
811 case Match_InvalidOperand:
812 SMLoc ErrorLoc = IDLoc;
813 if (ErrorInfo != ~0U) {
814 if (ErrorInfo >= InstOperands.size())
815 return Error(IDLoc, "too few operands for instruction");
817 ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get()))
819 if (ErrorLoc == SMLoc())
822 return Error(ErrorLoc, "invalid operand for instruction");
824 llvm_unreachable("Implement any new match types added!");
827 bool HexagonAsmParser::mustExtend(OperandVector &Operands) {
829 for (std::unique_ptr<MCParsedAsmOperand> &i : Operands)
831 if (static_cast<HexagonOperand *>(i.get())->Imm.MustExtend)
833 // Multiple extenders should have been filtered by iss9Ext et. al.
834 assert(Count < 2 && "Multiple extenders");
838 bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
839 OperandVector &Operands,
842 bool MatchingInlineAsm) {
845 MCB.addOperand(MCOperand::createImm(0));
847 HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]);
848 if (FirstOperand.isToken() && FirstOperand.getToken() == "{") {
849 assert(Operands.size() == 1 && "Brackets should be by themselves");
851 getParser().Error(IDLoc, "Already in a packet");
857 if (FirstOperand.isToken() && FirstOperand.getToken() == "}") {
858 assert(Operands.size() == 1 && "Brackets should be by themselves");
860 getParser().Error(IDLoc, "Not in a packet");
864 if (matchBundleOptions())
866 return finishBundle(IDLoc, Out);
868 MCInst *SubInst = new (getParser().getContext()) MCInst;
869 bool MustExtend = false;
870 if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
871 MatchingInlineAsm, MustExtend))
873 HexagonMCInstrInfo::extendIfNeeded(
875 HexagonMCInstrInfo::isExtended(MCII, *SubInst) || MustExtend);
876 MCB.addOperand(MCOperand::createInst(SubInst));
878 return finishBundle(IDLoc, Out);
882 /// ParseDirective parses the Hexagon specific directives
883 bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
884 StringRef IDVal = DirectiveID.getIdentifier();
885 if ((IDVal.lower() == ".word") || (IDVal.lower() == ".4byte"))
886 return ParseDirectiveValue(4, DirectiveID.getLoc());
887 if (IDVal.lower() == ".short" || IDVal.lower() == ".hword" ||
888 IDVal.lower() == ".half")
889 return ParseDirectiveValue(2, DirectiveID.getLoc());
890 if (IDVal.lower() == ".falign")
891 return ParseDirectiveFalign(256, DirectiveID.getLoc());
892 if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon"))
893 return ParseDirectiveComm(true, DirectiveID.getLoc());
894 if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common"))
895 return ParseDirectiveComm(false, DirectiveID.getLoc());
896 if (IDVal.lower() == ".subsection")
897 return ParseDirectiveSubsection(DirectiveID.getLoc());
901 bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) {
902 const MCExpr *Subsection = 0;
905 assert((getLexer().isNot(AsmToken::EndOfStatement)) &&
906 "Invalid subsection directive");
907 getParser().parseExpression(Subsection);
909 if (!Subsection->evaluateAsAbsolute(Res))
910 return Error(L, "Cannot evaluate subsection number");
912 if (getLexer().isNot(AsmToken::EndOfStatement))
913 return TokError("unexpected token in directive");
915 // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the
916 // negative subsections together and in the same order but at the opposite
917 // end of the section. Only legacy hexagon-gcc created assembly code
918 // used negative subsections.
919 if ((Res < 0) && (Res > -8193))
920 Subsection = MCConstantExpr::create(8192 + Res, this->getContext());
922 getStreamer().SubSection(Subsection);
926 /// ::= .falign [expression]
927 bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) {
929 int64_t MaxBytesToFill = 15;
931 // if there is an arguement
932 if (getLexer().isNot(AsmToken::EndOfStatement)) {
936 // Make sure we have a number (false is returned if expression is a number)
937 if (getParser().parseExpression(Value) == false) {
938 // Make sure this is a number that is in range
939 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value);
940 uint64_t IntValue = MCE->getValue();
941 if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue))
942 return Error(ExprLoc, "literal value out of range (256) for falign");
943 MaxBytesToFill = IntValue;
946 return Error(ExprLoc, "not a valid expression for falign directive");
950 getTargetStreamer().emitFAlign(16, MaxBytesToFill);
956 /// ::= .word [ expression (, expression)* ]
957 bool HexagonAsmParser::ParseDirectiveValue(unsigned Size, SMLoc L) {
958 if (getLexer().isNot(AsmToken::EndOfStatement)) {
963 if (getParser().parseExpression(Value))
966 // Special case constant expressions to match code generator.
967 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value)) {
968 assert(Size <= 8 && "Invalid size");
969 uint64_t IntValue = MCE->getValue();
970 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
971 return Error(ExprLoc, "literal value out of range for directive");
972 getStreamer().EmitIntValue(IntValue, Size);
974 getStreamer().EmitValue(Value, Size);
976 if (getLexer().is(AsmToken::EndOfStatement))
979 // FIXME: Improve diagnostic.
980 if (getLexer().isNot(AsmToken::Comma))
981 return TokError("unexpected token in directive");
990 // This is largely a copy of AsmParser's ParseDirectiveComm extended to
991 // accept a 3rd argument, AccessAlignment which indicates the smallest
992 // memory access made to the symbol, expressed in bytes. If no
993 // AccessAlignment is specified it defaults to the Alignment Value.
995 // .lcomm Symbol, Length, Alignment, AccessAlignment
996 bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
997 // FIXME: need better way to detect if AsmStreamer (upstream removed
999 if (getStreamer().hasRawTextSupport())
1000 return true; // Only object file output requires special treatment.
1003 if (getParser().parseIdentifier(Name))
1004 return TokError("expected identifier in directive");
1005 // Handle the identifier as the key symbol.
1006 MCSymbol *Sym = getContext().getOrCreateSymbol(Name);
1008 if (getLexer().isNot(AsmToken::Comma))
1009 return TokError("unexpected token in directive");
1013 SMLoc SizeLoc = getLexer().getLoc();
1014 if (getParser().parseAbsoluteExpression(Size))
1017 int64_t ByteAlignment = 1;
1018 SMLoc ByteAlignmentLoc;
1019 if (getLexer().is(AsmToken::Comma)) {
1021 ByteAlignmentLoc = getLexer().getLoc();
1022 if (getParser().parseAbsoluteExpression(ByteAlignment))
1024 if (!isPowerOf2_64(ByteAlignment))
1025 return Error(ByteAlignmentLoc, "alignment must be a power of 2");
1028 int64_t AccessAlignment = 0;
1029 if (getLexer().is(AsmToken::Comma)) {
1030 // The optional access argument specifies the size of the smallest memory
1031 // access to be made to the symbol, expressed in bytes.
1032 SMLoc AccessAlignmentLoc;
1034 AccessAlignmentLoc = getLexer().getLoc();
1035 if (getParser().parseAbsoluteExpression(AccessAlignment))
1038 if (!isPowerOf2_64(AccessAlignment))
1039 return Error(AccessAlignmentLoc, "access alignment must be a power of 2");
1042 if (getLexer().isNot(AsmToken::EndOfStatement))
1043 return TokError("unexpected token in '.comm' or '.lcomm' directive");
1047 // NOTE: a size of zero for a .comm should create a undefined symbol
1048 // but a size of .lcomm creates a bss symbol of size zero.
1050 return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't "
1051 "be less than zero");
1053 // NOTE: The alignment in the directive is a power of 2 value, the assembler
1054 // may internally end up wanting an alignment in bytes.
1055 // FIXME: Diagnose overflow.
1056 if (ByteAlignment < 0)
1057 return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive "
1058 "alignment, can't be less than zero");
1060 if (!Sym->isUndefined())
1061 return Error(Loc, "invalid symbol redefinition");
1063 HexagonMCELFStreamer &HexagonELFStreamer =
1064 static_cast<HexagonMCELFStreamer &>(getStreamer());
1066 HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment,
1071 HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment,
1076 // validate register against architecture
1077 bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
1081 // extern "C" void LLVMInitializeHexagonAsmLexer();
1083 /// Force static initialization.
1084 extern "C" void LLVMInitializeHexagonAsmParser() {
1085 RegisterMCAsmParser<HexagonAsmParser> X(TheHexagonTarget);
1088 #define GET_MATCHER_IMPLEMENTATION
1089 #define GET_REGISTER_MATCHER
1090 #include "HexagonGenAsmMatcher.inc"
1093 bool previousEqual(OperandVector &Operands, size_t Index, StringRef String) {
1094 if (Index >= Operands.size())
1096 MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1];
1097 if (!Operand.isToken())
1099 return static_cast<HexagonOperand &>(Operand).getToken().equals_lower(String);
1101 bool previousIsLoop(OperandVector &Operands, size_t Index) {
1102 return previousEqual(Operands, Index, "loop0") ||
1103 previousEqual(Operands, Index, "loop1") ||
1104 previousEqual(Operands, Index, "sp1loop0") ||
1105 previousEqual(Operands, Index, "sp2loop0") ||
1106 previousEqual(Operands, Index, "sp3loop0");
1110 bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {
1111 AsmToken const &Token = getParser().getTok();
1112 StringRef String = Token.getString();
1113 SMLoc Loc = Token.getLoc();
1116 std::pair<StringRef, StringRef> HeadTail = String.split('.');
1117 if (!HeadTail.first.empty())
1118 Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc));
1119 if (!HeadTail.second.empty())
1120 Operands.push_back(HexagonOperand::CreateToken(
1121 String.substr(HeadTail.first.size(), 1), Loc));
1122 String = HeadTail.second;
1123 } while (!String.empty());
1127 bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
1131 MCAsmLexer &Lexer = getLexer();
1132 if (!ParseRegister(Register, Begin, End)) {
1133 if (!ErrorMissingParenthesis)
1141 if (previousEqual(Operands, 0, "if")) {
1142 if (WarnMissingParenthesis)
1143 Warning (Begin, "Missing parenthesis around predicate register");
1144 static char const *LParen = "(";
1145 static char const *RParen = ")";
1146 Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));
1147 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
1148 AsmToken MaybeDotNew = Lexer.getTok();
1149 if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
1150 MaybeDotNew.getString().equals_lower(".new"))
1151 splitIdentifier(Operands);
1152 Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
1155 if (previousEqual(Operands, 0, "!") &&
1156 previousEqual(Operands, 1, "if")) {
1157 if (WarnMissingParenthesis)
1158 Warning (Begin, "Missing parenthesis around predicate register");
1159 static char const *LParen = "(";
1160 static char const *RParen = ")";
1161 Operands.insert(Operands.end () - 1,
1162 HexagonOperand::CreateToken(LParen, Begin));
1163 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
1164 AsmToken MaybeDotNew = Lexer.getTok();
1165 if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
1166 MaybeDotNew.getString().equals_lower(".new"))
1167 splitIdentifier(Operands);
1168 Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
1173 Operands.push_back(HexagonOperand::CreateReg(
1174 Register, Begin, End));
1177 return splitIdentifier(Operands);
1180 bool HexagonAsmParser::isLabel(AsmToken &Token) {
1181 MCAsmLexer &Lexer = getLexer();
1182 AsmToken const &Second = Lexer.getTok();
1183 AsmToken Third = Lexer.peekTok();
1184 StringRef String = Token.getString();
1185 if (Token.is(AsmToken::TokenKind::LCurly) ||
1186 Token.is(AsmToken::TokenKind::RCurly))
1188 if (!Token.is(AsmToken::TokenKind::Identifier))
1190 if (!MatchRegisterName(String.lower()))
1192 assert(Second.is(AsmToken::Colon)); (void)Second;
1193 StringRef Raw (String.data(), Third.getString().data() - String.data() +
1194 Third.getString().size());
1195 std::string Collapsed = Raw;
1196 Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace),
1198 StringRef Whole = Collapsed;
1199 std::pair<StringRef, StringRef> DotSplit = Whole.split('.');
1200 if (!MatchRegisterName(DotSplit.first.lower()))
1205 bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) {
1206 if (!Contigious && ErrorNoncontigiousRegister) {
1207 Error(Loc, "Register name is not contigious");
1210 if (!Contigious && WarnNoncontigiousRegister)
1211 Warning(Loc, "Register name is not contigious");
1215 bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1216 MCAsmLexer &Lexer = getLexer();
1217 StartLoc = getLexer().getLoc();
1218 SmallVector<AsmToken, 5> Lookahead;
1219 StringRef RawString(Lexer.getTok().getString().data(), 0);
1220 bool Again = Lexer.is(AsmToken::Identifier);
1221 bool NeededWorkaround = false;
1223 AsmToken const &Token = Lexer.getTok();
1224 RawString = StringRef(RawString.data(),
1225 Token.getString().data() - RawString.data () +
1226 Token.getString().size());
1227 Lookahead.push_back(Token);
1229 bool Contigious = Lexer.getTok().getString().data() ==
1230 Lookahead.back().getString().data() +
1231 Lookahead.back().getString().size();
1232 bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||
1233 Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
1234 Lexer.is(AsmToken::Colon);
1235 bool Workaround = Lexer.is(AsmToken::Colon) ||
1236 Lookahead.back().is(AsmToken::Colon);
1237 Again = (Contigious && Type) || (Workaround && Type);
1238 NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));
1240 std::string Collapsed = RawString;
1241 Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace),
1243 StringRef FullString = Collapsed;
1244 std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
1245 unsigned DotReg = MatchRegisterName(DotSplit.first.lower());
1246 if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1247 if (DotSplit.second.empty()) {
1249 EndLoc = Lexer.getLoc();
1250 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1255 size_t First = RawString.find('.');
1256 StringRef DotString (RawString.data() + First, RawString.size() - First);
1257 Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString));
1258 EndLoc = Lexer.getLoc();
1259 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1264 std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
1265 unsigned ColonReg = MatchRegisterName(ColonSplit.first.lower());
1266 if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1267 Lexer.UnLex(Lookahead.back());
1268 Lookahead.pop_back();
1269 Lexer.UnLex(Lookahead.back());
1270 Lookahead.pop_back();
1272 EndLoc = Lexer.getLoc();
1273 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1277 while (!Lookahead.empty()) {
1278 Lexer.UnLex(Lookahead.back());
1279 Lookahead.pop_back();
1284 bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) {
1285 if (previousEqual(Operands, 0, "call"))
1287 if (previousEqual(Operands, 0, "jump"))
1288 if (!getLexer().getTok().is(AsmToken::Colon))
1290 if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1))
1292 if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") &&
1293 (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t")))
1298 bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {
1299 llvm::SmallVector<AsmToken, 4> Tokens;
1300 MCAsmLexer &Lexer = getLexer();
1302 static char const * Comma = ",";
1304 Tokens.emplace_back (Lexer.getTok());
1306 switch (Tokens.back().getKind())
1308 case AsmToken::TokenKind::Hash:
1309 if (Tokens.size () > 1)
1310 if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) {
1311 Tokens.insert(Tokens.end() - 2,
1312 AsmToken(AsmToken::TokenKind::Comma, Comma));
1316 case AsmToken::TokenKind::RCurly:
1317 case AsmToken::TokenKind::EndOfStatement:
1318 case AsmToken::TokenKind::Eof:
1325 while (!Tokens.empty()) {
1326 Lexer.UnLex(Tokens.back());
1329 return getParser().parseExpression(Expr);
1332 bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
1333 if (implicitExpressionLocation(Operands)) {
1334 MCAsmParser &Parser = getParser();
1335 SMLoc Loc = Parser.getLexer().getLoc();
1336 std::unique_ptr<HexagonOperand> Expr =
1337 HexagonOperand::CreateImm(nullptr, Loc, Loc);
1338 MCExpr const *& Val = Expr->Imm.Val;
1339 Operands.push_back(std::move(Expr));
1340 return parseExpression(Val);
1342 return parseOperand(Operands);
1345 /// Parse an instruction.
1346 bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
1347 MCAsmParser &Parser = getParser();
1348 MCAsmLexer &Lexer = getLexer();
1350 AsmToken const &Token = Parser.getTok();
1351 switch (Token.getKind()) {
1352 case AsmToken::EndOfStatement: {
1356 case AsmToken::LCurly: {
1357 if (!Operands.empty())
1360 HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1364 case AsmToken::RCurly: {
1365 if (Operands.empty()) {
1367 HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1372 case AsmToken::Comma: {
1376 case AsmToken::EqualEqual:
1377 case AsmToken::ExclaimEqual:
1378 case AsmToken::GreaterEqual:
1379 case AsmToken::GreaterGreater:
1380 case AsmToken::LessEqual:
1381 case AsmToken::LessLess: {
1382 Operands.push_back(HexagonOperand::CreateToken(
1383 Token.getString().substr(0, 1), Token.getLoc()));
1384 Operands.push_back(HexagonOperand::CreateToken(
1385 Token.getString().substr(1, 1), Token.getLoc()));
1389 case AsmToken::Hash: {
1390 bool MustNotExtend = false;
1391 bool ImplicitExpression = implicitExpressionLocation(Operands);
1392 std::unique_ptr<HexagonOperand> Expr = HexagonOperand::CreateImm(
1393 nullptr, Lexer.getLoc(), Lexer.getLoc());
1394 if (!ImplicitExpression)
1396 HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1398 bool MustExtend = false;
1399 bool HiOnly = false;
1400 bool LoOnly = false;
1401 if (Lexer.is(AsmToken::Hash)) {
1404 } else if (ImplicitExpression)
1405 MustNotExtend = true;
1406 AsmToken const &Token = Parser.getTok();
1407 if (Token.is(AsmToken::Identifier)) {
1408 StringRef String = Token.getString();
1409 AsmToken IDToken = Token;
1410 if (String.lower() == "hi") {
1412 } else if (String.lower() == "lo") {
1415 if (HiOnly || LoOnly) {
1416 AsmToken LParen = Lexer.peekTok();
1417 if (!LParen.is(AsmToken::LParen)) {
1425 if (parseExpression(Expr->Imm.Val))
1428 MCContext &Context = Parser.getContext();
1429 assert(Expr->Imm.Val != nullptr);
1430 if (Expr->Imm.Val->evaluateAsAbsolute(Value)) {
1432 Expr->Imm.Val = MCBinaryExpr::createLShr(
1433 Expr->Imm.Val, MCConstantExpr::create(16, Context), Context);
1434 if (HiOnly || LoOnly)
1435 Expr->Imm.Val = MCBinaryExpr::createAnd(
1436 Expr->Imm.Val, MCConstantExpr::create(0xffff, Context), Context);
1439 Expr->Imm.Val = HexagonNoExtendOperand::Create(Expr->Imm.Val, Context);
1440 Expr->Imm.MustExtend = MustExtend;
1441 Operands.push_back(std::move(Expr));
1447 if (parseExpressionOrOperand(Operands))
1452 bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1455 OperandVector &Operands) {
1456 getLexer().UnLex(ID);
1457 return parseInstruction(Operands);
1461 MCInst makeCombineInst(int opCode, MCOperand &Rdd,
1462 MCOperand &MO1, MCOperand &MO2) {
1464 TmpInst.setOpcode(opCode);
1465 TmpInst.addOperand(Rdd);
1466 TmpInst.addOperand(MO1);
1467 TmpInst.addOperand(MO2);
1473 // Define this matcher function after the auto-generated include so we
1474 // have the match class enum definitions.
1475 unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1477 HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp);
1482 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0
1484 : Match_InvalidOperand;
1488 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1
1490 : Match_InvalidOperand;
1492 case MCK__MINUS_1: {
1494 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == -1
1496 : Match_InvalidOperand;
1499 if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) {
1500 StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length);
1501 if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind)
1502 return Match_Success;
1503 if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind)
1504 return Match_Success;
1507 DEBUG(dbgs() << "Unmatched Operand:");
1509 DEBUG(dbgs() << "\n");
1511 return Match_InvalidOperand;
1514 void HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
1515 std::stringstream errStr;
1516 errStr << "value " << Val << "(0x" << std::hex << Val << std::dec
1517 << ") out of range: ";
1519 errStr << "0-" << Max;
1521 errStr << Max << "-" << (-Max - 1);
1522 Error(IDLoc, errStr.str().c_str());
1525 int HexagonAsmParser::processInstruction(MCInst &Inst,
1526 OperandVector const &Operands,
1527 SMLoc IDLoc, bool &MustExtend) {
1528 MCContext &Context = getParser().getContext();
1529 const MCRegisterInfo *RI = getContext().getRegisterInfo();
1530 std::string r = "r";
1531 std::string v = "v";
1532 std::string Colon = ":";
1534 bool is32bit = false; // used to distinguish between CONST32 and CONST64
1535 switch (Inst.getOpcode()) {
1539 case Hexagon::M4_mpyrr_addr:
1540 case Hexagon::S4_addi_asl_ri:
1541 case Hexagon::S4_addi_lsr_ri:
1542 case Hexagon::S4_andi_asl_ri:
1543 case Hexagon::S4_andi_lsr_ri:
1544 case Hexagon::S4_ori_asl_ri:
1545 case Hexagon::S4_ori_lsr_ri:
1546 case Hexagon::S4_or_andix:
1547 case Hexagon::S4_subi_asl_ri:
1548 case Hexagon::S4_subi_lsr_ri: {
1549 MCOperand &Ry = Inst.getOperand(0);
1550 MCOperand &src = Inst.getOperand(2);
1551 if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg()))
1552 return Match_InvalidOperand;
1556 case Hexagon::C2_cmpgei: {
1557 MCOperand &MO = Inst.getOperand(2);
1558 MO.setExpr(MCBinaryExpr::createSub(
1559 MO.getExpr(), MCConstantExpr::create(1, Context), Context));
1560 Inst.setOpcode(Hexagon::C2_cmpgti);
1564 case Hexagon::C2_cmpgeui: {
1565 MCOperand &MO = Inst.getOperand(2);
1567 bool Success = MO.getExpr()->evaluateAsAbsolute(Value);
1568 assert(Success && "Assured by matcher"); (void)Success;
1571 MCOperand &Pd = Inst.getOperand(0);
1572 MCOperand &Rt = Inst.getOperand(1);
1573 TmpInst.setOpcode(Hexagon::C2_cmpeq);
1574 TmpInst.addOperand(Pd);
1575 TmpInst.addOperand(Rt);
1576 TmpInst.addOperand(Rt);
1579 MO.setExpr(MCBinaryExpr::createSub(
1580 MO.getExpr(), MCConstantExpr::create(1, Context), Context));
1581 Inst.setOpcode(Hexagon::C2_cmpgtui);
1585 case Hexagon::J2_loop1r:
1586 case Hexagon::J2_loop1i:
1587 case Hexagon::J2_loop0r:
1588 case Hexagon::J2_loop0i: {
1589 MCOperand &MO = Inst.getOperand(0);
1590 // Loop has different opcodes for extended vs not extended, but we should
1591 // not use the other opcode as it is a legacy artifact of TD files.
1593 if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1594 // if the the operand can fit within a 7:2 field
1595 if (Value < (1 << 8) && Value >= -(1 << 8)) {
1596 SMLoc myLoc = Operands[2]->getStartLoc();
1597 // # is left in startLoc in the case of ##
1598 // If '##' found then force extension.
1599 if (*myLoc.getPointer() == '#') {
1604 // If immediate and out of 7:2 range.
1611 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1612 case Hexagon::A2_tfrp: {
1613 MCOperand &MO = Inst.getOperand(1);
1614 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1615 std::string R1 = r + llvm::utostr_32(RegPairNum + 1);
1617 MO.setReg(MatchRegisterName(Reg1));
1618 // Add a new operand for the second register in the pair.
1619 std::string R2 = r + llvm::utostr_32(RegPairNum);
1621 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
1622 Inst.setOpcode(Hexagon::A2_combinew);
1626 case Hexagon::A2_tfrpt:
1627 case Hexagon::A2_tfrpf: {
1628 MCOperand &MO = Inst.getOperand(2);
1629 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1630 std::string R1 = r + llvm::utostr_32(RegPairNum + 1);
1632 MO.setReg(MatchRegisterName(Reg1));
1633 // Add a new operand for the second register in the pair.
1634 std::string R2 = r + llvm::utostr_32(RegPairNum);
1636 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
1637 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
1638 ? Hexagon::C2_ccombinewt
1639 : Hexagon::C2_ccombinewf);
1642 case Hexagon::A2_tfrptnew:
1643 case Hexagon::A2_tfrpfnew: {
1644 MCOperand &MO = Inst.getOperand(2);
1645 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1646 std::string R1 = r + llvm::utostr_32(RegPairNum + 1);
1648 MO.setReg(MatchRegisterName(Reg1));
1649 // Add a new operand for the second register in the pair.
1650 std::string R2 = r + llvm::utostr_32(RegPairNum);
1652 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
1653 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
1654 ? Hexagon::C2_ccombinewnewt
1655 : Hexagon::C2_ccombinewnewf);
1659 // Translate a "$Rx = CONST32(#imm)" to "$Rx = memw(gp+#LABEL) "
1660 case Hexagon::CONST32:
1661 case Hexagon::CONST32_Float_Real:
1662 case Hexagon::CONST32_Int_Real:
1663 case Hexagon::FCONST32_nsdata:
1665 // Translate a "$Rx:y = CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "
1666 case Hexagon::CONST64_Float_Real:
1667 case Hexagon::CONST64_Int_Real:
1669 // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
1670 if (!Parser.getStreamer().hasRawTextSupport()) {
1671 MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
1672 MCOperand &MO_1 = Inst.getOperand(1);
1673 MCOperand &MO_0 = Inst.getOperand(0);
1675 // push section onto section stack
1678 std::string myCharStr;
1679 MCSectionELF *mySection;
1681 // check if this as an immediate or a symbol
1683 bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value);
1685 // Create a new section - one for each constant
1686 // Some or all of the zeros are replaced with the given immediate.
1688 std::string myImmStr = utohexstr(static_cast<uint32_t>(Value));
1689 myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000")
1690 .drop_back(myImmStr.size())
1694 std::string myImmStr = utohexstr(Value);
1695 myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000")
1696 .drop_back(myImmStr.size())
1701 mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1702 ELF::SHF_ALLOC | ELF::SHF_WRITE);
1703 } else if (MO_1.isExpr()) {
1704 // .lita - for expressions
1705 myCharStr = ".lita";
1706 mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1707 ELF::SHF_ALLOC | ELF::SHF_WRITE);
1709 llvm_unreachable("unexpected type of machine operand!");
1711 MES->SwitchSection(mySection);
1712 unsigned byteSize = is32bit ? 4 : 8;
1713 getStreamer().EmitCodeAlignment(byteSize, byteSize);
1717 // for symbols, get rid of prepended ".gnu.linkonce.lx."
1719 // emit symbol if needed
1721 Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16));
1722 if (Sym->isUndefined()) {
1723 getStreamer().EmitLabel(Sym);
1724 getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
1725 getStreamer().EmitIntValue(Value, byteSize);
1727 } else if (MO_1.isExpr()) {
1728 const char *StringStart = 0;
1729 const char *StringEnd = 0;
1730 if (*Operands[4]->getStartLoc().getPointer() == '#') {
1731 StringStart = Operands[5]->getStartLoc().getPointer();
1732 StringEnd = Operands[6]->getStartLoc().getPointer();
1733 } else { // no pound
1734 StringStart = Operands[4]->getStartLoc().getPointer();
1735 StringEnd = Operands[5]->getStartLoc().getPointer();
1738 unsigned size = StringEnd - StringStart;
1739 std::string DotConst = ".CONST_";
1740 Sym = getContext().getOrCreateSymbol(DotConst +
1741 StringRef(StringStart, size));
1743 if (Sym->isUndefined()) {
1744 // case where symbol is not yet defined: emit symbol
1745 getStreamer().EmitLabel(Sym);
1746 getStreamer().EmitSymbolAttribute(Sym, MCSA_Local);
1747 getStreamer().EmitValue(MO_1.getExpr(), 4);
1750 llvm_unreachable("unexpected type of machine operand!");
1756 if (is32bit) // 32 bit
1757 TmpInst.setOpcode(Hexagon::L2_loadrigp);
1759 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
1761 TmpInst.addOperand(MO_0);
1763 MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext())));
1769 // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)"
1770 case Hexagon::A2_tfrpi: {
1771 MCOperand &Rdd = Inst.getOperand(0);
1772 MCOperand &MO = Inst.getOperand(1);
1774 int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0;
1775 MCOperand imm(MCOperand::createExpr(MCConstantExpr::create(sVal, Context)));
1776 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO);
1780 // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)"
1781 case Hexagon::TFRI64_V4: {
1782 MCOperand &Rdd = Inst.getOperand(0);
1783 MCOperand &MO = Inst.getOperand(1);
1785 if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1786 unsigned long long u64 = Value;
1787 signed int s8 = (u64 >> 32) & 0xFFFFFFFF;
1788 if (s8 < -128 || s8 > 127)
1789 OutOfRange(IDLoc, s8, -128);
1790 MCOperand imm(MCOperand::createExpr(
1791 MCConstantExpr::create(s8, Context))); // upper 32
1792 MCOperand imm2(MCOperand::createExpr(
1793 MCConstantExpr::create(u64 & 0xFFFFFFFF, Context))); // lower 32
1794 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
1796 MCOperand imm(MCOperand::createExpr(
1797 MCConstantExpr::create(0, Context))); // upper 32
1798 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO);
1803 // Handle $Rdd = combine(##imm, #imm)"
1804 case Hexagon::TFRI64_V2_ext: {
1805 MCOperand &Rdd = Inst.getOperand(0);
1806 MCOperand &MO1 = Inst.getOperand(1);
1807 MCOperand &MO2 = Inst.getOperand(2);
1809 if (MO2.getExpr()->evaluateAsAbsolute(Value)) {
1811 if (s8 < -128 || s8 > 127)
1812 OutOfRange(IDLoc, s8, -128);
1814 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);
1818 // Handle $Rdd = combine(#imm, ##imm)"
1819 case Hexagon::A4_combineii: {
1820 MCOperand &Rdd = Inst.getOperand(0);
1821 MCOperand &MO1 = Inst.getOperand(1);
1823 if (MO1.getExpr()->evaluateAsAbsolute(Value)) {
1825 if (s8 < -128 || s8 > 127)
1826 OutOfRange(IDLoc, s8, -128);
1828 MCOperand &MO2 = Inst.getOperand(2);
1829 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);
1833 case Hexagon::S2_tableidxb_goodsyntax: {
1834 Inst.setOpcode(Hexagon::S2_tableidxb);
1838 case Hexagon::S2_tableidxh_goodsyntax: {
1840 MCOperand &Rx = Inst.getOperand(0);
1841 MCOperand &_dst_ = Inst.getOperand(1);
1842 MCOperand &Rs = Inst.getOperand(2);
1843 MCOperand &Imm4 = Inst.getOperand(3);
1844 MCOperand &Imm6 = Inst.getOperand(4);
1845 Imm6.setExpr(MCBinaryExpr::createSub(
1846 Imm6.getExpr(), MCConstantExpr::create(1, Context), Context));
1847 TmpInst.setOpcode(Hexagon::S2_tableidxh);
1848 TmpInst.addOperand(Rx);
1849 TmpInst.addOperand(_dst_);
1850 TmpInst.addOperand(Rs);
1851 TmpInst.addOperand(Imm4);
1852 TmpInst.addOperand(Imm6);
1857 case Hexagon::S2_tableidxw_goodsyntax: {
1859 MCOperand &Rx = Inst.getOperand(0);
1860 MCOperand &_dst_ = Inst.getOperand(1);
1861 MCOperand &Rs = Inst.getOperand(2);
1862 MCOperand &Imm4 = Inst.getOperand(3);
1863 MCOperand &Imm6 = Inst.getOperand(4);
1864 Imm6.setExpr(MCBinaryExpr::createSub(
1865 Imm6.getExpr(), MCConstantExpr::create(2, Context), Context));
1866 TmpInst.setOpcode(Hexagon::S2_tableidxw);
1867 TmpInst.addOperand(Rx);
1868 TmpInst.addOperand(_dst_);
1869 TmpInst.addOperand(Rs);
1870 TmpInst.addOperand(Imm4);
1871 TmpInst.addOperand(Imm6);
1876 case Hexagon::S2_tableidxd_goodsyntax: {
1878 MCOperand &Rx = Inst.getOperand(0);
1879 MCOperand &_dst_ = Inst.getOperand(1);
1880 MCOperand &Rs = Inst.getOperand(2);
1881 MCOperand &Imm4 = Inst.getOperand(3);
1882 MCOperand &Imm6 = Inst.getOperand(4);
1883 Imm6.setExpr(MCBinaryExpr::createSub(
1884 Imm6.getExpr(), MCConstantExpr::create(3, Context), Context));
1885 TmpInst.setOpcode(Hexagon::S2_tableidxd);
1886 TmpInst.addOperand(Rx);
1887 TmpInst.addOperand(_dst_);
1888 TmpInst.addOperand(Rs);
1889 TmpInst.addOperand(Imm4);
1890 TmpInst.addOperand(Imm6);
1895 case Hexagon::M2_mpyui: {
1896 Inst.setOpcode(Hexagon::M2_mpyi);
1899 case Hexagon::M2_mpysmi: {
1901 MCOperand &Rd = Inst.getOperand(0);
1902 MCOperand &Rs = Inst.getOperand(1);
1903 MCOperand &Imm = Inst.getOperand(2);
1905 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1909 if (Value < 0 && Value > -256) {
1910 Imm.setExpr(MCConstantExpr::create(Value * -1, Context));
1911 TmpInst.setOpcode(Hexagon::M2_mpysin);
1912 } else if (Value < 256 && Value >= 0)
1913 TmpInst.setOpcode(Hexagon::M2_mpysip);
1915 return Match_InvalidOperand;
1918 TmpInst.setOpcode(Hexagon::M2_mpysip);
1920 return Match_InvalidOperand;
1922 TmpInst.addOperand(Rd);
1923 TmpInst.addOperand(Rs);
1924 TmpInst.addOperand(Imm);
1929 case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
1930 MCOperand &Imm = Inst.getOperand(2);
1933 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1936 if (Value == 0) { // convert to $Rd = $Rs
1937 TmpInst.setOpcode(Hexagon::A2_tfr);
1938 MCOperand &Rd = Inst.getOperand(0);
1939 MCOperand &Rs = Inst.getOperand(1);
1940 TmpInst.addOperand(Rd);
1941 TmpInst.addOperand(Rs);
1943 Imm.setExpr(MCBinaryExpr::createSub(
1944 Imm.getExpr(), MCConstantExpr::create(1, Context), Context));
1945 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
1946 MCOperand &Rd = Inst.getOperand(0);
1947 MCOperand &Rs = Inst.getOperand(1);
1948 TmpInst.addOperand(Rd);
1949 TmpInst.addOperand(Rs);
1950 TmpInst.addOperand(Imm);
1956 case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
1957 MCOperand &Rdd = Inst.getOperand(0);
1958 MCOperand &Rss = Inst.getOperand(1);
1959 MCOperand &Imm = Inst.getOperand(2);
1961 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1964 if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1])
1966 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1967 std::string R1 = r + llvm::utostr_32(RegPairNum + 1);
1969 Rss.setReg(MatchRegisterName(Reg1));
1970 // Add a new operand for the second register in the pair.
1971 std::string R2 = r + llvm::utostr_32(RegPairNum);
1973 TmpInst.setOpcode(Hexagon::A2_combinew);
1974 TmpInst.addOperand(Rdd);
1975 TmpInst.addOperand(Rss);
1976 TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
1979 Imm.setExpr(MCBinaryExpr::createSub(
1980 Imm.getExpr(), MCConstantExpr::create(1, Context), Context));
1981 Inst.setOpcode(Hexagon::S2_asr_i_p_rnd);
1986 case Hexagon::A4_boundscheck: {
1987 MCOperand &Rs = Inst.getOperand(1);
1988 unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1989 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1990 Inst.setOpcode(Hexagon::A4_boundscheck_hi);
1992 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
1993 StringRef RegPair = Name;
1994 Rs.setReg(MatchRegisterName(RegPair));
1996 Inst.setOpcode(Hexagon::A4_boundscheck_lo);
1998 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);
1999 StringRef RegPair = Name;
2000 Rs.setReg(MatchRegisterName(RegPair));
2005 case Hexagon::A2_addsp: {
2006 MCOperand &Rs = Inst.getOperand(1);
2007 unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
2008 if (RegNum & 1) { // Odd mapped to raw:hi
2009 Inst.setOpcode(Hexagon::A2_addsph);
2011 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
2012 StringRef RegPair = Name;
2013 Rs.setReg(MatchRegisterName(RegPair));
2014 } else { // Even mapped raw:lo
2015 Inst.setOpcode(Hexagon::A2_addspl);
2017 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);
2018 StringRef RegPair = Name;
2019 Rs.setReg(MatchRegisterName(RegPair));
2024 case Hexagon::M2_vrcmpys_s1: {
2025 MCOperand &Rt = Inst.getOperand(2);
2026 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2027 if (RegNum & 1) { // Odd mapped to sat:raw:hi
2028 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
2030 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
2031 StringRef RegPair = Name;
2032 Rt.setReg(MatchRegisterName(RegPair));
2033 } else { // Even mapped sat:raw:lo
2034 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
2036 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);
2037 StringRef RegPair = Name;
2038 Rt.setReg(MatchRegisterName(RegPair));
2043 case Hexagon::M2_vrcmpys_acc_s1: {
2045 MCOperand &Rxx = Inst.getOperand(0);
2046 MCOperand &Rss = Inst.getOperand(2);
2047 MCOperand &Rt = Inst.getOperand(3);
2048 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2049 if (RegNum & 1) { // Odd mapped to sat:raw:hi
2050 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
2052 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
2053 StringRef RegPair = Name;
2054 Rt.setReg(MatchRegisterName(RegPair));
2055 } else { // Even mapped sat:raw:lo
2056 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
2058 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);
2059 StringRef RegPair = Name;
2060 Rt.setReg(MatchRegisterName(RegPair));
2062 // Registers are in different positions
2063 TmpInst.addOperand(Rxx);
2064 TmpInst.addOperand(Rxx);
2065 TmpInst.addOperand(Rss);
2066 TmpInst.addOperand(Rt);
2071 case Hexagon::M2_vrcmpys_s1rp: {
2072 MCOperand &Rt = Inst.getOperand(2);
2073 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2074 if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi
2075 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
2077 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
2078 StringRef RegPair = Name;
2079 Rt.setReg(MatchRegisterName(RegPair));
2080 } else { // Even mapped rnd:sat:raw:lo
2081 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
2083 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);
2084 StringRef RegPair = Name;
2085 Rt.setReg(MatchRegisterName(RegPair));
2090 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
2091 MCOperand &Imm = Inst.getOperand(2);
2093 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
2097 Inst.setOpcode(Hexagon::S2_vsathub);
2099 Imm.setExpr(MCBinaryExpr::createSub(
2100 Imm.getExpr(), MCConstantExpr::create(1, Context), Context));
2101 Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
2106 case Hexagon::S5_vasrhrnd_goodsyntax: {
2107 MCOperand &Rdd = Inst.getOperand(0);
2108 MCOperand &Rss = Inst.getOperand(1);
2109 MCOperand &Imm = Inst.getOperand(2);
2111 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
2116 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
2117 std::string R1 = r + llvm::utostr_32(RegPairNum + 1);
2119 Rss.setReg(MatchRegisterName(Reg1));
2120 // Add a new operand for the second register in the pair.
2121 std::string R2 = r + llvm::utostr_32(RegPairNum);
2123 TmpInst.setOpcode(Hexagon::A2_combinew);
2124 TmpInst.addOperand(Rdd);
2125 TmpInst.addOperand(Rss);
2126 TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
2129 Imm.setExpr(MCBinaryExpr::createSub(
2130 Imm.getExpr(), MCConstantExpr::create(1, Context), Context));
2131 Inst.setOpcode(Hexagon::S5_vasrhrnd);
2136 case Hexagon::A2_not: {
2138 MCOperand &Rd = Inst.getOperand(0);
2139 MCOperand &Rs = Inst.getOperand(1);
2140 TmpInst.setOpcode(Hexagon::A2_subri);
2141 TmpInst.addOperand(Rd);
2143 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
2144 TmpInst.addOperand(Rs);
2150 return Match_Success;