lib/Target/CellSPU/SPUInstrInfo.h

   1 //===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the CellSPU implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef SPU_INSTRUCTIONINFO_H
  15 #define SPU_INSTRUCTIONINFO_H
  16
  17 #include "SPU.h"
  18 #include "llvm/Target/TargetInstrInfo.h"
  19 #include "SPURegisterInfo.h"
  20
  21 namespace llvm {
  22   //! Cell SPU instruction information class
  23   class SPUInstrInfo : public TargetInstrInfoImpl {
  24     SPUTargetMachine &TM;
  25     const SPURegisterInfo RI;
  26   protected:
  27     virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
  28                                             MachineInstr* MI,
  29                                             const SmallVectorImpl<unsigned> &Ops,
  30                                             int FrameIndex) const;
  31
  32     virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
  33                                                 MachineInstr* MI,
  34                                                 const SmallVectorImpl<unsigned> &Ops,
  35                                                 MachineInstr* LoadMI) const {
  36       return 0;
  37     }
  38
  39   public:
  40     explicit SPUInstrInfo(SPUTargetMachine &tm);
  41
  42     /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  43     /// such, whenever a client has an instance of instruction info, it should
  44     /// always be able to get register info as well (through this method).
  45     ///
  46     virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
  47
  48     /// Return true if the instruction is a register to register move and return
  49     /// the source and dest operands and their sub-register indices by reference.
  50     virtual bool isMoveInstr(const MachineInstr &MI,
  51                              unsigned &SrcReg, unsigned &DstReg,
  52                              unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
  53
  54     unsigned isLoadFromStackSlot(const MachineInstr *MI,
  55                                  int &FrameIndex) const;
  56     unsigned isStoreToStackSlot(const MachineInstr *MI,
  57                                 int &FrameIndex) const;
  58
  59     virtual bool copyRegToReg(MachineBasicBlock &MBB,
  60                               MachineBasicBlock::iterator MI,
  61                               unsigned DestReg, unsigned SrcReg,
  62                               const TargetRegisterClass *DestRC,
  63                               const TargetRegisterClass *SrcRC) const;
  64
  65     //! Store a register to a stack slot, based on its register class.
  66     virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  67                                      MachineBasicBlock::iterator MBBI,
  68                                      unsigned SrcReg, bool isKill, int FrameIndex,
  69                                      const TargetRegisterClass *RC) const;
  70
  71     //! Load a register from a stack slot, based on its register class.
  72     virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  73                                       MachineBasicBlock::iterator MBBI,
  74                                       unsigned DestReg, int FrameIndex,
  75                                       const TargetRegisterClass *RC) const;
  76
  77     //! Return true if the specified load or store can be folded
  78     virtual
  79     bool canFoldMemoryOperand(const MachineInstr *MI,
  80                               const SmallVectorImpl<unsigned> &Ops) const;
  81
  82     //! Reverses a branch's condition, returning false on success.
  83     virtual
  84     bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
  85
  86     virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  87                                MachineBasicBlock *&FBB,
  88                                SmallVectorImpl<MachineOperand> &Cond,
  89                                bool AllowModify) const;
  90
  91     virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  92
  93     virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  94                               MachineBasicBlock *FBB,
  95                               const SmallVectorImpl<MachineOperand> &Cond) const;
  96    };
  97 }
  98
  99 #endif