1 //===-- AlphaTargetMachine.cpp - Define TargetMachine for Alpha -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AlphaJITInfo.h"
15 #include "AlphaTargetAsmInfo.h"
16 #include "AlphaTargetMachine.h"
17 #include "llvm/Module.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Target/TargetMachineRegistry.h"
20 #include "llvm/Support/FormattedStream.h"
24 // Register the targets
25 extern Target TheAlphaTarget;
26 static RegisterTarget<AlphaTargetMachine> X(TheAlphaTarget, "alpha",
27 "Alpha [experimental]");
29 // Force static initialization.
30 extern "C" void LLVMInitializeAlphaTarget() { }
32 const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
33 return new AlphaTargetAsmInfo(*this);
36 AlphaTargetMachine::AlphaTargetMachine(const Target &T, const Module &M,
37 const std::string &FS)
38 : LLVMTargetMachine(T),
39 DataLayout("e-f128:128:128"),
40 FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
44 setRelocationModel(Reloc::PIC_);
48 //===----------------------------------------------------------------------===//
49 // Pass Pipeline Configuration
50 //===----------------------------------------------------------------------===//
52 bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
53 CodeGenOpt::Level OptLevel) {
54 PM.add(createAlphaISelDag(*this));
57 bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
58 CodeGenOpt::Level OptLevel) {
59 // Must run branch selection immediately preceding the asm printer
60 PM.add(createAlphaBranchSelectionPass());
61 PM.add(createAlphaLLRPPass(*this));
64 bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
65 CodeGenOpt::Level OptLevel,
67 formatted_raw_ostream &Out) {
68 FunctionPass *Printer = getTarget().createAsmPrinter(Out, *this, Verbose);
70 llvm_report_error("unable to create assembly printer");
74 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
75 CodeGenOpt::Level OptLevel,
76 bool DumpAsm, MachineCodeEmitter &MCE) {
77 PM.add(createAlphaCodeEmitterPass(*this, MCE));
79 addAssemblyEmitter(PM, OptLevel, true, ferrs());
82 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
83 CodeGenOpt::Level OptLevel,
84 bool DumpAsm, JITCodeEmitter &JCE) {
85 PM.add(createAlphaJITCodeEmitterPass(*this, JCE));
87 addAssemblyEmitter(PM, OptLevel, true, ferrs());
90 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
91 CodeGenOpt::Level OptLevel,
92 bool DumpAsm, ObjectCodeEmitter &OCE) {
93 PM.add(createAlphaObjectCodeEmitterPass(*this, OCE));
95 addAssemblyEmitter(PM, OptLevel, true, ferrs());
98 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
99 CodeGenOpt::Level OptLevel,
101 MachineCodeEmitter &MCE) {
102 return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
104 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
105 CodeGenOpt::Level OptLevel,
107 JITCodeEmitter &JCE) {
108 return addCodeEmitter(PM, OptLevel, DumpAsm, JCE);
110 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
111 CodeGenOpt::Level OptLevel,
113 ObjectCodeEmitter &OCE) {
114 return addCodeEmitter(PM, OptLevel, DumpAsm, OCE);