1 //===- AlphaRegisterInfo.cpp - Alpha Register Information ---*- C++ -*-----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/CodeGen/ValueTypes.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/Target/TargetFrameInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/ADT/STLExtras.h"
34 AlphaRegisterInfo::AlphaRegisterInfo()
35 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
39 static const TargetRegisterClass *getClass(unsigned SrcReg) {
40 if (Alpha::FPRCRegisterClass->contains(SrcReg))
41 return Alpha::FPRCRegisterClass;
42 assert(Alpha::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
43 return Alpha::GPRCRegisterClass;
47 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
48 MachineBasicBlock::iterator MI,
49 unsigned SrcReg, int FrameIdx) const {
50 //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
51 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
52 BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx);
53 // assert(0 && "TODO");
57 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MI,
59 unsigned DestReg, int FrameIdx) const{
60 //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
61 //BuildMI(MBB, MI, Alpha::WTF, 0, DestReg);
62 BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx);
63 // assert(0 && "TODO");
66 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator MI,
68 unsigned DestReg, unsigned SrcReg,
69 const TargetRegisterClass *RC) const {
70 // std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
71 if (RC == Alpha::GPRCRegisterClass) {
72 BuildMI(MBB, MI, Alpha::BIS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
73 } else if (RC == Alpha::FPRCRegisterClass) {
74 BuildMI(MBB, MI, Alpha::CPYS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
76 std::cerr << "Attempt to copy register that is not GPR or FPR";
81 //===----------------------------------------------------------------------===//
82 // Stack Frame Processing methods
83 //===----------------------------------------------------------------------===//
85 // hasFP - Return true if the specified function should have a dedicated frame
86 // pointer register. This is true if the function has variable sized allocas or
87 // if frame pointer elimination is disabled.
89 static bool hasFP(MachineFunction &MF) {
90 MachineFrameInfo *MFI = MF.getFrameInfo();
91 return MFI->hasVarSizedObjects();
94 void AlphaRegisterInfo::
95 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator I) const {
99 // If we have a frame pointer, turn the adjcallstackup instruction into a
100 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
102 MachineInstr *Old = I;
103 unsigned Amount = Old->getOperand(0).getImmedValue();
105 // We need to keep the stack aligned properly. To do this, we round the
106 // amount of space needed for the outgoing arguments up to the next
107 // alignment boundary.
108 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
109 Amount = (Amount+Align-1)/Align*Align;
112 // if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
113 // New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
116 // assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
117 // New=BuildMI(X86::ADD32ri, 1, X86::ESP, MachineOperand::UseAndDef)
121 // Replace the pseudo instruction with a new instruction...
130 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
133 // MachineInstr &MI = *II;
134 // MachineBasicBlock &MBB = *MI.getParent();
135 // MachineFunction &MF = *MBB.getParent();
137 // while (!MI.getOperand(i).isFrameIndex()) {
139 // assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
142 // int FrameIndex = MI.getOperand(i).getFrameIndex();
144 // // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
145 // MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
147 // // Take into account whether it's an add or mem instruction
148 // unsigned OffIdx = (i == 2) ? 1 : 2;
150 // // Now add the frame object offset to the offset from r1.
151 // int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
152 // MI.getOperand(OffIdx).getImmedValue();
154 // // If we're not using a Frame Pointer that has been set to the value of the
155 // // SP before having the stack size subtracted from it, then add the stack size
156 // // to Offset to get the correct offset.
157 // Offset += MF.getFrameInfo()->getStackSize();
159 // if (Offset > 32767 || Offset < -32768) {
160 // // Insert a set of r0 with the full offset value before the ld, st, or add
161 // MachineBasicBlock *MBB = MI.getParent();
162 // MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
163 // MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
165 // // convert into indexed form of the instruction
166 // // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
167 // // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
168 // unsigned NewOpcode =
169 // const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
170 // assert(NewOpcode && "No indexed form of load or store available!");
171 // MI.setOpcode(NewOpcode);
172 // MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
173 // MI.SetMachineOperandReg(2, PPC::R0);
175 // MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
181 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
182 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
183 MachineBasicBlock::iterator MBBI = MBB.begin();
184 MachineFrameInfo *MFI = MF.getFrameInfo();
188 MI = BuildMI(Alpha::LDGP, 0);
189 MBB.insert(MBBI, MI);
191 // Get the number of bytes to allocate from the FrameInfo
192 unsigned NumBytes = MFI->getStackSize();
194 // Do we need to allocate space on the stack?
195 if (NumBytes == 0) return;
197 // Add the size of R30 to NumBytes size for the store of R30 to the
199 // std::cerr << "Spillsize of R30 is " << getSpillSize(Alpha::R30) << "\n";
200 // NumBytes = NumBytes + getSpillSize(Alpha::R30)/8;
202 // Update frame info to pretend that this is part of the stack...
203 MFI->setStackSize(NumBytes);
205 // adjust stack pointer: r30 -= numbytes
207 if (NumBytes <= 32767) {
208 MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(-NumBytes).addReg(Alpha::R30);
209 MBB.insert(MBBI, MI);
210 } else if ((unsigned long)NumBytes <= (unsigned long)32767 * (unsigned long)65536) {
211 long y = NumBytes / 65536;
212 if (NumBytes % 65536 > 32767)
214 MI=BuildMI(Alpha::LDAH, 2, Alpha::R30).addImm(-y).addReg(Alpha::R30);
215 MBB.insert(MBBI, MI);
216 MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(-(NumBytes - y * 65536)).addReg(Alpha::R30);
217 MBB.insert(MBBI, MI);
219 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
224 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
225 MachineBasicBlock &MBB) const {
226 const MachineFrameInfo *MFI = MF.getFrameInfo();
227 MachineBasicBlock::iterator MBBI = prior(MBB.end());
229 assert((MBBI->getOpcode() == Alpha::RET || MBBI->getOpcode() == Alpha::RETURN) &&
230 "Can only insert epilog into returning blocks");
232 // Get the number of bytes allocated from the FrameInfo...
233 unsigned NumBytes = MFI->getStackSize();
237 if (NumBytes <= 32767) {
238 MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(NumBytes).addReg(Alpha::R30);
239 MBB.insert(MBBI, MI);
240 } else if ((unsigned long)NumBytes <= (unsigned long)32767 * (unsigned long)65536) {
241 long y = NumBytes / 65536;
242 if (NumBytes % 65536 > 32767)
244 MI=BuildMI(Alpha::LDAH, 2, Alpha::R30).addImm(y).addReg(Alpha::R30);
245 MBB.insert(MBBI, MI);
246 MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(NumBytes - y * 65536).addReg(Alpha::R30);
247 MBB.insert(MBBI, MI);
249 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
255 #include "AlphaGenRegisterInfo.inc"
257 const TargetRegisterClass*
258 AlphaRegisterInfo::getRegClassForType(const Type* Ty) const {
259 switch (Ty->getTypeID()) {
260 default: assert(0 && "Invalid type to getClass!");
262 case Type::SByteTyID:
263 case Type::UByteTyID:
264 case Type::ShortTyID:
265 case Type::UShortTyID:
268 case Type::PointerTyID:
270 case Type::ULongTyID: return &GPRCInstance;
272 case Type::FloatTyID:
273 case Type::DoubleTyID: return &FPRCInstance;
277 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
279 std::string s(RegisterDescriptors[reg].Name);