1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/STLExtras.h"
37 static const int IMM_LOW = -32768;
38 static const int IMM_HIGH = 32767;
39 static const int IMM_MULT = 65536;
41 static long getUpper16(long l)
43 long y = l / IMM_MULT;
44 if (l % IMM_MULT > IMM_HIGH)
49 static long getLower16(long l)
51 long h = getUpper16(l);
52 return l - h * IMM_MULT;
55 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
56 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
62 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI,
64 unsigned SrcReg, int FrameIdx,
65 const TargetRegisterClass *RC) const {
66 //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
67 //<< FrameIdx << "\n";
68 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
69 if (RC == Alpha::F4RCRegisterClass)
70 BuildMI(MBB, MI, TII.get(Alpha::STS))
71 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
72 else if (RC == Alpha::F8RCRegisterClass)
73 BuildMI(MBB, MI, TII.get(Alpha::STT))
74 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
75 else if (RC == Alpha::GPRCRegisterClass)
76 BuildMI(MBB, MI, TII.get(Alpha::STQ))
77 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
83 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI,
85 unsigned DestReg, int FrameIdx,
86 const TargetRegisterClass *RC) const {
87 //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
88 //<< FrameIdx << "\n";
89 if (RC == Alpha::F4RCRegisterClass)
90 BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
91 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
92 else if (RC == Alpha::F8RCRegisterClass)
93 BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
94 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
95 else if (RC == Alpha::GPRCRegisterClass)
96 BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
97 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
102 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
104 int FrameIndex) const {
105 // Make sure this is a reg-reg copy.
106 unsigned Opc = MI->getOpcode();
108 MachineInstr *NewMI = NULL;
115 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
116 if (OpNum == 0) { // move -> store
117 unsigned InReg = MI->getOperand(1).getReg();
118 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
119 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
120 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
122 } else { // load -> move
123 unsigned OutReg = MI->getOperand(0).getReg();
124 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
125 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
126 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
133 NewMI->copyKillDeadInfo(MI);
138 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
139 MachineBasicBlock::iterator MI,
140 unsigned DestReg, unsigned SrcReg,
141 const TargetRegisterClass *RC) const {
142 // std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
143 if (RC == Alpha::GPRCRegisterClass) {
144 BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
145 } else if (RC == Alpha::F4RCRegisterClass) {
146 BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
147 } else if (RC == Alpha::F8RCRegisterClass) {
148 BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
150 std::cerr << "Attempt to copy register that is not GPR or FPR";
155 const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
156 static const unsigned CalleeSaveRegs[] = {
157 Alpha::R9, Alpha::R10,
158 Alpha::R11, Alpha::R12,
159 Alpha::R13, Alpha::R14,
160 Alpha::F2, Alpha::F3,
161 Alpha::F4, Alpha::F5,
162 Alpha::F6, Alpha::F7,
163 Alpha::F8, Alpha::F9, 0
165 return CalleeSaveRegs;
168 const TargetRegisterClass* const*
169 AlphaRegisterInfo::getCalleeSaveRegClasses() const {
170 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
171 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
172 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
173 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
174 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
175 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
176 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
177 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
179 return CalleeSaveRegClasses;
182 //===----------------------------------------------------------------------===//
183 // Stack Frame Processing methods
184 //===----------------------------------------------------------------------===//
186 // hasFP - Return true if the specified function should have a dedicated frame
187 // pointer register. This is true if the function has variable sized allocas or
188 // if frame pointer elimination is disabled.
190 static bool hasFP(const MachineFunction &MF) {
191 MachineFrameInfo *MFI = MF.getFrameInfo();
192 return MFI->hasVarSizedObjects();
195 void AlphaRegisterInfo::
196 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
197 MachineBasicBlock::iterator I) const {
199 // If we have a frame pointer, turn the adjcallstackup instruction into a
200 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
202 MachineInstr *Old = I;
203 uint64_t Amount = Old->getOperand(0).getImmedValue();
205 // We need to keep the stack aligned properly. To do this, we round the
206 // amount of space needed for the outgoing arguments up to the next
207 // alignment boundary.
208 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
209 Amount = (Amount+Align-1)/Align*Align;
212 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
213 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
214 .addImm(-Amount).addReg(Alpha::R30);
216 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
217 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
218 .addImm(Amount).addReg(Alpha::R30);
221 // Replace the pseudo instruction with a new instruction...
229 //Alpha has a slightly funny stack:
232 //fixed locals (and spills, callee saved, etc)
238 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
240 MachineInstr &MI = *II;
241 MachineBasicBlock &MBB = *MI.getParent();
242 MachineFunction &MF = *MBB.getParent();
245 while (!MI.getOperand(i).isFrameIndex()) {
247 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
250 int FrameIndex = MI.getOperand(i).getFrameIndex();
252 // Add the base register of R30 (SP) or R15 (FP).
253 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
255 // Now add the frame object offset to the offset from the virtual frame index.
256 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
258 DEBUG(std::cerr << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
260 Offset += MF.getFrameInfo()->getStackSize();
262 DEBUG(std::cerr << "Corrected Offset " << Offset <<
263 " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
265 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
266 DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: "
268 //so in this case, we need to use a temporary register, and move the
269 //original inst off the SP/FP
271 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
272 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
274 MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
275 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
278 MI.getOperand(i).ChangeToImmediate(Offset);
283 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
284 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
285 MachineBasicBlock::iterator MBBI = MBB.begin();
286 MachineFrameInfo *MFI = MF.getFrameInfo();
289 static int curgpdist = 0;
292 BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
293 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
294 .addReg(Alpha::R27).addImm(++curgpdist);
295 BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
296 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
297 .addReg(Alpha::R29).addImm(curgpdist);
299 //evil const_cast until MO stuff setup to handle const
300 BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
301 .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
303 // Get the number of bytes to allocate from the FrameInfo
304 long NumBytes = MFI->getStackSize();
306 if (MFI->hasCalls() && !FP) {
307 // We reserve argument space for call sites in the function immediately on
308 // entry to the current function. This eliminates the need for add/sub
309 // brackets around call sites.
310 //If there is a frame pointer, then we don't do this
311 NumBytes += MFI->getMaxCallFrameSize();
312 DEBUG(std::cerr << "Added " << MFI->getMaxCallFrameSize()
313 << " to the stack due to calls\n");
317 NumBytes += 8; //reserve space for the old FP
319 // Do we need to allocate space on the stack?
320 if (NumBytes == 0) return;
322 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
323 NumBytes = (NumBytes+Align-1)/Align*Align;
325 // Update frame info to pretend that this is part of the stack...
326 MFI->setStackSize(NumBytes);
328 // adjust stack pointer: r30 -= numbytes
329 NumBytes = -NumBytes;
330 if (NumBytes >= IMM_LOW) {
331 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
333 } else if (getUpper16(NumBytes) >= IMM_LOW) {
334 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
336 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
339 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
343 //now if we need to, save the old FP and set the new
346 BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
347 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
348 //this must be the last instr in the prolog
349 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
350 .addReg(Alpha::R30).addReg(Alpha::R30);
355 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
356 MachineBasicBlock &MBB) const {
357 const MachineFrameInfo *MFI = MF.getFrameInfo();
358 MachineBasicBlock::iterator MBBI = prior(MBB.end());
359 assert(MBBI->getOpcode() == Alpha::RETDAG ||
360 MBBI->getOpcode() == Alpha::RETDAGp
361 && "Can only insert epilog into returning blocks");
365 // Get the number of bytes allocated from the FrameInfo...
366 long NumBytes = MFI->getStackSize();
368 //now if we need to, restore the old FP
371 //copy the FP into the SP (discards allocas)
372 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
375 BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
380 if (NumBytes <= IMM_HIGH) {
381 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
383 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
384 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
385 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
386 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
387 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
389 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
395 unsigned AlphaRegisterInfo::getRARegister() const {
396 assert(0 && "What is the return address register");
400 unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
401 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
404 #include "AlphaGenRegisterInfo.inc"
406 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
408 std::string s(RegisterDescriptors[reg].Name);