1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/STLExtras.h"
37 static const int IMM_LOW = -32768;
38 static const int IMM_HIGH = 32767;
39 static const int IMM_MULT = 65536;
41 static long getUpper16(long l)
43 long y = l / IMM_MULT;
44 if (l % IMM_MULT > IMM_HIGH)
49 static long getLower16(long l)
51 long h = getUpper16(l);
52 return l - h * IMM_MULT;
55 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
56 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
62 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI,
64 unsigned SrcReg, int FrameIdx,
65 const TargetRegisterClass *RC) const {
66 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
67 // << FrameIdx << "\n";
68 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
69 if (RC == Alpha::F4RCRegisterClass)
70 BuildMI(MBB, MI, TII.get(Alpha::STS))
71 .addReg(SrcReg, false, false, true)
72 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
73 else if (RC == Alpha::F8RCRegisterClass)
74 BuildMI(MBB, MI, TII.get(Alpha::STT))
75 .addReg(SrcReg, false, false, true)
76 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
77 else if (RC == Alpha::GPRCRegisterClass)
78 BuildMI(MBB, MI, TII.get(Alpha::STQ))
79 .addReg(SrcReg, false, false, true)
80 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
85 void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
86 SmallVectorImpl<MachineOperand> &Addr,
87 const TargetRegisterClass *RC,
88 SmallVectorImpl<MachineInstr*> &NewMIs) const {
90 if (RC == Alpha::F4RCRegisterClass)
92 else if (RC == Alpha::F8RCRegisterClass)
94 else if (RC == Alpha::GPRCRegisterClass)
98 MachineInstrBuilder MIB =
99 BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, true);
100 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
101 MachineOperand &MO = Addr[i];
103 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
105 MIB.addImm(MO.getImm());
107 NewMIs.push_back(MIB);
111 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
112 MachineBasicBlock::iterator MI,
113 unsigned DestReg, int FrameIdx,
114 const TargetRegisterClass *RC) const {
115 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
116 // << FrameIdx << "\n";
117 if (RC == Alpha::F4RCRegisterClass)
118 BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
119 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
120 else if (RC == Alpha::F8RCRegisterClass)
121 BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
122 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
123 else if (RC == Alpha::GPRCRegisterClass)
124 BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
125 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
130 void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
131 SmallVectorImpl<MachineOperand> &Addr,
132 const TargetRegisterClass *RC,
133 SmallVectorImpl<MachineInstr*> &NewMIs) const {
135 if (RC == Alpha::F4RCRegisterClass)
137 else if (RC == Alpha::F8RCRegisterClass)
139 else if (RC == Alpha::GPRCRegisterClass)
143 MachineInstrBuilder MIB =
144 BuildMI(TII.get(Opc), DestReg);
145 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
146 MachineOperand &MO = Addr[i];
148 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
150 MIB.addImm(MO.getImm());
152 NewMIs.push_back(MIB);
155 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
156 SmallVectorImpl<unsigned> &Ops,
157 int FrameIndex) const {
158 if (Ops.size() != 1) return NULL;
160 // Make sure this is a reg-reg copy.
161 unsigned Opc = MI->getOpcode();
163 MachineInstr *NewMI = NULL;
170 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
171 if (Ops[0] == 0) { // move -> store
172 unsigned InReg = MI->getOperand(1).getReg();
173 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
174 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
175 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
177 } else { // load -> move
178 unsigned OutReg = MI->getOperand(0).getReg();
179 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
180 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
181 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
188 NewMI->copyKillDeadInfo(MI);
193 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
194 MachineBasicBlock::iterator MI,
195 unsigned DestReg, unsigned SrcReg,
196 const TargetRegisterClass *DestRC,
197 const TargetRegisterClass *SrcRC) const {
198 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
199 if (DestRC != SrcRC) {
200 cerr << "Not yet supported!";
204 if (DestRC == Alpha::GPRCRegisterClass) {
205 BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
206 } else if (DestRC == Alpha::F4RCRegisterClass) {
207 BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
208 } else if (DestRC == Alpha::F8RCRegisterClass) {
209 BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
211 cerr << "Attempt to copy register that is not GPR or FPR";
216 void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
217 MachineBasicBlock::iterator I,
219 const MachineInstr *Orig) const {
220 MachineInstr *MI = Orig->clone();
221 MI->getOperand(0).setReg(DestReg);
225 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
227 static const unsigned CalleeSavedRegs[] = {
228 Alpha::R9, Alpha::R10,
229 Alpha::R11, Alpha::R12,
230 Alpha::R13, Alpha::R14,
231 Alpha::F2, Alpha::F3,
232 Alpha::F4, Alpha::F5,
233 Alpha::F6, Alpha::F7,
234 Alpha::F8, Alpha::F9, 0
236 return CalleeSavedRegs;
239 const TargetRegisterClass* const*
240 AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
241 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
242 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
243 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
244 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
245 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
246 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
247 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
248 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
250 return CalleeSavedRegClasses;
253 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
254 BitVector Reserved(getNumRegs());
255 Reserved.set(Alpha::R15);
256 Reserved.set(Alpha::R30);
257 Reserved.set(Alpha::R31);
261 //===----------------------------------------------------------------------===//
262 // Stack Frame Processing methods
263 //===----------------------------------------------------------------------===//
265 // hasFP - Return true if the specified function should have a dedicated frame
266 // pointer register. This is true if the function has variable sized allocas or
267 // if frame pointer elimination is disabled.
269 bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
270 MachineFrameInfo *MFI = MF.getFrameInfo();
271 return MFI->hasVarSizedObjects();
274 void AlphaRegisterInfo::
275 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
276 MachineBasicBlock::iterator I) const {
278 // If we have a frame pointer, turn the adjcallstackup instruction into a
279 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
281 MachineInstr *Old = I;
282 uint64_t Amount = Old->getOperand(0).getImmedValue();
284 // We need to keep the stack aligned properly. To do this, we round the
285 // amount of space needed for the outgoing arguments up to the next
286 // alignment boundary.
287 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
288 Amount = (Amount+Align-1)/Align*Align;
291 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
292 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
293 .addImm(-Amount).addReg(Alpha::R30);
295 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
296 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
297 .addImm(Amount).addReg(Alpha::R30);
300 // Replace the pseudo instruction with a new instruction...
308 //Alpha has a slightly funny stack:
311 //fixed locals (and spills, callee saved, etc)
316 void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
317 int SPAdj, RegScavenger *RS) const {
318 assert(SPAdj == 0 && "Unexpected");
321 MachineInstr &MI = *II;
322 MachineBasicBlock &MBB = *MI.getParent();
323 MachineFunction &MF = *MBB.getParent();
326 while (!MI.getOperand(i).isFrameIndex()) {
328 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
331 int FrameIndex = MI.getOperand(i).getFrameIndex();
333 // Add the base register of R30 (SP) or R15 (FP).
334 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
336 // Now add the frame object offset to the offset from the virtual frame index.
337 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
339 DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n";
341 Offset += MF.getFrameInfo()->getStackSize();
343 DOUT << "Corrected Offset " << Offset
344 << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n";
346 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
347 DOUT << "Unconditionally using R28 for evil purposes Offset: "
349 //so in this case, we need to use a temporary register, and move the
350 //original inst off the SP/FP
352 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
353 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
355 MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
356 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
359 MI.getOperand(i).ChangeToImmediate(Offset);
364 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
365 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
366 MachineBasicBlock::iterator MBBI = MBB.begin();
367 MachineFrameInfo *MFI = MF.getFrameInfo();
370 static int curgpdist = 0;
373 BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
374 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
375 .addReg(Alpha::R27).addImm(++curgpdist);
376 BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
377 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
378 .addReg(Alpha::R29).addImm(curgpdist);
380 //evil const_cast until MO stuff setup to handle const
381 BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
382 .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
384 // Get the number of bytes to allocate from the FrameInfo
385 long NumBytes = MFI->getStackSize();
388 NumBytes += 8; //reserve space for the old FP
390 // Do we need to allocate space on the stack?
391 if (NumBytes == 0) return;
393 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
394 NumBytes = (NumBytes+Align-1)/Align*Align;
396 // Update frame info to pretend that this is part of the stack...
397 MFI->setStackSize(NumBytes);
399 // adjust stack pointer: r30 -= numbytes
400 NumBytes = -NumBytes;
401 if (NumBytes >= IMM_LOW) {
402 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
404 } else if (getUpper16(NumBytes) >= IMM_LOW) {
405 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
407 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
410 cerr << "Too big a stack frame at " << NumBytes << "\n";
414 //now if we need to, save the old FP and set the new
417 BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
418 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
419 //this must be the last instr in the prolog
420 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
421 .addReg(Alpha::R30).addReg(Alpha::R30);
426 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
427 MachineBasicBlock &MBB) const {
428 const MachineFrameInfo *MFI = MF.getFrameInfo();
429 MachineBasicBlock::iterator MBBI = prior(MBB.end());
430 assert(MBBI->getOpcode() == Alpha::RETDAG ||
431 MBBI->getOpcode() == Alpha::RETDAGp
432 && "Can only insert epilog into returning blocks");
436 // Get the number of bytes allocated from the FrameInfo...
437 long NumBytes = MFI->getStackSize();
439 //now if we need to, restore the old FP
442 //copy the FP into the SP (discards allocas)
443 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
446 BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
451 if (NumBytes <= IMM_HIGH) {
452 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
454 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
455 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
456 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
457 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
458 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
460 cerr << "Too big a stack frame at " << NumBytes << "\n";
466 unsigned AlphaRegisterInfo::getRARegister() const {
467 assert(0 && "What is the return address register");
471 unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
472 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
475 unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
476 assert(0 && "What is the exception register");
480 unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
481 assert(0 && "What is the exception handler register");
485 int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
486 assert(0 && "What is the dwarf register number");
490 #include "AlphaGenRegisterInfo.inc"
492 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
494 std::string s(RegisterDescriptors[reg].Name);