1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/STLExtras.h"
37 static const int IMM_LOW = -32768;
38 static const int IMM_HIGH = 32767;
39 static const int IMM_MULT = 65536;
41 static long getUpper16(long l)
43 long y = l / IMM_MULT;
44 if (l % IMM_MULT > IMM_HIGH)
49 static long getLower16(long l)
51 long h = getUpper16(l);
52 return l - h * IMM_MULT;
55 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
56 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
62 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI,
64 unsigned SrcReg, int FrameIdx,
65 const TargetRegisterClass *RC) const {
66 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
67 // << FrameIdx << "\n";
68 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
69 if (RC == Alpha::F4RCRegisterClass)
70 BuildMI(MBB, MI, TII.get(Alpha::STS))
71 .addReg(SrcReg, false, false, true)
72 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
73 else if (RC == Alpha::F8RCRegisterClass)
74 BuildMI(MBB, MI, TII.get(Alpha::STT))
75 .addReg(SrcReg, false, false, true)
76 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
77 else if (RC == Alpha::GPRCRegisterClass)
78 BuildMI(MBB, MI, TII.get(Alpha::STQ))
79 .addReg(SrcReg, false, false, true)
80 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
86 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI,
88 unsigned DestReg, int FrameIdx,
89 const TargetRegisterClass *RC) const {
90 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
91 // << FrameIdx << "\n";
92 if (RC == Alpha::F4RCRegisterClass)
93 BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
94 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
95 else if (RC == Alpha::F8RCRegisterClass)
96 BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
97 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
98 else if (RC == Alpha::GPRCRegisterClass)
99 BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
100 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
105 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
107 int FrameIndex) const {
108 // Make sure this is a reg-reg copy.
109 unsigned Opc = MI->getOpcode();
111 MachineInstr *NewMI = NULL;
118 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
119 if (OpNum == 0) { // move -> store
120 unsigned InReg = MI->getOperand(1).getReg();
121 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
122 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
123 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
125 } else { // load -> move
126 unsigned OutReg = MI->getOperand(0).getReg();
127 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
128 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
129 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
136 NewMI->copyKillDeadInfo(MI);
141 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
142 MachineBasicBlock::iterator MI,
143 unsigned DestReg, unsigned SrcReg,
144 const TargetRegisterClass *DestRC,
145 const TargetRegisterClass *SrcRC) const {
146 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
147 if (DestRC != SrcRC) {
148 cerr << "Not yet supported!";
152 if (DestRC == Alpha::GPRCRegisterClass) {
153 BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
154 } else if (DestRC == Alpha::F4RCRegisterClass) {
155 BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
156 } else if (DestRC == Alpha::F8RCRegisterClass) {
157 BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
159 cerr << "Attempt to copy register that is not GPR or FPR";
164 void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
165 MachineBasicBlock::iterator I,
167 const MachineInstr *Orig) const {
168 MachineInstr *MI = Orig->clone();
169 MI->getOperand(0).setReg(DestReg);
173 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
175 static const unsigned CalleeSavedRegs[] = {
176 Alpha::R9, Alpha::R10,
177 Alpha::R11, Alpha::R12,
178 Alpha::R13, Alpha::R14,
179 Alpha::F2, Alpha::F3,
180 Alpha::F4, Alpha::F5,
181 Alpha::F6, Alpha::F7,
182 Alpha::F8, Alpha::F9, 0
184 return CalleeSavedRegs;
187 const TargetRegisterClass* const*
188 AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
189 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
190 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
191 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
192 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
193 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
194 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
195 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
196 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
198 return CalleeSavedRegClasses;
201 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
202 BitVector Reserved(getNumRegs());
203 Reserved.set(Alpha::R15);
204 Reserved.set(Alpha::R30);
205 Reserved.set(Alpha::R31);
209 //===----------------------------------------------------------------------===//
210 // Stack Frame Processing methods
211 //===----------------------------------------------------------------------===//
213 // hasFP - Return true if the specified function should have a dedicated frame
214 // pointer register. This is true if the function has variable sized allocas or
215 // if frame pointer elimination is disabled.
217 bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
218 MachineFrameInfo *MFI = MF.getFrameInfo();
219 return MFI->hasVarSizedObjects();
222 void AlphaRegisterInfo::
223 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
224 MachineBasicBlock::iterator I) const {
226 // If we have a frame pointer, turn the adjcallstackup instruction into a
227 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
229 MachineInstr *Old = I;
230 uint64_t Amount = Old->getOperand(0).getImmedValue();
232 // We need to keep the stack aligned properly. To do this, we round the
233 // amount of space needed for the outgoing arguments up to the next
234 // alignment boundary.
235 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
236 Amount = (Amount+Align-1)/Align*Align;
239 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
240 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
241 .addImm(-Amount).addReg(Alpha::R30);
243 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
244 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
245 .addImm(Amount).addReg(Alpha::R30);
248 // Replace the pseudo instruction with a new instruction...
256 //Alpha has a slightly funny stack:
259 //fixed locals (and spills, callee saved, etc)
264 void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
265 int SPAdj, RegScavenger *RS) const {
266 assert(SPAdj == 0 && "Unexpected");
269 MachineInstr &MI = *II;
270 MachineBasicBlock &MBB = *MI.getParent();
271 MachineFunction &MF = *MBB.getParent();
274 while (!MI.getOperand(i).isFrameIndex()) {
276 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
279 int FrameIndex = MI.getOperand(i).getFrameIndex();
281 // Add the base register of R30 (SP) or R15 (FP).
282 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
284 // Now add the frame object offset to the offset from the virtual frame index.
285 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
287 DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n";
289 Offset += MF.getFrameInfo()->getStackSize();
291 DOUT << "Corrected Offset " << Offset
292 << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n";
294 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
295 DOUT << "Unconditionally using R28 for evil purposes Offset: "
297 //so in this case, we need to use a temporary register, and move the
298 //original inst off the SP/FP
300 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
301 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
303 MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
304 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
307 MI.getOperand(i).ChangeToImmediate(Offset);
312 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
313 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
314 MachineBasicBlock::iterator MBBI = MBB.begin();
315 MachineFrameInfo *MFI = MF.getFrameInfo();
318 static int curgpdist = 0;
321 BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
322 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
323 .addReg(Alpha::R27).addImm(++curgpdist);
324 BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
325 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
326 .addReg(Alpha::R29).addImm(curgpdist);
328 //evil const_cast until MO stuff setup to handle const
329 BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
330 .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
332 // Get the number of bytes to allocate from the FrameInfo
333 long NumBytes = MFI->getStackSize();
336 NumBytes += 8; //reserve space for the old FP
338 // Do we need to allocate space on the stack?
339 if (NumBytes == 0) return;
341 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
342 NumBytes = (NumBytes+Align-1)/Align*Align;
344 // Update frame info to pretend that this is part of the stack...
345 MFI->setStackSize(NumBytes);
347 // adjust stack pointer: r30 -= numbytes
348 NumBytes = -NumBytes;
349 if (NumBytes >= IMM_LOW) {
350 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
352 } else if (getUpper16(NumBytes) >= IMM_LOW) {
353 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
355 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
358 cerr << "Too big a stack frame at " << NumBytes << "\n";
362 //now if we need to, save the old FP and set the new
365 BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
366 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
367 //this must be the last instr in the prolog
368 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
369 .addReg(Alpha::R30).addReg(Alpha::R30);
374 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
375 MachineBasicBlock &MBB) const {
376 const MachineFrameInfo *MFI = MF.getFrameInfo();
377 MachineBasicBlock::iterator MBBI = prior(MBB.end());
378 assert(MBBI->getOpcode() == Alpha::RETDAG ||
379 MBBI->getOpcode() == Alpha::RETDAGp
380 && "Can only insert epilog into returning blocks");
384 // Get the number of bytes allocated from the FrameInfo...
385 long NumBytes = MFI->getStackSize();
387 //now if we need to, restore the old FP
390 //copy the FP into the SP (discards allocas)
391 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
394 BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
399 if (NumBytes <= IMM_HIGH) {
400 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
402 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
403 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
404 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
405 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
406 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
408 cerr << "Too big a stack frame at " << NumBytes << "\n";
414 unsigned AlphaRegisterInfo::getRARegister() const {
415 assert(0 && "What is the return address register");
419 unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
420 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
423 unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
424 assert(0 && "What is the exception register");
428 unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
429 assert(0 && "What is the exception handler register");
433 #include "AlphaGenRegisterInfo.inc"
435 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
437 std::string s(RegisterDescriptors[reg].Name);