1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/STLExtras.h"
37 static const int IMM_LOW = -32768;
38 static const int IMM_HIGH = 32767;
39 static const int IMM_MULT = 65536;
41 static long getUpper16(long l)
43 long y = l / IMM_MULT;
44 if (l % IMM_MULT > IMM_HIGH)
49 static long getLower16(long l)
51 long h = getUpper16(l);
52 return l - h * IMM_MULT;
55 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
56 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
62 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI,
64 unsigned SrcReg, int FrameIdx,
65 const TargetRegisterClass *RC) const {
66 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
67 // << FrameIdx << "\n";
68 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
69 if (RC == Alpha::F4RCRegisterClass)
70 BuildMI(MBB, MI, TII.get(Alpha::STS))
71 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
72 else if (RC == Alpha::F8RCRegisterClass)
73 BuildMI(MBB, MI, TII.get(Alpha::STT))
74 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
75 else if (RC == Alpha::GPRCRegisterClass)
76 BuildMI(MBB, MI, TII.get(Alpha::STQ))
77 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
83 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI,
85 unsigned DestReg, int FrameIdx,
86 const TargetRegisterClass *RC) const {
87 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
88 // << FrameIdx << "\n";
89 if (RC == Alpha::F4RCRegisterClass)
90 BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
91 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
92 else if (RC == Alpha::F8RCRegisterClass)
93 BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
94 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
95 else if (RC == Alpha::GPRCRegisterClass)
96 BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
97 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
102 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
104 int FrameIndex) const {
105 // Make sure this is a reg-reg copy.
106 unsigned Opc = MI->getOpcode();
108 MachineInstr *NewMI = NULL;
115 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
116 if (OpNum == 0) { // move -> store
117 unsigned InReg = MI->getOperand(1).getReg();
118 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
119 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
120 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
122 } else { // load -> move
123 unsigned OutReg = MI->getOperand(0).getReg();
124 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
125 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
126 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
133 NewMI->copyKillDeadInfo(MI);
138 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
139 MachineBasicBlock::iterator MI,
140 unsigned DestReg, unsigned SrcReg,
141 const TargetRegisterClass *RC) const {
142 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
143 if (RC == Alpha::GPRCRegisterClass) {
144 BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
145 } else if (RC == Alpha::F4RCRegisterClass) {
146 BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
147 } else if (RC == Alpha::F8RCRegisterClass) {
148 BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
150 cerr << "Attempt to copy register that is not GPR or FPR";
155 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs() const {
156 static const unsigned CalleeSavedRegs[] = {
157 Alpha::R9, Alpha::R10,
158 Alpha::R11, Alpha::R12,
159 Alpha::R13, Alpha::R14,
160 Alpha::F2, Alpha::F3,
161 Alpha::F4, Alpha::F5,
162 Alpha::F6, Alpha::F7,
163 Alpha::F8, Alpha::F9, 0
165 return CalleeSavedRegs;
168 const TargetRegisterClass* const*
169 AlphaRegisterInfo::getCalleeSavedRegClasses() const {
170 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
171 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
172 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
173 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
174 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
175 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
176 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
177 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
179 return CalleeSavedRegClasses;
182 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
183 BitVector Reserved(getNumRegs());
184 Reserved.set(Alpha::R15);
185 Reserved.set(Alpha::R30);
186 Reserved.set(Alpha::R31);
190 //===----------------------------------------------------------------------===//
191 // Stack Frame Processing methods
192 //===----------------------------------------------------------------------===//
194 // hasFP - Return true if the specified function should have a dedicated frame
195 // pointer register. This is true if the function has variable sized allocas or
196 // if frame pointer elimination is disabled.
198 bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
199 MachineFrameInfo *MFI = MF.getFrameInfo();
200 return MFI->hasVarSizedObjects();
203 void AlphaRegisterInfo::
204 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
205 MachineBasicBlock::iterator I) const {
207 // If we have a frame pointer, turn the adjcallstackup instruction into a
208 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
210 MachineInstr *Old = I;
211 uint64_t Amount = Old->getOperand(0).getImmedValue();
213 // We need to keep the stack aligned properly. To do this, we round the
214 // amount of space needed for the outgoing arguments up to the next
215 // alignment boundary.
216 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
217 Amount = (Amount+Align-1)/Align*Align;
220 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
221 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
222 .addImm(-Amount).addReg(Alpha::R30);
224 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
225 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
226 .addImm(Amount).addReg(Alpha::R30);
229 // Replace the pseudo instruction with a new instruction...
237 //Alpha has a slightly funny stack:
240 //fixed locals (and spills, callee saved, etc)
246 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
248 MachineInstr &MI = *II;
249 MachineBasicBlock &MBB = *MI.getParent();
250 MachineFunction &MF = *MBB.getParent();
253 while (!MI.getOperand(i).isFrameIndex()) {
255 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
258 int FrameIndex = MI.getOperand(i).getFrameIndex();
260 // Add the base register of R30 (SP) or R15 (FP).
261 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
263 // Now add the frame object offset to the offset from the virtual frame index.
264 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
266 DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n";
268 Offset += MF.getFrameInfo()->getStackSize();
270 DOUT << "Corrected Offset " << Offset
271 << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n";
273 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
274 DOUT << "Unconditionally using R28 for evil purposes Offset: "
276 //so in this case, we need to use a temporary register, and move the
277 //original inst off the SP/FP
279 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
280 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
282 MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
283 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
286 MI.getOperand(i).ChangeToImmediate(Offset);
291 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
292 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
293 MachineBasicBlock::iterator MBBI = MBB.begin();
294 MachineFrameInfo *MFI = MF.getFrameInfo();
297 static int curgpdist = 0;
300 BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
301 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
302 .addReg(Alpha::R27).addImm(++curgpdist);
303 BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
304 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
305 .addReg(Alpha::R29).addImm(curgpdist);
307 //evil const_cast until MO stuff setup to handle const
308 BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
309 .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
311 // Get the number of bytes to allocate from the FrameInfo
312 long NumBytes = MFI->getStackSize();
315 NumBytes += 8; //reserve space for the old FP
317 // Do we need to allocate space on the stack?
318 if (NumBytes == 0) return;
320 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
321 NumBytes = (NumBytes+Align-1)/Align*Align;
323 // Update frame info to pretend that this is part of the stack...
324 MFI->setStackSize(NumBytes);
326 // adjust stack pointer: r30 -= numbytes
327 NumBytes = -NumBytes;
328 if (NumBytes >= IMM_LOW) {
329 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
331 } else if (getUpper16(NumBytes) >= IMM_LOW) {
332 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
334 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
337 cerr << "Too big a stack frame at " << NumBytes << "\n";
341 //now if we need to, save the old FP and set the new
344 BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
345 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
346 //this must be the last instr in the prolog
347 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
348 .addReg(Alpha::R30).addReg(Alpha::R30);
353 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
354 MachineBasicBlock &MBB) const {
355 const MachineFrameInfo *MFI = MF.getFrameInfo();
356 MachineBasicBlock::iterator MBBI = prior(MBB.end());
357 assert(MBBI->getOpcode() == Alpha::RETDAG ||
358 MBBI->getOpcode() == Alpha::RETDAGp
359 && "Can only insert epilog into returning blocks");
363 // Get the number of bytes allocated from the FrameInfo...
364 long NumBytes = MFI->getStackSize();
366 //now if we need to, restore the old FP
369 //copy the FP into the SP (discards allocas)
370 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
373 BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
378 if (NumBytes <= IMM_HIGH) {
379 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
381 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
382 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
383 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
384 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
385 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
387 cerr << "Too big a stack frame at " << NumBytes << "\n";
393 unsigned AlphaRegisterInfo::getRARegister() const {
394 assert(0 && "What is the return address register");
398 unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
399 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
402 unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
403 assert(0 && "What is the exception register");
407 unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
408 assert(0 && "What is the exception handler register");
412 #include "AlphaGenRegisterInfo.inc"
414 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
416 std::string s(RegisterDescriptors[reg].Name);