1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/ADT/STLExtras.h"
36 static const int IMM_LOW = -32768;
37 static const int IMM_HIGH = 32767;
38 static const int IMM_MULT = 65536;
40 static long getUpper16(long l)
42 long y = l / IMM_MULT;
43 if (l % IMM_MULT > IMM_HIGH)
48 static long getLower16(long l)
50 long h = getUpper16(l);
51 return l - h * IMM_MULT;
54 AlphaRegisterInfo::AlphaRegisterInfo()
55 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
60 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MI,
62 unsigned SrcReg, int FrameIdx,
63 const TargetRegisterClass *RC) const {
64 //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
65 //<< FrameIdx << "\n";
66 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
67 if (RC == Alpha::F4RCRegisterClass)
68 BuildMI(MBB, MI, Alpha::STS, 3)
69 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
70 else if (RC == Alpha::F8RCRegisterClass)
71 BuildMI(MBB, MI, Alpha::STT, 3)
72 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
73 else if (RC == Alpha::GPRCRegisterClass)
74 BuildMI(MBB, MI, Alpha::STQ, 3)
75 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
81 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MI,
83 unsigned DestReg, int FrameIdx,
84 const TargetRegisterClass *RC) const {
85 //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
86 //<< FrameIdx << "\n";
87 if (RC == Alpha::F4RCRegisterClass)
88 BuildMI(MBB, MI, Alpha::LDS, 2, DestReg)
89 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
90 else if (RC == Alpha::F8RCRegisterClass)
91 BuildMI(MBB, MI, Alpha::LDT, 2, DestReg)
92 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
93 else if (RC == Alpha::GPRCRegisterClass)
94 BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg)
95 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
100 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
102 int FrameIndex) const {
103 // Make sure this is a reg-reg copy.
104 unsigned Opc = MI->getOpcode();
112 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
113 if (OpNum == 0) { // move -> store
114 unsigned InReg = MI->getOperand(1).getReg();
115 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
116 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
117 return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
119 } else { // load -> move
120 unsigned OutReg = MI->getOperand(0).getReg();
121 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
122 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
123 return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex)
133 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
134 MachineBasicBlock::iterator MI,
135 unsigned DestReg, unsigned SrcReg,
136 const TargetRegisterClass *RC) const {
137 // std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
138 if (RC == Alpha::GPRCRegisterClass) {
139 BuildMI(MBB, MI, Alpha::BISr, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
140 } else if (RC == Alpha::F4RCRegisterClass) {
141 BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
142 } else if (RC == Alpha::F8RCRegisterClass) {
143 BuildMI(MBB, MI, Alpha::CPYST, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
145 std::cerr << "Attempt to copy register that is not GPR or FPR";
150 const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
151 static const unsigned CalleeSaveRegs[] = {
152 Alpha::R9, Alpha::R10,
153 Alpha::R11, Alpha::R12,
154 Alpha::R13, Alpha::R14,
155 Alpha::F2, Alpha::F3,
156 Alpha::F4, Alpha::F5,
157 Alpha::F6, Alpha::F7,
158 Alpha::F8, Alpha::F9, 0
160 return CalleeSaveRegs;
163 const TargetRegisterClass* const*
164 AlphaRegisterInfo::getCalleeSaveRegClasses() const {
165 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
166 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
167 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
168 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
169 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
170 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
171 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
172 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
174 return CalleeSaveRegClasses;
177 //===----------------------------------------------------------------------===//
178 // Stack Frame Processing methods
179 //===----------------------------------------------------------------------===//
181 // hasFP - Return true if the specified function should have a dedicated frame
182 // pointer register. This is true if the function has variable sized allocas or
183 // if frame pointer elimination is disabled.
185 static bool hasFP(const MachineFunction &MF) {
186 MachineFrameInfo *MFI = MF.getFrameInfo();
187 return MFI->hasVarSizedObjects();
190 void AlphaRegisterInfo::
191 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
192 MachineBasicBlock::iterator I) const {
194 // If we have a frame pointer, turn the adjcallstackup instruction into a
195 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
197 MachineInstr *Old = I;
198 uint64_t Amount = Old->getOperand(0).getImmedValue();
200 // We need to keep the stack aligned properly. To do this, we round the
201 // amount of space needed for the outgoing arguments up to the next
202 // alignment boundary.
203 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
204 Amount = (Amount+Align-1)/Align*Align;
207 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
208 New=BuildMI(Alpha::LDA, 2, Alpha::R30)
209 .addImm(-Amount).addReg(Alpha::R30);
211 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
212 New=BuildMI(Alpha::LDA, 2, Alpha::R30)
213 .addImm(Amount).addReg(Alpha::R30);
216 // Replace the pseudo instruction with a new instruction...
224 //Alpha has a slightly funny stack:
227 //fixed locals (and spills, callee saved, etc)
233 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
235 MachineInstr &MI = *II;
236 MachineBasicBlock &MBB = *MI.getParent();
237 MachineFunction &MF = *MBB.getParent();
240 while (!MI.getOperand(i).isFrameIndex()) {
242 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
245 int FrameIndex = MI.getOperand(i).getFrameIndex();
247 // Add the base register of R30 (SP) or R15 (FP).
248 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
250 // Now add the frame object offset to the offset from the virtual frame index.
251 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
253 DEBUG(std::cerr << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
255 Offset += MF.getFrameInfo()->getStackSize();
257 DEBUG(std::cerr << "Corrected Offset " << Offset <<
258 " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
260 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
261 DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: "
263 //so in this case, we need to use a temporary register, and move the
264 //original inst off the SP/FP
266 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
267 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
269 MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
270 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
273 MI.getOperand(i).ChangeToImmediate(Offset);
278 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
279 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
280 MachineBasicBlock::iterator MBBI = MBB.begin();
281 MachineFrameInfo *MFI = MF.getFrameInfo();
284 static int curgpdist = 0;
287 BuildMI(MBB, MBBI, Alpha::LDAHg, 3, Alpha::R29)
288 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
289 .addReg(Alpha::R27).addImm(++curgpdist);
290 BuildMI(MBB, MBBI, Alpha::LDAg, 3, Alpha::R29)
291 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
292 .addReg(Alpha::R29).addImm(curgpdist);
294 //evil const_cast until MO stuff setup to handle const
295 BuildMI(MBB, MBBI, Alpha::ALTENT, 1)
296 .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
298 // Get the number of bytes to allocate from the FrameInfo
299 long NumBytes = MFI->getStackSize();
301 if (MFI->hasCalls() && !FP) {
302 // We reserve argument space for call sites in the function immediately on
303 // entry to the current function. This eliminates the need for add/sub
304 // brackets around call sites.
305 //If there is a frame pointer, then we don't do this
306 NumBytes += MFI->getMaxCallFrameSize();
307 DEBUG(std::cerr << "Added " << MFI->getMaxCallFrameSize()
308 << " to the stack due to calls\n");
312 NumBytes += 8; //reserve space for the old FP
314 // Do we need to allocate space on the stack?
315 if (NumBytes == 0) return;
317 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
318 NumBytes = (NumBytes+Align-1)/Align*Align;
320 // Update frame info to pretend that this is part of the stack...
321 MFI->setStackSize(NumBytes);
323 // adjust stack pointer: r30 -= numbytes
324 NumBytes = -NumBytes;
325 if (NumBytes >= IMM_LOW) {
326 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
328 } else if (getUpper16(NumBytes) >= IMM_LOW) {
329 BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30).addImm(getUpper16(NumBytes))
331 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(getLower16(NumBytes))
334 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
338 //now if we need to, save the old FP and set the new
341 BuildMI(MBB, MBBI, Alpha::STQ, 3)
342 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
343 //this must be the last instr in the prolog
344 BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R15)
345 .addReg(Alpha::R30).addReg(Alpha::R30);
350 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
351 MachineBasicBlock &MBB) const {
352 const MachineFrameInfo *MFI = MF.getFrameInfo();
353 MachineBasicBlock::iterator MBBI = prior(MBB.end());
354 assert(MBBI->getOpcode() == Alpha::RETDAG ||
355 MBBI->getOpcode() == Alpha::RETDAGp
356 && "Can only insert epilog into returning blocks");
360 // Get the number of bytes allocated from the FrameInfo...
361 long NumBytes = MFI->getStackSize();
363 //now if we need to, restore the old FP
366 //copy the FP into the SP (discards allocas)
367 BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R30).addReg(Alpha::R15)
370 BuildMI(MBB, MBBI, Alpha::LDQ, 2, Alpha::R15).addImm(0).addReg(Alpha::R15);
375 if (NumBytes <= IMM_HIGH) {
376 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
378 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
379 BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30)
380 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
381 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30)
382 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
384 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
390 unsigned AlphaRegisterInfo::getRARegister() const {
391 assert(0 && "What is the return address register");
395 unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
396 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
399 #include "AlphaGenRegisterInfo.inc"
401 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
403 std::string s(RegisterDescriptors[reg].Name);