1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Support/CommandLine.h"
29 extern cl::opt<bool> EnableAlphaIDIV;
30 extern cl::opt<bool> EnableAlphaCount;
31 extern cl::opt<bool> EnableAlphaLSMark;
34 /// AddLiveIn - This helper function adds the specified physical register to the
35 /// MachineFunction as a live in value. It also creates a corresponding virtual
37 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
38 TargetRegisterClass *RC) {
39 assert(RC->contains(PReg) && "Not the correct regclass!");
40 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
41 MF.addLiveIn(PReg, VReg);
45 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
46 // Set up the TargetLowering object.
47 //I am having problems with shr n ubyte 1
48 setShiftAmountType(MVT::i64);
49 setSetCCResultType(MVT::i64);
50 setSetCCResultContents(ZeroOrOneSetCCResult);
52 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
53 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
54 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
56 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
57 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
59 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
60 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
62 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
63 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
65 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
66 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
67 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
69 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
71 setOperationAction(ISD::FREM, MVT::f32, Expand);
72 setOperationAction(ISD::FREM, MVT::f64, Expand);
74 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
75 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
76 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
77 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
79 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
80 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
81 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
82 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
84 setOperationAction(ISD::ROTL , MVT::i64, Expand);
85 setOperationAction(ISD::ROTR , MVT::i64, Expand);
87 setOperationAction(ISD::SREM , MVT::i64, Custom);
88 setOperationAction(ISD::UREM , MVT::i64, Custom);
89 setOperationAction(ISD::SDIV , MVT::i64, Custom);
90 setOperationAction(ISD::UDIV , MVT::i64, Custom);
92 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
93 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
94 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
96 // We don't support sin/cos/sqrt
97 setOperationAction(ISD::FSIN , MVT::f64, Expand);
98 setOperationAction(ISD::FCOS , MVT::f64, Expand);
99 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
100 setOperationAction(ISD::FSIN , MVT::f32, Expand);
101 setOperationAction(ISD::FCOS , MVT::f32, Expand);
102 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
104 setOperationAction(ISD::SETCC, MVT::f32, Promote);
106 // We don't have line number support yet.
107 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
108 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
109 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
111 // We want to legalize GlobalAddress and ConstantPool and
112 // ExternalSymbols nodes into the appropriate instructions to
113 // materialize the address.
114 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
115 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
116 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
118 addLegalFPImmediate(+0.0); //F31
119 addLegalFPImmediate(-0.0); //-F31
121 computeRegisterProperties();
123 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
127 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
129 //For now, just use variable size stack frame format
131 //In a standard call, the first six items are passed in registers $16
132 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
133 //of argument-to-register correspondence.) The remaining items are
134 //collected in a memory argument list that is a naturally aligned
135 //array of quadwords. In a standard call, this list, if present, must
136 //be passed at 0(SP).
137 //7 ... n 0(SP) ... (n-7)*8(SP)
145 std::vector<SDOperand>
146 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
148 MachineFunction &MF = DAG.getMachineFunction();
149 MachineFrameInfo *MFI = MF.getFrameInfo();
150 MachineBasicBlock& BB = MF.front();
151 std::vector<SDOperand> ArgValues;
153 unsigned args_int[] = {
154 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
155 unsigned args_float[] = {
156 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
160 GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
161 RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
163 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
168 MVT::ValueType VT = getValueType(I->getType());
171 std::cerr << "Unknown Type " << VT << "\n";
175 args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
176 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
177 DAG.setRoot(argt.getValue(1));
184 args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
185 argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
186 DAG.setRoot(argt.getValue(1));
187 if (VT != MVT::i64) {
189 I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
190 argt = DAG.getNode(AssertOp, MVT::i64, argt,
191 DAG.getValueType(VT));
192 argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
197 // Create the frame index object for this incoming parameter...
198 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
200 // Create the SelectionDAG nodes corresponding to a load
201 //from this parameter
202 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
203 argt = DAG.getLoad(getValueType(I->getType()),
204 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
207 ArgValues.push_back(argt);
210 // If the functions takes variable number of arguments, copy all regs to stack
212 VarArgsOffset = count * 8;
213 std::vector<SDOperand> LS;
214 for (int i = 0; i < 6; ++i) {
215 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
216 args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
217 SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
218 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
219 if (i == 0) VarArgsBase = FI;
220 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
221 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
222 SDFI, DAG.getSrcValue(NULL)));
224 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
225 args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
226 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
227 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
228 SDFI = DAG.getFrameIndex(FI, MVT::i64);
229 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
230 SDFI, DAG.getSrcValue(NULL)));
233 //Set up a token factor with all the stack traffic
234 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
237 // Finally, inform the code generator which regs we return values in.
238 switch (getValueType(F.getReturnType())) {
239 default: assert(0 && "Unknown type!");
240 case MVT::isVoid: break;
246 MF.addLiveOut(Alpha::R0);
250 MF.addLiveOut(Alpha::F0);
254 //return the arguments
258 std::pair<SDOperand, SDOperand>
259 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
260 const Type *RetTy, bool isVarArg,
261 unsigned CallingConv, bool isTailCall,
262 SDOperand Callee, ArgListTy &Args,
266 NumBytes = (Args.size() - 6) * 8;
268 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
269 DAG.getConstant(NumBytes, getPointerTy()));
270 std::vector<SDOperand> args_to_use;
271 for (unsigned i = 0, e = Args.size(); i != e; ++i)
273 switch (getValueType(Args[i].second)) {
274 default: assert(0 && "Unexpected ValueType for argument!");
279 // Promote the integer to 64 bits. If the input type is signed use a
280 // sign extend, otherwise use a zero extend.
281 if (Args[i].second->isSigned())
282 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
284 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
291 args_to_use.push_back(Args[i].first);
294 std::vector<MVT::ValueType> RetVals;
295 MVT::ValueType RetTyVT = getValueType(RetTy);
296 MVT::ValueType ActualRetTyVT = RetTyVT;
297 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
298 ActualRetTyVT = MVT::i64;
300 if (RetTyVT != MVT::isVoid)
301 RetVals.push_back(ActualRetTyVT);
302 RetVals.push_back(MVT::Other);
304 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
305 Chain, Callee, args_to_use), 0);
306 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
307 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
308 DAG.getConstant(NumBytes, getPointerTy()));
309 SDOperand RetVal = TheCall;
311 if (RetTyVT != ActualRetTyVT) {
312 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
313 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
314 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
317 return std::make_pair(RetVal, Chain);
320 SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
321 Value *VAListV, SelectionDAG &DAG) {
322 // vastart stores the address of the VarArgsBase and VarArgsOffset
323 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
324 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
325 DAG.getSrcValue(VAListV));
326 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
327 DAG.getConstant(8, MVT::i64));
328 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
329 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
330 DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
333 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
334 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
335 const Type *ArgTy, SelectionDAG &DAG) {
336 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
337 DAG.getSrcValue(VAListV));
338 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
339 DAG.getConstant(8, MVT::i64));
340 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
341 Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
342 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
343 if (ArgTy->isFloatingPoint())
345 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
346 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
347 DAG.getConstant(8*6, MVT::i64));
348 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
349 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
350 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
354 if (ArgTy == Type::IntTy)
355 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
356 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
357 else if (ArgTy == Type::UIntTy)
358 Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
359 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
361 Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
362 DAG.getSrcValue(NULL));
364 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
365 DAG.getConstant(8, MVT::i64));
366 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
367 Result.getValue(1), NewOffset,
368 Tmp, DAG.getSrcValue(VAListV, 8),
369 DAG.getValueType(MVT::i32));
370 Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
372 return std::make_pair(Result, Update);
376 SDOperand AlphaTargetLowering::
377 LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
378 Value *DestV, SelectionDAG &DAG) {
379 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
380 DAG.getSrcValue(SrcV));
381 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
382 Val, DestP, DAG.getSrcValue(DestV));
383 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
384 DAG.getConstant(8, MVT::i64));
385 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
386 DAG.getSrcValue(SrcV, 8), MVT::i32);
387 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
388 DAG.getConstant(8, MVT::i64));
389 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
390 Val, NPD, DAG.getSrcValue(DestV, 8),
391 DAG.getValueType(MVT::i32));
394 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
396 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
398 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
400 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
404 /// LowerOperation - Provide custom lowering hooks for some operations.
406 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
407 switch (Op.getOpcode()) {
408 default: assert(0 && "Wasn't expecting to be able to lower this!");
409 case ISD::SINT_TO_FP: {
410 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
411 "Unhandled SINT_TO_FP type in custom expander!");
413 bool isDouble = MVT::f64 == Op.getValueType();
415 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
418 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
419 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
420 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
421 Op.getOperand(0), FI, DAG.getSrcValue(0));
422 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
424 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
425 isDouble?MVT::f64:MVT::f32, LD);
428 case ISD::FP_TO_SINT: {
429 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
430 SDOperand src = Op.getOperand(0);
432 if (!isDouble) //Promote
433 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
435 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
438 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
441 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
442 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
443 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
444 src, FI, DAG.getSrcValue(0));
445 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
448 case ISD::ConstantPool: {
449 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
450 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64);
452 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
453 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
454 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
457 case ISD::GlobalAddress: {
458 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
459 GlobalValue *GV = GSDN->getGlobal();
460 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
462 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
463 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
464 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
465 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
468 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
470 case ISD::ExternalSymbol: {
471 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
472 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
473 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
480 if (MVT::isInteger(Op.getValueType())) {
481 const char* opstr = 0;
482 switch(Op.getOpcode()) {
483 case ISD::UREM: opstr = "__remqu"; break;
484 case ISD::SREM: opstr = "__remq"; break;
485 case ISD::UDIV: opstr = "__divqu"; break;
486 case ISD::SDIV: opstr = "__divq"; break;
488 SDOperand Tmp1 = Op.getOperand(0),
489 Tmp2 = Op.getOperand(1),
490 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
491 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);