lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp

   1 //===-- ARM64ELFObjectWriter.cpp - ARM64 ELF Writer -----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file handles ELF-specific object emission, converting LLVM's internal
  11 // fixups into the appropriate relocations.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "MCTargetDesc/ARM64FixupKinds.h"
  16 #include "MCTargetDesc/ARM64MCExpr.h"
  17 #include "MCTargetDesc/ARM64MCTargetDesc.h"
  18 #include "llvm/MC/MCELFObjectWriter.h"
  19 #include "llvm/MC/MCValue.h"
  20 #include "llvm/Support/ErrorHandling.h"
  21
  22 using namespace llvm;
  23
  24 namespace {
  25 class ARM64ELFObjectWriter : public MCELFObjectTargetWriter {
  26 public:
  27   ARM64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian);
  28
  29   virtual ~ARM64ELFObjectWriter();
  30
  31 protected:
  32   unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
  33                         bool IsPCRel) const override;
  34
  35 private:
  36 };
  37 }
  38
  39 ARM64ELFObjectWriter::ARM64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian)
  40     : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
  41                               /*HasRelocationAddend*/ true) {}
  42
  43 ARM64ELFObjectWriter::~ARM64ELFObjectWriter() {}
  44
  45 unsigned ARM64ELFObjectWriter::GetRelocType(const MCValue &Target,
  46                                             const MCFixup &Fixup,
  47                                             bool IsPCRel) const {
  48   ARM64MCExpr::VariantKind RefKind =
  49       static_cast<ARM64MCExpr::VariantKind>(Target.getRefKind());
  50   ARM64MCExpr::VariantKind SymLoc = ARM64MCExpr::getSymbolLoc(RefKind);
  51   bool IsNC = ARM64MCExpr::isNotChecked(RefKind);
  52
  53   assert((!Target.getSymA() ||
  54           Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) &&
  55          "Should only be expression-level modifiers here");
  56
  57   assert((!Target.getSymB() ||
  58           Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
  59          "Should only be expression-level modifiers here");
  60
  61   if (IsPCRel) {
  62     switch ((unsigned)Fixup.getKind()) {
  63     case FK_Data_2:
  64       return ELF::R_AARCH64_PREL16;
  65     case FK_Data_4:
  66       return ELF::R_AARCH64_PREL32;
  67     case FK_Data_8:
  68       return ELF::R_AARCH64_PREL64;
  69     case ARM64::fixup_arm64_pcrel_adr_imm21:
  70       assert(SymLoc == ARM64MCExpr::VK_NONE && "unexpected ADR relocation");
  71       return ELF::R_AARCH64_ADR_PREL_LO21;
  72     case ARM64::fixup_arm64_pcrel_adrp_imm21:
  73       if (SymLoc == ARM64MCExpr::VK_ABS && !IsNC)
  74         return ELF::R_AARCH64_ADR_PREL_PG_HI21;
  75       if (SymLoc == ARM64MCExpr::VK_GOT && !IsNC)
  76         return ELF::R_AARCH64_ADR_GOT_PAGE;
  77       if (SymLoc == ARM64MCExpr::VK_GOTTPREL && !IsNC)
  78         return ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21;
  79       if (SymLoc == ARM64MCExpr::VK_TLSDESC && !IsNC)
  80         return ELF::R_AARCH64_TLSDESC_ADR_PAGE;
  81       llvm_unreachable("invalid symbol kind for ADRP relocation");
  82     case ARM64::fixup_arm64_pcrel_branch26:
  83       return ELF::R_AARCH64_JUMP26;
  84     case ARM64::fixup_arm64_pcrel_call26:
  85       return ELF::R_AARCH64_CALL26;
  86     case ARM64::fixup_arm64_ldr_pcrel_imm19:
  87       if (SymLoc == ARM64MCExpr::VK_GOTTPREL)
  88         return ELF::R_AARCH64_TLSIE_LD_GOTTPREL_PREL19;
  89       return ELF::R_AARCH64_LD_PREL_LO19;
  90     case ARM64::fixup_arm64_pcrel_branch14:
  91       return ELF::R_AARCH64_TSTBR14;
  92     case ARM64::fixup_arm64_pcrel_branch19:
  93       return ELF::R_AARCH64_CONDBR19;
  94     default:
  95       llvm_unreachable("Unsupported pc-relative fixup kind");
  96     }
  97   } else {
  98     switch ((unsigned)Fixup.getKind()) {
  99     case FK_Data_2:
 100       return ELF::R_AARCH64_ABS16;
 101     case FK_Data_4:
 102       return ELF::R_AARCH64_ABS32;
 103     case FK_Data_8:
 104       return ELF::R_AARCH64_ABS64;
 105     case ARM64::fixup_arm64_add_imm12:
 106       if (RefKind == ARM64MCExpr::VK_DTPREL_HI12)
 107         return ELF::R_AARCH64_TLSLD_ADD_DTPREL_HI12;
 108       if (RefKind == ARM64MCExpr::VK_TPREL_HI12)
 109         return ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12;
 110       if (RefKind == ARM64MCExpr::VK_DTPREL_LO12_NC)
 111         return ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC;
 112       if (RefKind == ARM64MCExpr::VK_DTPREL_LO12)
 113         return ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12;
 114       if (RefKind == ARM64MCExpr::VK_TPREL_LO12_NC)
 115         return ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC;
 116       if (RefKind == ARM64MCExpr::VK_TPREL_LO12)
 117         return ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12;
 118       if (RefKind == ARM64MCExpr::VK_TLSDESC_LO12)
 119         return ELF::R_AARCH64_TLSDESC_ADD_LO12_NC;
 120       if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
 121         return ELF::R_AARCH64_ADD_ABS_LO12_NC;
 122
 123       report_fatal_error("invalid fixup for add (uimm12) instruction");
 124       return 0;
 125     case ARM64::fixup_arm64_ldst_imm12_scale1:
 126       if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
 127         return ELF::R_AARCH64_LDST8_ABS_LO12_NC;
 128       if (SymLoc == ARM64MCExpr::VK_DTPREL && !IsNC)
 129         return ELF::R_AARCH64_TLSLD_LDST8_DTPREL_LO12;
 130       if (SymLoc == ARM64MCExpr::VK_DTPREL && IsNC)
 131         return ELF::R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC;
 132       if (SymLoc == ARM64MCExpr::VK_TPREL && !IsNC)
 133         return ELF::R_AARCH64_TLSLE_LDST8_TPREL_LO12;
 134       if (SymLoc == ARM64MCExpr::VK_TPREL && IsNC)
 135         return ELF::R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC;
 136
 137       report_fatal_error("invalid fixup for 8-bit load/store instruction");
 138       return 0;
 139     case ARM64::fixup_arm64_ldst_imm12_scale2:
 140       if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
 141         return ELF::R_AARCH64_LDST16_ABS_LO12_NC;
 142       if (SymLoc == ARM64MCExpr::VK_DTPREL && !IsNC)
 143         return ELF::R_AARCH64_TLSLD_LDST16_DTPREL_LO12;
 144       if (SymLoc == ARM64MCExpr::VK_DTPREL && IsNC)
 145         return ELF::R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC;
 146       if (SymLoc == ARM64MCExpr::VK_TPREL && !IsNC)
 147         return ELF::R_AARCH64_TLSLE_LDST16_TPREL_LO12;
 148       if (SymLoc == ARM64MCExpr::VK_TPREL && IsNC)
 149         return ELF::R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC;
 150
 151       report_fatal_error("invalid fixup for 16-bit load/store instruction");
 152       return 0;
 153     case ARM64::fixup_arm64_ldst_imm12_scale4:
 154       if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
 155         return ELF::R_AARCH64_LDST32_ABS_LO12_NC;
 156       if (SymLoc == ARM64MCExpr::VK_DTPREL && !IsNC)
 157         return ELF::R_AARCH64_TLSLD_LDST32_DTPREL_LO12;
 158       if (SymLoc == ARM64MCExpr::VK_DTPREL && IsNC)
 159         return ELF::R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC;
 160       if (SymLoc == ARM64MCExpr::VK_TPREL && !IsNC)
 161         return ELF::R_AARCH64_TLSLE_LDST32_TPREL_LO12;
 162       if (SymLoc == ARM64MCExpr::VK_TPREL && IsNC)
 163         return ELF::R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC;
 164
 165       report_fatal_error("invalid fixup for 32-bit load/store instruction");
 166       return 0;
 167     case ARM64::fixup_arm64_ldst_imm12_scale8:
 168       if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
 169         return ELF::R_AARCH64_LDST64_ABS_LO12_NC;
 170       if (SymLoc == ARM64MCExpr::VK_GOT && IsNC)
 171         return ELF::R_AARCH64_LD64_GOT_LO12_NC;
 172       if (SymLoc == ARM64MCExpr::VK_DTPREL && !IsNC)
 173         return ELF::R_AARCH64_TLSLD_LDST64_DTPREL_LO12;
 174       if (SymLoc == ARM64MCExpr::VK_DTPREL && IsNC)
 175         return ELF::R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC;
 176       if (SymLoc == ARM64MCExpr::VK_TPREL && !IsNC)
 177         return ELF::R_AARCH64_TLSLE_LDST64_TPREL_LO12;
 178       if (SymLoc == ARM64MCExpr::VK_TPREL && IsNC)
 179         return ELF::R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC;
 180       if (SymLoc == ARM64MCExpr::VK_GOTTPREL && IsNC)
 181         return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
 182       if (SymLoc == ARM64MCExpr::VK_TLSDESC && IsNC)
 183         return ELF::R_AARCH64_TLSDESC_LD64_LO12_NC;
 184
 185       report_fatal_error("invalid fixup for 64-bit load/store instruction");
 186       return 0;
 187     case ARM64::fixup_arm64_ldst_imm12_scale16:
 188       if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
 189         return ELF::R_AARCH64_LDST128_ABS_LO12_NC;
 190
 191       report_fatal_error("invalid fixup for 128-bit load/store instruction");
 192       return 0;
 193     case ARM64::fixup_arm64_movw:
 194       if (RefKind == ARM64MCExpr::VK_ABS_G3)
 195         return ELF::R_AARCH64_MOVW_UABS_G3;
 196       if (RefKind == ARM64MCExpr::VK_ABS_G2)
 197         return ELF::R_AARCH64_MOVW_UABS_G2;
 198       if (RefKind == ARM64MCExpr::VK_ABS_G2_S)
 199         return ELF::R_AARCH64_MOVW_SABS_G2;
 200       if (RefKind == ARM64MCExpr::VK_ABS_G2_NC)
 201         return ELF::R_AARCH64_MOVW_UABS_G2_NC;
 202       if (RefKind == ARM64MCExpr::VK_ABS_G1)
 203         return ELF::R_AARCH64_MOVW_UABS_G1;
 204       if (RefKind == ARM64MCExpr::VK_ABS_G1_S)
 205         return ELF::R_AARCH64_MOVW_SABS_G1;
 206       if (RefKind == ARM64MCExpr::VK_ABS_G1_NC)
 207         return ELF::R_AARCH64_MOVW_UABS_G1_NC;
 208       if (RefKind == ARM64MCExpr::VK_ABS_G0)
 209         return ELF::R_AARCH64_MOVW_UABS_G0;
 210       if (RefKind == ARM64MCExpr::VK_ABS_G0_S)
 211         return ELF::R_AARCH64_MOVW_SABS_G0;
 212       if (RefKind == ARM64MCExpr::VK_ABS_G0_NC)
 213         return ELF::R_AARCH64_MOVW_UABS_G0_NC;
 214       if (RefKind == ARM64MCExpr::VK_DTPREL_G2)
 215         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
 216       if (RefKind == ARM64MCExpr::VK_DTPREL_G1)
 217         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1;
 218       if (RefKind == ARM64MCExpr::VK_DTPREL_G1_NC)
 219         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
 220       if (RefKind == ARM64MCExpr::VK_DTPREL_G0)
 221         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G0;
 222       if (RefKind == ARM64MCExpr::VK_DTPREL_G0_NC)
 223         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC;
 224       if (RefKind == ARM64MCExpr::VK_TPREL_G2)
 225         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
 226       if (RefKind == ARM64MCExpr::VK_TPREL_G1)
 227         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1;
 228       if (RefKind == ARM64MCExpr::VK_TPREL_G1_NC)
 229         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
 230       if (RefKind == ARM64MCExpr::VK_TPREL_G0)
 231         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0;
 232       if (RefKind == ARM64MCExpr::VK_TPREL_G0_NC)
 233         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC;
 234       if (RefKind == ARM64MCExpr::VK_GOTTPREL_G1)
 235         return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
 236       if (RefKind == ARM64MCExpr::VK_GOTTPREL_G0_NC)
 237         return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
 238       report_fatal_error("invalid fixup for movz/movk instruction");
 239       return 0;
 240     case ARM64::fixup_arm64_tlsdesc_call:
 241       return ELF::R_AARCH64_TLSDESC_CALL;
 242     default:
 243       llvm_unreachable("Unknown ELF relocation type");
 244     }
 245   }
 246
 247   llvm_unreachable("Unimplemented fixup -> relocation");
 248 }
 249
 250 MCObjectWriter *llvm::createARM64ELFObjectWriter(raw_ostream &OS,
 251                                                  uint8_t OSABI,
 252                                                  bool IsLittleEndian) {
 253   MCELFObjectTargetWriter *MOTW = new ARM64ELFObjectWriter(OSABI, IsLittleEndian);
 254   return createELFObjectWriter(MOTW, OS, IsLittleEndian);
 255 }