lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp

   1 //===- ARM64Disassembler.cpp - Disassembler for ARM64 -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARM64Disassembler.h"
  14 #include "ARM64ExternalSymbolizer.h"
  15 #include "ARM64Subtarget.h"
  16 #include "MCTargetDesc/ARM64AddressingModes.h"
  17 #include "Utils/ARM64BaseInfo.h"
  18 #include "llvm/MC/MCInst.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/Support/Debug.h"
  21 #include "llvm/Support/MemoryObject.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23 #include "llvm/Support/ErrorHandling.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "arm64-disassembler"
  28
  29 // Pull DecodeStatus and its enum values into the global namespace.
  30 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 // Forward declare these because the autogenerated code will reference them.
  33 // Definitions are further down.
  34 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
  35                                               unsigned RegNo, uint64_t Address,
  36                                               const void *Decoder);
  37 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
  38                                                  unsigned RegNo,
  39                                                  uint64_t Address,
  40                                                  const void *Decoder);
  41 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  42                                              uint64_t Address,
  43                                              const void *Decoder);
  44 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  45                                              uint64_t Address,
  46                                              const void *Decoder);
  47 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  48                                              uint64_t Address,
  49                                              const void *Decoder);
  50 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  51                                             uint64_t Address,
  52                                             const void *Decoder);
  53 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  54                                              uint64_t Address,
  55                                              const void *Decoder);
  56 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
  57                                                unsigned RegNo, uint64_t Address,
  58                                                const void *Decoder);
  59 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  60                                              uint64_t Address,
  61                                              const void *Decoder);
  62 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
  63                                                unsigned RegNo, uint64_t Address,
  64                                                const void *Decoder);
  65 static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  66                                           uint64_t Address,
  67                                           const void *Decoder);
  68 static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  69                                            uint64_t Address,
  70                                            const void *Decoder);
  71 static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  72                                             uint64_t Address,
  73                                             const void *Decoder);
  74 static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                                           uint64_t Address,
  76                                           const void *Decoder);
  77 static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  78                                            uint64_t Address,
  79                                            const void *Decoder);
  80 static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  81                                             uint64_t Address,
  82                                             const void *Decoder);
  83
  84 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
  85                                                uint64_t Address,
  86                                                const void *Decoder);
  87 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
  88                                                uint64_t Address,
  89                                                const void *Decoder);
  90 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
  91                                        uint64_t Address, const void *Decoder);
  92 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
  93                                     uint64_t Address, const void *Decoder);
  94 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
  95                                             uint64_t Address, const void *Decoder);
  96 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
  97                                             uint64_t Address, const void *Decoder);
  98 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
  99                                                    uint32_t insn,
 100                                                    uint64_t Address,
 101                                                    const void *Decoder);
 102 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 103                                              uint64_t Address,
 104                                              const void *Decoder);
 105 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
 106                                                   uint32_t insn,
 107                                                   uint64_t Address,
 108                                                   const void *Decoder);
 109 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
 110                                                 uint32_t insn, uint64_t Address,
 111                                                 const void *Decoder);
 112 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
 113                                                    uint32_t insn,
 114                                                    uint64_t Address,
 115                                                    const void *Decoder);
 116 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
 117                                               uint64_t Address,
 118                                               const void *Decoder);
 119 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
 120                                                 uint32_t insn, uint64_t Address,
 121                                                 const void *Decoder);
 122 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
 123                                                 uint32_t insn, uint64_t Address,
 124                                                 const void *Decoder);
 125 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 126                                             uint64_t Address,
 127                                             const void *Decoder);
 128 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
 129                                                 uint32_t insn, uint64_t Address,
 130                                                 const void *Decoder);
 131 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
 132                                          uint64_t Address, const void *Decoder);
 133 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
 134                                         uint64_t Address, const void *Decoder);
 135 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
 136                                               uint64_t Address,
 137                                               const void *Decoder);
 138 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
 139                                                   uint32_t insn,
 140                                                   uint64_t Address,
 141                                                   const void *Decoder);
 142 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
 143                                         uint64_t Address, const void *Decoder);
 144
 145 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 146                                               uint64_t Address,
 147                                               const void *Decoder);
 148 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
 149                                          uint64_t Addr, const void *Decoder);
 150 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 151                                                uint64_t Addr,
 152                                                const void *Decoder);
 153 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
 154                                          uint64_t Addr, const void *Decoder);
 155 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 156                                                uint64_t Addr,
 157                                                const void *Decoder);
 158 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
 159                                          uint64_t Addr, const void *Decoder);
 160 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 161                                                uint64_t Addr,
 162                                                const void *Decoder);
 163 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
 164                                         uint64_t Addr, const void *Decoder);
 165 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
 166                                          uint64_t Addr, const void *Decoder);
 167 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
 168                                          uint64_t Addr, const void *Decoder);
 169 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
 170                                          uint64_t Addr, const void *Decoder);
 171 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
 172                                         uint64_t Addr, const void *Decoder);
 173
 174 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 175   switch (In) {
 176     case MCDisassembler::Success:
 177       // Out stays the same.
 178       return true;
 179     case MCDisassembler::SoftFail:
 180       Out = In;
 181       return true;
 182     case MCDisassembler::Fail:
 183       Out = In;
 184       return false;
 185   }
 186   llvm_unreachable("Invalid DecodeStatus!");
 187 }
 188
 189 #include "ARM64GenDisassemblerTables.inc"
 190 #include "ARM64GenInstrInfo.inc"
 191
 192 #define Success llvm::MCDisassembler::Success
 193 #define Fail llvm::MCDisassembler::Fail
 194 #define SoftFail llvm::MCDisassembler::SoftFail
 195
 196 static MCDisassembler *createARM64Disassembler(const Target &T,
 197                                                const MCSubtargetInfo &STI,
 198                                                MCContext &Ctx) {
 199   return new ARM64Disassembler(STI, Ctx);
 200 }
 201
 202 DecodeStatus ARM64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 203                                                const MemoryObject &Region,
 204                                                uint64_t Address,
 205                                                raw_ostream &os,
 206                                                raw_ostream &cs) const {
 207   CommentStream = &cs;
 208
 209   uint8_t bytes[4];
 210
 211   Size = 0;
 212   // We want to read exactly 4 bytes of data.
 213   if (Region.readBytes(Address, 4, (uint8_t *)bytes) == -1)
 214     return Fail;
 215   Size = 4;
 216
 217   // Encoded as a small-endian 32-bit word in the stream.
 218   uint32_t insn =
 219       (bytes[3] << 24) | (bytes[2] << 16) | (bytes[1] << 8) | (bytes[0] << 0);
 220
 221   // Calling the auto-generated decoder function.
 222   return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
 223 }
 224
 225 static MCSymbolizer *
 226 createARM64ExternalSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
 227                               LLVMSymbolLookupCallback SymbolLookUp,
 228                               void *DisInfo, MCContext *Ctx,
 229                               MCRelocationInfo *RelInfo) {
 230   return new llvm::ARM64ExternalSymbolizer(
 231                                      *Ctx,
 232                                      std::unique_ptr<MCRelocationInfo>(RelInfo),
 233                                      GetOpInfo, SymbolLookUp, DisInfo);
 234 }
 235
 236 extern "C" void LLVMInitializeARM64Disassembler() {
 237   TargetRegistry::RegisterMCDisassembler(TheARM64leTarget,
 238                                          createARM64Disassembler);
 239   TargetRegistry::RegisterMCDisassembler(TheARM64beTarget,
 240                                          createARM64Disassembler);
 241   TargetRegistry::RegisterMCSymbolizer(TheARM64leTarget,
 242                                        createARM64ExternalSymbolizer);
 243   TargetRegistry::RegisterMCSymbolizer(TheARM64beTarget,
 244                                        createARM64ExternalSymbolizer);
 245
 246   TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
 247                                          createARM64Disassembler);
 248   TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
 249                                          createARM64Disassembler);
 250   TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget,
 251                                        createARM64ExternalSymbolizer);
 252   TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget,
 253                                        createARM64ExternalSymbolizer);
 254 }
 255
 256 static const unsigned FPR128DecoderTable[] = {
 257   ARM64::Q0,  ARM64::Q1,  ARM64::Q2,  ARM64::Q3,  ARM64::Q4,  ARM64::Q5,
 258   ARM64::Q6,  ARM64::Q7,  ARM64::Q8,  ARM64::Q9,  ARM64::Q10, ARM64::Q11,
 259   ARM64::Q12, ARM64::Q13, ARM64::Q14, ARM64::Q15, ARM64::Q16, ARM64::Q17,
 260   ARM64::Q18, ARM64::Q19, ARM64::Q20, ARM64::Q21, ARM64::Q22, ARM64::Q23,
 261   ARM64::Q24, ARM64::Q25, ARM64::Q26, ARM64::Q27, ARM64::Q28, ARM64::Q29,
 262   ARM64::Q30, ARM64::Q31
 263 };
 264
 265 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
 266                                               uint64_t Addr,
 267                                               const void *Decoder) {
 268   if (RegNo > 31)
 269     return Fail;
 270
 271   unsigned Register = FPR128DecoderTable[RegNo];
 272   Inst.addOperand(MCOperand::CreateReg(Register));
 273   return Success;
 274 }
 275
 276 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
 277                                                  uint64_t Addr,
 278                                                  const void *Decoder) {
 279   if (RegNo > 15)
 280     return Fail;
 281   return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
 282 }
 283
 284 static const unsigned FPR64DecoderTable[] = {
 285   ARM64::D0,  ARM64::D1,  ARM64::D2,  ARM64::D3,  ARM64::D4,  ARM64::D5,
 286   ARM64::D6,  ARM64::D7,  ARM64::D8,  ARM64::D9,  ARM64::D10, ARM64::D11,
 287   ARM64::D12, ARM64::D13, ARM64::D14, ARM64::D15, ARM64::D16, ARM64::D17,
 288   ARM64::D18, ARM64::D19, ARM64::D20, ARM64::D21, ARM64::D22, ARM64::D23,
 289   ARM64::D24, ARM64::D25, ARM64::D26, ARM64::D27, ARM64::D28, ARM64::D29,
 290   ARM64::D30, ARM64::D31
 291 };
 292
 293 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
 294                                              uint64_t Addr,
 295                                              const void *Decoder) {
 296   if (RegNo > 31)
 297     return Fail;
 298
 299   unsigned Register = FPR64DecoderTable[RegNo];
 300   Inst.addOperand(MCOperand::CreateReg(Register));
 301   return Success;
 302 }
 303
 304 static const unsigned FPR32DecoderTable[] = {
 305   ARM64::S0,  ARM64::S1,  ARM64::S2,  ARM64::S3,  ARM64::S4,  ARM64::S5,
 306   ARM64::S6,  ARM64::S7,  ARM64::S8,  ARM64::S9,  ARM64::S10, ARM64::S11,
 307   ARM64::S12, ARM64::S13, ARM64::S14, ARM64::S15, ARM64::S16, ARM64::S17,
 308   ARM64::S18, ARM64::S19, ARM64::S20, ARM64::S21, ARM64::S22, ARM64::S23,
 309   ARM64::S24, ARM64::S25, ARM64::S26, ARM64::S27, ARM64::S28, ARM64::S29,
 310   ARM64::S30, ARM64::S31
 311 };
 312
 313 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
 314                                              uint64_t Addr,
 315                                              const void *Decoder) {
 316   if (RegNo > 31)
 317     return Fail;
 318
 319   unsigned Register = FPR32DecoderTable[RegNo];
 320   Inst.addOperand(MCOperand::CreateReg(Register));
 321   return Success;
 322 }
 323
 324 static const unsigned FPR16DecoderTable[] = {
 325   ARM64::H0,  ARM64::H1,  ARM64::H2,  ARM64::H3,  ARM64::H4,  ARM64::H5,
 326   ARM64::H6,  ARM64::H7,  ARM64::H8,  ARM64::H9,  ARM64::H10, ARM64::H11,
 327   ARM64::H12, ARM64::H13, ARM64::H14, ARM64::H15, ARM64::H16, ARM64::H17,
 328   ARM64::H18, ARM64::H19, ARM64::H20, ARM64::H21, ARM64::H22, ARM64::H23,
 329   ARM64::H24, ARM64::H25, ARM64::H26, ARM64::H27, ARM64::H28, ARM64::H29,
 330   ARM64::H30, ARM64::H31
 331 };
 332
 333 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
 334                                              uint64_t Addr,
 335                                              const void *Decoder) {
 336   if (RegNo > 31)
 337     return Fail;
 338
 339   unsigned Register = FPR16DecoderTable[RegNo];
 340   Inst.addOperand(MCOperand::CreateReg(Register));
 341   return Success;
 342 }
 343
 344 static const unsigned FPR8DecoderTable[] = {
 345   ARM64::B0,  ARM64::B1,  ARM64::B2,  ARM64::B3,  ARM64::B4,  ARM64::B5,
 346   ARM64::B6,  ARM64::B7,  ARM64::B8,  ARM64::B9,  ARM64::B10, ARM64::B11,
 347   ARM64::B12, ARM64::B13, ARM64::B14, ARM64::B15, ARM64::B16, ARM64::B17,
 348   ARM64::B18, ARM64::B19, ARM64::B20, ARM64::B21, ARM64::B22, ARM64::B23,
 349   ARM64::B24, ARM64::B25, ARM64::B26, ARM64::B27, ARM64::B28, ARM64::B29,
 350   ARM64::B30, ARM64::B31
 351 };
 352
 353 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
 354                                             uint64_t Addr,
 355                                             const void *Decoder) {
 356   if (RegNo > 31)
 357     return Fail;
 358
 359   unsigned Register = FPR8DecoderTable[RegNo];
 360   Inst.addOperand(MCOperand::CreateReg(Register));
 361   return Success;
 362 }
 363
 364 static const unsigned GPR64DecoderTable[] = {
 365   ARM64::X0,  ARM64::X1,  ARM64::X2,  ARM64::X3,  ARM64::X4,  ARM64::X5,
 366   ARM64::X6,  ARM64::X7,  ARM64::X8,  ARM64::X9,  ARM64::X10, ARM64::X11,
 367   ARM64::X12, ARM64::X13, ARM64::X14, ARM64::X15, ARM64::X16, ARM64::X17,
 368   ARM64::X18, ARM64::X19, ARM64::X20, ARM64::X21, ARM64::X22, ARM64::X23,
 369   ARM64::X24, ARM64::X25, ARM64::X26, ARM64::X27, ARM64::X28, ARM64::FP,
 370   ARM64::LR,  ARM64::XZR
 371 };
 372
 373 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
 374                                              uint64_t Addr,
 375                                              const void *Decoder) {
 376   if (RegNo > 31)
 377     return Fail;
 378
 379   unsigned Register = GPR64DecoderTable[RegNo];
 380   Inst.addOperand(MCOperand::CreateReg(Register));
 381   return Success;
 382 }
 383
 384 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
 385                                                uint64_t Addr,
 386                                                const void *Decoder) {
 387   if (RegNo > 31)
 388     return Fail;
 389   unsigned Register = GPR64DecoderTable[RegNo];
 390   if (Register == ARM64::XZR)
 391     Register = ARM64::SP;
 392   Inst.addOperand(MCOperand::CreateReg(Register));
 393   return Success;
 394 }
 395
 396 static const unsigned GPR32DecoderTable[] = {
 397   ARM64::W0,  ARM64::W1,  ARM64::W2,  ARM64::W3,  ARM64::W4,  ARM64::W5,
 398   ARM64::W6,  ARM64::W7,  ARM64::W8,  ARM64::W9,  ARM64::W10, ARM64::W11,
 399   ARM64::W12, ARM64::W13, ARM64::W14, ARM64::W15, ARM64::W16, ARM64::W17,
 400   ARM64::W18, ARM64::W19, ARM64::W20, ARM64::W21, ARM64::W22, ARM64::W23,
 401   ARM64::W24, ARM64::W25, ARM64::W26, ARM64::W27, ARM64::W28, ARM64::W29,
 402   ARM64::W30, ARM64::WZR
 403 };
 404
 405 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
 406                                              uint64_t Addr,
 407                                              const void *Decoder) {
 408   if (RegNo > 31)
 409     return Fail;
 410
 411   unsigned Register = GPR32DecoderTable[RegNo];
 412   Inst.addOperand(MCOperand::CreateReg(Register));
 413   return Success;
 414 }
 415
 416 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
 417                                                uint64_t Addr,
 418                                                const void *Decoder) {
 419   if (RegNo > 31)
 420     return Fail;
 421
 422   unsigned Register = GPR32DecoderTable[RegNo];
 423   if (Register == ARM64::WZR)
 424     Register = ARM64::WSP;
 425   Inst.addOperand(MCOperand::CreateReg(Register));
 426   return Success;
 427 }
 428
 429 static const unsigned VectorDecoderTable[] = {
 430   ARM64::Q0,  ARM64::Q1,  ARM64::Q2,  ARM64::Q3,  ARM64::Q4,  ARM64::Q5,
 431   ARM64::Q6,  ARM64::Q7,  ARM64::Q8,  ARM64::Q9,  ARM64::Q10, ARM64::Q11,
 432   ARM64::Q12, ARM64::Q13, ARM64::Q14, ARM64::Q15, ARM64::Q16, ARM64::Q17,
 433   ARM64::Q18, ARM64::Q19, ARM64::Q20, ARM64::Q21, ARM64::Q22, ARM64::Q23,
 434   ARM64::Q24, ARM64::Q25, ARM64::Q26, ARM64::Q27, ARM64::Q28, ARM64::Q29,
 435   ARM64::Q30, ARM64::Q31
 436 };
 437
 438 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
 439                                               uint64_t Addr,
 440                                               const void *Decoder) {
 441   if (RegNo > 31)
 442     return Fail;
 443
 444   unsigned Register = VectorDecoderTable[RegNo];
 445   Inst.addOperand(MCOperand::CreateReg(Register));
 446   return Success;
 447 }
 448
 449 static const unsigned QQDecoderTable[] = {
 450   ARM64::Q0_Q1,   ARM64::Q1_Q2,   ARM64::Q2_Q3,   ARM64::Q3_Q4,
 451   ARM64::Q4_Q5,   ARM64::Q5_Q6,   ARM64::Q6_Q7,   ARM64::Q7_Q8,
 452   ARM64::Q8_Q9,   ARM64::Q9_Q10,  ARM64::Q10_Q11, ARM64::Q11_Q12,
 453   ARM64::Q12_Q13, ARM64::Q13_Q14, ARM64::Q14_Q15, ARM64::Q15_Q16,
 454   ARM64::Q16_Q17, ARM64::Q17_Q18, ARM64::Q18_Q19, ARM64::Q19_Q20,
 455   ARM64::Q20_Q21, ARM64::Q21_Q22, ARM64::Q22_Q23, ARM64::Q23_Q24,
 456   ARM64::Q24_Q25, ARM64::Q25_Q26, ARM64::Q26_Q27, ARM64::Q27_Q28,
 457   ARM64::Q28_Q29, ARM64::Q29_Q30, ARM64::Q30_Q31, ARM64::Q31_Q0
 458 };
 459
 460 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
 461                                           uint64_t Addr, const void *Decoder) {
 462   if (RegNo > 31)
 463     return Fail;
 464   unsigned Register = QQDecoderTable[RegNo];
 465   Inst.addOperand(MCOperand::CreateReg(Register));
 466   return Success;
 467 }
 468
 469 static const unsigned QQQDecoderTable[] = {
 470   ARM64::Q0_Q1_Q2,    ARM64::Q1_Q2_Q3,    ARM64::Q2_Q3_Q4,
 471   ARM64::Q3_Q4_Q5,    ARM64::Q4_Q5_Q6,    ARM64::Q5_Q6_Q7,
 472   ARM64::Q6_Q7_Q8,    ARM64::Q7_Q8_Q9,    ARM64::Q8_Q9_Q10,
 473   ARM64::Q9_Q10_Q11,  ARM64::Q10_Q11_Q12, ARM64::Q11_Q12_Q13,
 474   ARM64::Q12_Q13_Q14, ARM64::Q13_Q14_Q15, ARM64::Q14_Q15_Q16,
 475   ARM64::Q15_Q16_Q17, ARM64::Q16_Q17_Q18, ARM64::Q17_Q18_Q19,
 476   ARM64::Q18_Q19_Q20, ARM64::Q19_Q20_Q21, ARM64::Q20_Q21_Q22,
 477   ARM64::Q21_Q22_Q23, ARM64::Q22_Q23_Q24, ARM64::Q23_Q24_Q25,
 478   ARM64::Q24_Q25_Q26, ARM64::Q25_Q26_Q27, ARM64::Q26_Q27_Q28,
 479   ARM64::Q27_Q28_Q29, ARM64::Q28_Q29_Q30, ARM64::Q29_Q30_Q31,
 480   ARM64::Q30_Q31_Q0,  ARM64::Q31_Q0_Q1
 481 };
 482
 483 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
 484                                            uint64_t Addr, const void *Decoder) {
 485   if (RegNo > 31)
 486     return Fail;
 487   unsigned Register = QQQDecoderTable[RegNo];
 488   Inst.addOperand(MCOperand::CreateReg(Register));
 489   return Success;
 490 }
 491
 492 static const unsigned QQQQDecoderTable[] = {
 493   ARM64::Q0_Q1_Q2_Q3,     ARM64::Q1_Q2_Q3_Q4,     ARM64::Q2_Q3_Q4_Q5,
 494   ARM64::Q3_Q4_Q5_Q6,     ARM64::Q4_Q5_Q6_Q7,     ARM64::Q5_Q6_Q7_Q8,
 495   ARM64::Q6_Q7_Q8_Q9,     ARM64::Q7_Q8_Q9_Q10,    ARM64::Q8_Q9_Q10_Q11,
 496   ARM64::Q9_Q10_Q11_Q12,  ARM64::Q10_Q11_Q12_Q13, ARM64::Q11_Q12_Q13_Q14,
 497   ARM64::Q12_Q13_Q14_Q15, ARM64::Q13_Q14_Q15_Q16, ARM64::Q14_Q15_Q16_Q17,
 498   ARM64::Q15_Q16_Q17_Q18, ARM64::Q16_Q17_Q18_Q19, ARM64::Q17_Q18_Q19_Q20,
 499   ARM64::Q18_Q19_Q20_Q21, ARM64::Q19_Q20_Q21_Q22, ARM64::Q20_Q21_Q22_Q23,
 500   ARM64::Q21_Q22_Q23_Q24, ARM64::Q22_Q23_Q24_Q25, ARM64::Q23_Q24_Q25_Q26,
 501   ARM64::Q24_Q25_Q26_Q27, ARM64::Q25_Q26_Q27_Q28, ARM64::Q26_Q27_Q28_Q29,
 502   ARM64::Q27_Q28_Q29_Q30, ARM64::Q28_Q29_Q30_Q31, ARM64::Q29_Q30_Q31_Q0,
 503   ARM64::Q30_Q31_Q0_Q1,   ARM64::Q31_Q0_Q1_Q2
 504 };
 505
 506 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
 507                                             uint64_t Addr,
 508                                             const void *Decoder) {
 509   if (RegNo > 31)
 510     return Fail;
 511   unsigned Register = QQQQDecoderTable[RegNo];
 512   Inst.addOperand(MCOperand::CreateReg(Register));
 513   return Success;
 514 }
 515
 516 static const unsigned DDDecoderTable[] = {
 517   ARM64::D0_D1,   ARM64::D1_D2,   ARM64::D2_D3,   ARM64::D3_D4,
 518   ARM64::D4_D5,   ARM64::D5_D6,   ARM64::D6_D7,   ARM64::D7_D8,
 519   ARM64::D8_D9,   ARM64::D9_D10,  ARM64::D10_D11, ARM64::D11_D12,
 520   ARM64::D12_D13, ARM64::D13_D14, ARM64::D14_D15, ARM64::D15_D16,
 521   ARM64::D16_D17, ARM64::D17_D18, ARM64::D18_D19, ARM64::D19_D20,
 522   ARM64::D20_D21, ARM64::D21_D22, ARM64::D22_D23, ARM64::D23_D24,
 523   ARM64::D24_D25, ARM64::D25_D26, ARM64::D26_D27, ARM64::D27_D28,
 524   ARM64::D28_D29, ARM64::D29_D30, ARM64::D30_D31, ARM64::D31_D0
 525 };
 526
 527 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
 528                                           uint64_t Addr, const void *Decoder) {
 529   if (RegNo > 31)
 530     return Fail;
 531   unsigned Register = DDDecoderTable[RegNo];
 532   Inst.addOperand(MCOperand::CreateReg(Register));
 533   return Success;
 534 }
 535
 536 static const unsigned DDDDecoderTable[] = {
 537   ARM64::D0_D1_D2,    ARM64::D1_D2_D3,    ARM64::D2_D3_D4,
 538   ARM64::D3_D4_D5,    ARM64::D4_D5_D6,    ARM64::D5_D6_D7,
 539   ARM64::D6_D7_D8,    ARM64::D7_D8_D9,    ARM64::D8_D9_D10,
 540   ARM64::D9_D10_D11,  ARM64::D10_D11_D12, ARM64::D11_D12_D13,
 541   ARM64::D12_D13_D14, ARM64::D13_D14_D15, ARM64::D14_D15_D16,
 542   ARM64::D15_D16_D17, ARM64::D16_D17_D18, ARM64::D17_D18_D19,
 543   ARM64::D18_D19_D20, ARM64::D19_D20_D21, ARM64::D20_D21_D22,
 544   ARM64::D21_D22_D23, ARM64::D22_D23_D24, ARM64::D23_D24_D25,
 545   ARM64::D24_D25_D26, ARM64::D25_D26_D27, ARM64::D26_D27_D28,
 546   ARM64::D27_D28_D29, ARM64::D28_D29_D30, ARM64::D29_D30_D31,
 547   ARM64::D30_D31_D0,  ARM64::D31_D0_D1
 548 };
 549
 550 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
 551                                            uint64_t Addr, const void *Decoder) {
 552   if (RegNo > 31)
 553     return Fail;
 554   unsigned Register = DDDDecoderTable[RegNo];
 555   Inst.addOperand(MCOperand::CreateReg(Register));
 556   return Success;
 557 }
 558
 559 static const unsigned DDDDDecoderTable[] = {
 560   ARM64::D0_D1_D2_D3,     ARM64::D1_D2_D3_D4,     ARM64::D2_D3_D4_D5,
 561   ARM64::D3_D4_D5_D6,     ARM64::D4_D5_D6_D7,     ARM64::D5_D6_D7_D8,
 562   ARM64::D6_D7_D8_D9,     ARM64::D7_D8_D9_D10,    ARM64::D8_D9_D10_D11,
 563   ARM64::D9_D10_D11_D12,  ARM64::D10_D11_D12_D13, ARM64::D11_D12_D13_D14,
 564   ARM64::D12_D13_D14_D15, ARM64::D13_D14_D15_D16, ARM64::D14_D15_D16_D17,
 565   ARM64::D15_D16_D17_D18, ARM64::D16_D17_D18_D19, ARM64::D17_D18_D19_D20,
 566   ARM64::D18_D19_D20_D21, ARM64::D19_D20_D21_D22, ARM64::D20_D21_D22_D23,
 567   ARM64::D21_D22_D23_D24, ARM64::D22_D23_D24_D25, ARM64::D23_D24_D25_D26,
 568   ARM64::D24_D25_D26_D27, ARM64::D25_D26_D27_D28, ARM64::D26_D27_D28_D29,
 569   ARM64::D27_D28_D29_D30, ARM64::D28_D29_D30_D31, ARM64::D29_D30_D31_D0,
 570   ARM64::D30_D31_D0_D1,   ARM64::D31_D0_D1_D2
 571 };
 572
 573 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
 574                                             uint64_t Addr,
 575                                             const void *Decoder) {
 576   if (RegNo > 31)
 577     return Fail;
 578   unsigned Register = DDDDDecoderTable[RegNo];
 579   Inst.addOperand(MCOperand::CreateReg(Register));
 580   return Success;
 581 }
 582
 583 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
 584                                                uint64_t Addr,
 585                                                const void *Decoder) {
 586   // scale{5} is asserted as 1 in tblgen.
 587   Imm |= 0x20;
 588   Inst.addOperand(MCOperand::CreateImm(64 - Imm));
 589   return Success;
 590 }
 591
 592 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
 593                                                uint64_t Addr,
 594                                                const void *Decoder) {
 595   Inst.addOperand(MCOperand::CreateImm(64 - Imm));
 596   return Success;
 597 }
 598
 599 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
 600                                        uint64_t Addr, const void *Decoder) {
 601   int64_t ImmVal = Imm;
 602   const ARM64Disassembler *Dis =
 603       static_cast<const ARM64Disassembler *>(Decoder);
 604
 605   // Sign-extend 19-bit immediate.
 606   if (ImmVal & (1 << (19 - 1)))
 607     ImmVal |= ~((1LL << 19) - 1);
 608
 609   if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal << 2, Addr,
 610                                      Inst.getOpcode() != ARM64::LDRXl, 0, 4))
 611     Inst.addOperand(MCOperand::CreateImm(ImmVal));
 612   return Success;
 613 }
 614
 615 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
 616                                     uint64_t Address, const void *Decoder) {
 617   Inst.addOperand(MCOperand::CreateImm((Imm  >> 1) & 1));
 618   Inst.addOperand(MCOperand::CreateImm(Imm & 1));
 619   return Success;
 620 }
 621
 622 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
 623                                             uint64_t Address,
 624                                             const void *Decoder) {
 625   const ARM64Disassembler *Dis =
 626       static_cast<const ARM64Disassembler *>(Decoder);
 627   const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
 628
 629   Imm |= 0x8000;
 630   Inst.addOperand(MCOperand::CreateImm(Imm));
 631
 632   bool ValidNamed;
 633   (void)ARM64SysReg::MRSMapper(STI.getFeatureBits()).toString(Imm, ValidNamed);
 634
 635   return ValidNamed ? Success : Fail;
 636 }
 637
 638 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
 639                                             uint64_t Address,
 640                                             const void *Decoder) {
 641   const ARM64Disassembler *Dis =
 642       static_cast<const ARM64Disassembler *>(Decoder);
 643   const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
 644
 645   Imm |= 0x8000;
 646   Inst.addOperand(MCOperand::CreateImm(Imm));
 647
 648   bool ValidNamed;
 649   (void)ARM64SysReg::MSRMapper(STI.getFeatureBits()).toString(Imm, ValidNamed);
 650
 651   return ValidNamed ? Success : Fail;
 652 }
 653
 654 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 655                                               uint64_t Address,
 656                                               const void *Decoder) {
 657   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 658   // be 1 in assembly but has no other real manifestation.
 659   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 660   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 661   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 662
 663   if (IsToVec) {
 664     DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
 665     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 666   } else {
 667     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 668     DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
 669   }
 670
 671   // Add the lane
 672   Inst.addOperand(MCOperand::CreateImm(1));
 673
 674   return Success;
 675 }
 676
 677 static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
 678                                        unsigned Add) {
 679   Inst.addOperand(MCOperand::CreateImm(Add - Imm));
 680   return Success;
 681 }
 682
 683 static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
 684                                        unsigned Add) {
 685   Inst.addOperand(MCOperand::CreateImm((Imm + Add) & (Add - 1)));
 686   return Success;
 687 }
 688
 689 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
 690                                          uint64_t Addr, const void *Decoder) {
 691   return DecodeVecShiftRImm(Inst, Imm, 64);
 692 }
 693
 694 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 695                                                uint64_t Addr,
 696                                                const void *Decoder) {
 697   return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
 698 }
 699
 700 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
 701                                          uint64_t Addr, const void *Decoder) {
 702   return DecodeVecShiftRImm(Inst, Imm, 32);
 703 }
 704
 705 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 706                                                uint64_t Addr,
 707                                                const void *Decoder) {
 708   return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
 709 }
 710
 711 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
 712                                          uint64_t Addr, const void *Decoder) {
 713   return DecodeVecShiftRImm(Inst, Imm, 16);
 714 }
 715
 716 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 717                                                uint64_t Addr,
 718                                                const void *Decoder) {
 719   return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
 720 }
 721
 722 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
 723                                         uint64_t Addr, const void *Decoder) {
 724   return DecodeVecShiftRImm(Inst, Imm, 8);
 725 }
 726
 727 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
 728                                          uint64_t Addr, const void *Decoder) {
 729   return DecodeVecShiftLImm(Inst, Imm, 64);
 730 }
 731
 732 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
 733                                          uint64_t Addr, const void *Decoder) {
 734   return DecodeVecShiftLImm(Inst, Imm, 32);
 735 }
 736
 737 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
 738                                          uint64_t Addr, const void *Decoder) {
 739   return DecodeVecShiftLImm(Inst, Imm, 16);
 740 }
 741
 742 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
 743                                         uint64_t Addr, const void *Decoder) {
 744   return DecodeVecShiftLImm(Inst, Imm, 8);
 745 }
 746
 747 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
 748                                                    uint32_t insn, uint64_t Addr,
 749                                                    const void *Decoder) {
 750   unsigned Rd = fieldFromInstruction(insn, 0, 5);
 751   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 752   unsigned Rm = fieldFromInstruction(insn, 16, 5);
 753   unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
 754   unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
 755   unsigned shift = (shiftHi << 6) | shiftLo;
 756   switch (Inst.getOpcode()) {
 757   default:
 758     return Fail;
 759   case ARM64::ADDWrs:
 760   case ARM64::ADDSWrs:
 761   case ARM64::SUBWrs:
 762   case ARM64::SUBSWrs:
 763     // if shift == '11' then ReservedValue()
 764     if (shiftHi == 0x3)
 765       return Fail;
 766     // Deliberate fallthrough
 767   case ARM64::ANDWrs:
 768   case ARM64::ANDSWrs:
 769   case ARM64::BICWrs:
 770   case ARM64::BICSWrs:
 771   case ARM64::ORRWrs:
 772   case ARM64::ORNWrs:
 773   case ARM64::EORWrs:
 774   case ARM64::EONWrs: {
 775     // if sf == '0' and imm6<5> == '1' then ReservedValue()
 776     if (shiftLo >> 5 == 1)
 777       return Fail;
 778     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
 779     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
 780     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
 781     break;
 782   }
 783   case ARM64::ADDXrs:
 784   case ARM64::ADDSXrs:
 785   case ARM64::SUBXrs:
 786   case ARM64::SUBSXrs:
 787     // if shift == '11' then ReservedValue()
 788     if (shiftHi == 0x3)
 789       return Fail;
 790     // Deliberate fallthrough
 791   case ARM64::ANDXrs:
 792   case ARM64::ANDSXrs:
 793   case ARM64::BICXrs:
 794   case ARM64::BICSXrs:
 795   case ARM64::ORRXrs:
 796   case ARM64::ORNXrs:
 797   case ARM64::EORXrs:
 798   case ARM64::EONXrs:
 799     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
 800     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
 801     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
 802     break;
 803   }
 804
 805   Inst.addOperand(MCOperand::CreateImm(shift));
 806   return Success;
 807 }
 808
 809 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 810                                              uint64_t Addr,
 811                                              const void *Decoder) {
 812   unsigned Rd = fieldFromInstruction(insn, 0, 5);
 813   unsigned imm = fieldFromInstruction(insn, 5, 16);
 814   unsigned shift = fieldFromInstruction(insn, 21, 2);
 815   shift <<= 4;
 816   switch (Inst.getOpcode()) {
 817   default:
 818     return Fail;
 819   case ARM64::MOVZWi:
 820   case ARM64::MOVNWi:
 821   case ARM64::MOVKWi:
 822     if (shift & (1U << 5))
 823       return Fail;
 824     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
 825     break;
 826   case ARM64::MOVZXi:
 827   case ARM64::MOVNXi:
 828   case ARM64::MOVKXi:
 829     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
 830     break;
 831   }
 832
 833   if (Inst.getOpcode() == ARM64::MOVKWi || Inst.getOpcode() == ARM64::MOVKXi)
 834     Inst.addOperand(Inst.getOperand(0));
 835
 836   Inst.addOperand(MCOperand::CreateImm(imm));
 837   Inst.addOperand(MCOperand::CreateImm(shift));
 838   return Success;
 839 }
 840
 841 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
 842                                                   uint32_t insn, uint64_t Addr,
 843                                                   const void *Decoder) {
 844   unsigned Rt = fieldFromInstruction(insn, 0, 5);
 845   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 846   unsigned offset = fieldFromInstruction(insn, 10, 12);
 847   const ARM64Disassembler *Dis =
 848       static_cast<const ARM64Disassembler *>(Decoder);
 849
 850   switch (Inst.getOpcode()) {
 851   default:
 852     return Fail;
 853   case ARM64::PRFMui:
 854     // Rt is an immediate in prefetch.
 855     Inst.addOperand(MCOperand::CreateImm(Rt));
 856     break;
 857   case ARM64::STRBBui:
 858   case ARM64::LDRBBui:
 859   case ARM64::LDRSBWui:
 860   case ARM64::STRHHui:
 861   case ARM64::LDRHHui:
 862   case ARM64::LDRSHWui:
 863   case ARM64::STRWui:
 864   case ARM64::LDRWui:
 865     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
 866     break;
 867   case ARM64::LDRSBXui:
 868   case ARM64::LDRSHXui:
 869   case ARM64::LDRSWui:
 870   case ARM64::STRXui:
 871   case ARM64::LDRXui:
 872     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
 873     break;
 874   case ARM64::LDRQui:
 875   case ARM64::STRQui:
 876     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
 877     break;
 878   case ARM64::LDRDui:
 879   case ARM64::STRDui:
 880     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
 881     break;
 882   case ARM64::LDRSui:
 883   case ARM64::STRSui:
 884     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
 885     break;
 886   case ARM64::LDRHui:
 887   case ARM64::STRHui:
 888     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
 889     break;
 890   case ARM64::LDRBui:
 891   case ARM64::STRBui:
 892     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
 893     break;
 894   }
 895
 896   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 897   if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
 898     Inst.addOperand(MCOperand::CreateImm(offset));
 899   return Success;
 900 }
 901
 902 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
 903                                                 uint32_t insn, uint64_t Addr,
 904                                                 const void *Decoder) {
 905   unsigned Rt = fieldFromInstruction(insn, 0, 5);
 906   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 907   int64_t offset = fieldFromInstruction(insn, 12, 9);
 908
 909   // offset is a 9-bit signed immediate, so sign extend it to
 910   // fill the unsigned.
 911   if (offset & (1 << (9 - 1)))
 912     offset |= ~((1LL << 9) - 1);
 913
 914   // First operand is always the writeback to the address register, if needed.
 915   switch (Inst.getOpcode()) {
 916   default:
 917     break;
 918   case ARM64::LDRSBWpre:
 919   case ARM64::LDRSHWpre:
 920   case ARM64::STRBBpre:
 921   case ARM64::LDRBBpre:
 922   case ARM64::STRHHpre:
 923   case ARM64::LDRHHpre:
 924   case ARM64::STRWpre:
 925   case ARM64::LDRWpre:
 926   case ARM64::LDRSBWpost:
 927   case ARM64::LDRSHWpost:
 928   case ARM64::STRBBpost:
 929   case ARM64::LDRBBpost:
 930   case ARM64::STRHHpost:
 931   case ARM64::LDRHHpost:
 932   case ARM64::STRWpost:
 933   case ARM64::LDRWpost:
 934   case ARM64::LDRSBXpre:
 935   case ARM64::LDRSHXpre:
 936   case ARM64::STRXpre:
 937   case ARM64::LDRSWpre:
 938   case ARM64::LDRXpre:
 939   case ARM64::LDRSBXpost:
 940   case ARM64::LDRSHXpost:
 941   case ARM64::STRXpost:
 942   case ARM64::LDRSWpost:
 943   case ARM64::LDRXpost:
 944   case ARM64::LDRQpre:
 945   case ARM64::STRQpre:
 946   case ARM64::LDRQpost:
 947   case ARM64::STRQpost:
 948   case ARM64::LDRDpre:
 949   case ARM64::STRDpre:
 950   case ARM64::LDRDpost:
 951   case ARM64::STRDpost:
 952   case ARM64::LDRSpre:
 953   case ARM64::STRSpre:
 954   case ARM64::LDRSpost:
 955   case ARM64::STRSpost:
 956   case ARM64::LDRHpre:
 957   case ARM64::STRHpre:
 958   case ARM64::LDRHpost:
 959   case ARM64::STRHpost:
 960   case ARM64::LDRBpre:
 961   case ARM64::STRBpre:
 962   case ARM64::LDRBpost:
 963   case ARM64::STRBpost:
 964     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 965     break;
 966   }
 967
 968   switch (Inst.getOpcode()) {
 969   default:
 970     return Fail;
 971   case ARM64::PRFUMi:
 972     // Rt is an immediate in prefetch.
 973     Inst.addOperand(MCOperand::CreateImm(Rt));
 974     break;
 975   case ARM64::STURBBi:
 976   case ARM64::LDURBBi:
 977   case ARM64::LDURSBWi:
 978   case ARM64::STURHHi:
 979   case ARM64::LDURHHi:
 980   case ARM64::LDURSHWi:
 981   case ARM64::STURWi:
 982   case ARM64::LDURWi:
 983   case ARM64::LDTRSBWi:
 984   case ARM64::LDTRSHWi:
 985   case ARM64::STTRWi:
 986   case ARM64::LDTRWi:
 987   case ARM64::STTRHi:
 988   case ARM64::LDTRHi:
 989   case ARM64::LDTRBi:
 990   case ARM64::STTRBi:
 991   case ARM64::LDRSBWpre:
 992   case ARM64::LDRSHWpre:
 993   case ARM64::STRBBpre:
 994   case ARM64::LDRBBpre:
 995   case ARM64::STRHHpre:
 996   case ARM64::LDRHHpre:
 997   case ARM64::STRWpre:
 998   case ARM64::LDRWpre:
 999   case ARM64::LDRSBWpost:
1000   case ARM64::LDRSHWpost:
1001   case ARM64::STRBBpost:
1002   case ARM64::LDRBBpost:
1003   case ARM64::STRHHpost:
1004   case ARM64::LDRHHpost:
1005   case ARM64::STRWpost:
1006   case ARM64::LDRWpost:
1007     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1008     break;
1009   case ARM64::LDURSBXi:
1010   case ARM64::LDURSHXi:
1011   case ARM64::LDURSWi:
1012   case ARM64::STURXi:
1013   case ARM64::LDURXi:
1014   case ARM64::LDTRSBXi:
1015   case ARM64::LDTRSHXi:
1016   case ARM64::LDTRSWi:
1017   case ARM64::STTRXi:
1018   case ARM64::LDTRXi:
1019   case ARM64::LDRSBXpre:
1020   case ARM64::LDRSHXpre:
1021   case ARM64::STRXpre:
1022   case ARM64::LDRSWpre:
1023   case ARM64::LDRXpre:
1024   case ARM64::LDRSBXpost:
1025   case ARM64::LDRSHXpost:
1026   case ARM64::STRXpost:
1027   case ARM64::LDRSWpost:
1028   case ARM64::LDRXpost:
1029     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1030     break;
1031   case ARM64::LDURQi:
1032   case ARM64::STURQi:
1033   case ARM64::LDRQpre:
1034   case ARM64::STRQpre:
1035   case ARM64::LDRQpost:
1036   case ARM64::STRQpost:
1037     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1038     break;
1039   case ARM64::LDURDi:
1040   case ARM64::STURDi:
1041   case ARM64::LDRDpre:
1042   case ARM64::STRDpre:
1043   case ARM64::LDRDpost:
1044   case ARM64::STRDpost:
1045     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1046     break;
1047   case ARM64::LDURSi:
1048   case ARM64::STURSi:
1049   case ARM64::LDRSpre:
1050   case ARM64::STRSpre:
1051   case ARM64::LDRSpost:
1052   case ARM64::STRSpost:
1053     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1054     break;
1055   case ARM64::LDURHi:
1056   case ARM64::STURHi:
1057   case ARM64::LDRHpre:
1058   case ARM64::STRHpre:
1059   case ARM64::LDRHpost:
1060   case ARM64::STRHpost:
1061     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1062     break;
1063   case ARM64::LDURBi:
1064   case ARM64::STURBi:
1065   case ARM64::LDRBpre:
1066   case ARM64::STRBpre:
1067   case ARM64::LDRBpost:
1068   case ARM64::STRBpost:
1069     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1070     break;
1071   }
1072
1073   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1074   Inst.addOperand(MCOperand::CreateImm(offset));
1075
1076   bool IsLoad = fieldFromInstruction(insn, 22, 1);
1077   bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1078   bool IsFP = fieldFromInstruction(insn, 26, 1);
1079
1080   // Cannot write back to a transfer register (but xzr != sp).
1081   if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1082     return SoftFail;
1083
1084   return Success;
1085 }
1086
1087 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
1088                                                    uint32_t insn, uint64_t Addr,
1089                                                    const void *Decoder) {
1090   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1091   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1092   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1093   unsigned Rs = fieldFromInstruction(insn, 16, 5);
1094
1095   unsigned Opcode = Inst.getOpcode();
1096   switch (Opcode) {
1097   default:
1098     return Fail;
1099   case ARM64::STLXRW:
1100   case ARM64::STLXRB:
1101   case ARM64::STLXRH:
1102   case ARM64::STXRW:
1103   case ARM64::STXRB:
1104   case ARM64::STXRH:
1105     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1106   // FALLTHROUGH
1107   case ARM64::LDARW:
1108   case ARM64::LDARB:
1109   case ARM64::LDARH:
1110   case ARM64::LDAXRW:
1111   case ARM64::LDAXRB:
1112   case ARM64::LDAXRH:
1113   case ARM64::LDXRW:
1114   case ARM64::LDXRB:
1115   case ARM64::LDXRH:
1116   case ARM64::STLRW:
1117   case ARM64::STLRB:
1118   case ARM64::STLRH:
1119     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1120     break;
1121   case ARM64::STLXRX:
1122   case ARM64::STXRX:
1123     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1124   // FALLTHROUGH
1125   case ARM64::LDARX:
1126   case ARM64::LDAXRX:
1127   case ARM64::LDXRX:
1128   case ARM64::STLRX:
1129     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1130     break;
1131   case ARM64::STLXPW:
1132   case ARM64::STXPW:
1133     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1134   // FALLTHROUGH
1135   case ARM64::LDAXPW:
1136   case ARM64::LDXPW:
1137     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1138     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1139     break;
1140   case ARM64::STLXPX:
1141   case ARM64::STXPX:
1142     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1143   // FALLTHROUGH
1144   case ARM64::LDAXPX:
1145   case ARM64::LDXPX:
1146     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1147     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1148     break;
1149   }
1150
1151   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1152
1153   // You shouldn't load to the same register twice in an instruction...
1154   if ((Opcode == ARM64::LDAXPW || Opcode == ARM64::LDXPW ||
1155        Opcode == ARM64::LDAXPX || Opcode == ARM64::LDXPX) &&
1156       Rt == Rt2)
1157     return SoftFail;
1158
1159   return Success;
1160 }
1161
1162 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
1163                                               uint64_t Addr,
1164                                               const void *Decoder) {
1165   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1166   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1167   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1168   int64_t offset = fieldFromInstruction(insn, 15, 7);
1169   bool IsLoad = fieldFromInstruction(insn, 22, 1);
1170
1171   // offset is a 7-bit signed immediate, so sign extend it to
1172   // fill the unsigned.
1173   if (offset & (1 << (7 - 1)))
1174     offset |= ~((1LL << 7) - 1);
1175
1176   unsigned Opcode = Inst.getOpcode();
1177   bool NeedsDisjointWritebackTransfer = false;
1178
1179   // First operand is always writeback of base register.
1180   switch (Opcode) {
1181   default:
1182     break;
1183   case ARM64::LDPXpost:
1184   case ARM64::STPXpost:
1185   case ARM64::LDPSWpost:
1186   case ARM64::LDPXpre:
1187   case ARM64::STPXpre:
1188   case ARM64::LDPSWpre:
1189   case ARM64::LDPWpost:
1190   case ARM64::STPWpost:
1191   case ARM64::LDPWpre:
1192   case ARM64::STPWpre:
1193   case ARM64::LDPQpost:
1194   case ARM64::STPQpost:
1195   case ARM64::LDPQpre:
1196   case ARM64::STPQpre:
1197   case ARM64::LDPDpost:
1198   case ARM64::STPDpost:
1199   case ARM64::LDPDpre:
1200   case ARM64::STPDpre:
1201   case ARM64::LDPSpost:
1202   case ARM64::STPSpost:
1203   case ARM64::LDPSpre:
1204   case ARM64::STPSpre:
1205     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1206     break;
1207   }
1208
1209   switch (Opcode) {
1210   default:
1211     return Fail;
1212   case ARM64::LDPXpost:
1213   case ARM64::STPXpost:
1214   case ARM64::LDPSWpost:
1215   case ARM64::LDPXpre:
1216   case ARM64::STPXpre:
1217   case ARM64::LDPSWpre:
1218     NeedsDisjointWritebackTransfer = true;
1219     // Fallthrough
1220   case ARM64::LDNPXi:
1221   case ARM64::STNPXi:
1222   case ARM64::LDPXi:
1223   case ARM64::STPXi:
1224   case ARM64::LDPSWi:
1225     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1226     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1227     break;
1228   case ARM64::LDPWpost:
1229   case ARM64::STPWpost:
1230   case ARM64::LDPWpre:
1231   case ARM64::STPWpre:
1232     NeedsDisjointWritebackTransfer = true;
1233     // Fallthrough
1234   case ARM64::LDNPWi:
1235   case ARM64::STNPWi:
1236   case ARM64::LDPWi:
1237   case ARM64::STPWi:
1238     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1239     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1240     break;
1241   case ARM64::LDNPQi:
1242   case ARM64::STNPQi:
1243   case ARM64::LDPQpost:
1244   case ARM64::STPQpost:
1245   case ARM64::LDPQi:
1246   case ARM64::STPQi:
1247   case ARM64::LDPQpre:
1248   case ARM64::STPQpre:
1249     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1250     DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1251     break;
1252   case ARM64::LDNPDi:
1253   case ARM64::STNPDi:
1254   case ARM64::LDPDpost:
1255   case ARM64::STPDpost:
1256   case ARM64::LDPDi:
1257   case ARM64::STPDi:
1258   case ARM64::LDPDpre:
1259   case ARM64::STPDpre:
1260     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1261     DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1262     break;
1263   case ARM64::LDNPSi:
1264   case ARM64::STNPSi:
1265   case ARM64::LDPSpost:
1266   case ARM64::STPSpost:
1267   case ARM64::LDPSi:
1268   case ARM64::STPSi:
1269   case ARM64::LDPSpre:
1270   case ARM64::STPSpre:
1271     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1272     DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1273     break;
1274   }
1275
1276   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1277   Inst.addOperand(MCOperand::CreateImm(offset));
1278
1279   // You shouldn't load to the same register twice in an instruction...
1280   if (IsLoad && Rt == Rt2)
1281     return SoftFail;
1282
1283   // ... or do any operation that writes-back to a transfer register. But note
1284   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1285   if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1286     return SoftFail;
1287
1288   return Success;
1289 }
1290
1291 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
1292                                                 uint32_t insn, uint64_t Addr,
1293                                                 const void *Decoder) {
1294   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1295   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1296   unsigned Rm = fieldFromInstruction(insn, 16, 5);
1297   unsigned extend = fieldFromInstruction(insn, 10, 6);
1298
1299   unsigned shift = extend & 0x7;
1300   if (shift > 4)
1301     return Fail;
1302
1303   switch (Inst.getOpcode()) {
1304   default:
1305     return Fail;
1306   case ARM64::ADDWrx:
1307   case ARM64::SUBWrx:
1308     DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1309     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1310     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1311     break;
1312   case ARM64::ADDSWrx:
1313   case ARM64::SUBSWrx:
1314     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1315     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1316     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1317     break;
1318   case ARM64::ADDXrx:
1319   case ARM64::SUBXrx:
1320     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1321     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1322     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1323     break;
1324   case ARM64::ADDSXrx:
1325   case ARM64::SUBSXrx:
1326     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1327     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1328     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1329     break;
1330   case ARM64::ADDXrx64:
1331   case ARM64::SUBXrx64:
1332     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1333     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1334     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1335     break;
1336   case ARM64::SUBSXrx64:
1337   case ARM64::ADDSXrx64:
1338     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1339     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1340     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1341     break;
1342   }
1343
1344   Inst.addOperand(MCOperand::CreateImm(extend));
1345   return Success;
1346 }
1347
1348 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
1349                                                 uint32_t insn, uint64_t Addr,
1350                                                 const void *Decoder) {
1351   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1352   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1353   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1354   unsigned imm;
1355
1356   if (Datasize) {
1357     if (Inst.getOpcode() == ARM64::ANDSXri)
1358       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1359     else
1360       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1361     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1362     imm = fieldFromInstruction(insn, 10, 13);
1363     if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 64))
1364       return Fail;
1365   } else {
1366     if (Inst.getOpcode() == ARM64::ANDSWri)
1367       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1368     else
1369       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1370     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1371     imm = fieldFromInstruction(insn, 10, 12);
1372     if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 32))
1373       return Fail;
1374   }
1375   Inst.addOperand(MCOperand::CreateImm(imm));
1376   return Success;
1377 }
1378
1379 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
1380                                             uint64_t Addr,
1381                                             const void *Decoder) {
1382   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1383   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1384   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1385   imm |= fieldFromInstruction(insn, 5, 5);
1386
1387   if (Inst.getOpcode() == ARM64::MOVID)
1388     DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1389   else
1390     DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1391
1392   Inst.addOperand(MCOperand::CreateImm(imm));
1393
1394   switch (Inst.getOpcode()) {
1395   default:
1396     break;
1397   case ARM64::MOVIv4i16:
1398   case ARM64::MOVIv8i16:
1399   case ARM64::MVNIv4i16:
1400   case ARM64::MVNIv8i16:
1401   case ARM64::MOVIv2i32:
1402   case ARM64::MOVIv4i32:
1403   case ARM64::MVNIv2i32:
1404   case ARM64::MVNIv4i32:
1405     Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1406     break;
1407   case ARM64::MOVIv2s_msl:
1408   case ARM64::MOVIv4s_msl:
1409   case ARM64::MVNIv2s_msl:
1410   case ARM64::MVNIv4s_msl:
1411     Inst.addOperand(MCOperand::CreateImm(cmode & 1 ? 0x110 : 0x108));
1412     break;
1413   }
1414
1415   return Success;
1416 }
1417
1418 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
1419                                                 uint32_t insn, uint64_t Addr,
1420                                                 const void *Decoder) {
1421   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1422   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1423   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1424   imm |= fieldFromInstruction(insn, 5, 5);
1425
1426   // Tied operands added twice.
1427   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1428   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1429
1430   Inst.addOperand(MCOperand::CreateImm(imm));
1431   Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1432
1433   return Success;
1434 }
1435
1436 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
1437                                          uint64_t Addr, const void *Decoder) {
1438   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1439   int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1440   imm |= fieldFromInstruction(insn, 29, 2);
1441   const ARM64Disassembler *Dis =
1442       static_cast<const ARM64Disassembler *>(Decoder);
1443
1444   // Sign-extend the 21-bit immediate.
1445   if (imm & (1 << (21 - 1)))
1446     imm |= ~((1LL << 21) - 1);
1447
1448   DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1449   if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1450     Inst.addOperand(MCOperand::CreateImm(imm));
1451
1452   return Success;
1453 }
1454
1455 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
1456                                         uint64_t Addr, const void *Decoder) {
1457   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1458   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1459   unsigned Imm = fieldFromInstruction(insn, 10, 14);
1460   unsigned S = fieldFromInstruction(insn, 29, 1);
1461   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1462
1463   unsigned ShifterVal = (Imm >> 12) & 3;
1464   unsigned ImmVal = Imm & 0xFFF;
1465   const ARM64Disassembler *Dis =
1466       static_cast<const ARM64Disassembler *>(Decoder);
1467
1468   if (ShifterVal != 0 && ShifterVal != 1)
1469     return Fail;
1470
1471   if (Datasize) {
1472     if (Rd == 31 && !S)
1473       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1474     else
1475       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1476     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1477   } else {
1478     if (Rd == 31 && !S)
1479       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1480     else
1481       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1482     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1483   }
1484
1485   if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1486     Inst.addOperand(MCOperand::CreateImm(ImmVal));
1487   Inst.addOperand(MCOperand::CreateImm(12 * ShifterVal));
1488   return Success;
1489 }
1490
1491 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
1492                                               uint64_t Addr,
1493                                               const void *Decoder) {
1494   int64_t imm = fieldFromInstruction(insn, 0, 26);
1495   const ARM64Disassembler *Dis =
1496       static_cast<const ARM64Disassembler *>(Decoder);
1497
1498   // Sign-extend the 26-bit immediate.
1499   if (imm & (1 << (26 - 1)))
1500     imm |= ~((1LL << 26) - 1);
1501
1502   if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4))
1503     Inst.addOperand(MCOperand::CreateImm(imm));
1504
1505   return Success;
1506 }
1507
1508 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
1509                                                   uint32_t insn, uint64_t Addr,
1510                                                   const void *Decoder) {
1511   uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1512   uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1513   uint64_t crm = fieldFromInstruction(insn, 8, 4);
1514
1515   uint64_t pstate_field = (op1 << 3) | op2;
1516
1517   Inst.addOperand(MCOperand::CreateImm(pstate_field));
1518   Inst.addOperand(MCOperand::CreateImm(crm));
1519
1520   bool ValidNamed;
1521   (void)ARM64PState::PStateMapper().toString(pstate_field, ValidNamed);
1522
1523   return ValidNamed ? Success : Fail;
1524 }
1525
1526 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
1527                                         uint64_t Addr, const void *Decoder) {
1528   uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1529   uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1530   bit |= fieldFromInstruction(insn, 19, 5);
1531   int64_t dst = fieldFromInstruction(insn, 5, 14);
1532   const ARM64Disassembler *Dis =
1533       static_cast<const ARM64Disassembler *>(Decoder);
1534
1535   // Sign-extend 14-bit immediate.
1536   if (dst & (1 << (14 - 1)))
1537     dst |= ~((1LL << 14) - 1);
1538
1539   if (fieldFromInstruction(insn, 31, 1) == 0)
1540     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1541   else
1542     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1543   Inst.addOperand(MCOperand::CreateImm(bit));
1544   if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4))
1545     Inst.addOperand(MCOperand::CreateImm(dst));
1546
1547   return Success;
1548 }