lib/Target/ARM64/ARM64TargetMachine.cpp

   1 //===-- ARM64TargetMachine.cpp - Define TargetMachine for ARM64 -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARM64.h"
  14 #include "ARM64TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/CodeGen/Passes.h"
  17 #include "llvm/Support/CommandLine.h"
  18 #include "llvm/Support/TargetRegistry.h"
  19 #include "llvm/Target/TargetOptions.h"
  20 #include "llvm/Transforms/Scalar.h"
  21 using namespace llvm;
  22
  23 static cl::opt<bool> EnableCCMP("arm64-ccmp",
  24                                 cl::desc("Enable the CCMP formation pass"),
  25                                 cl::init(true));
  26
  27 static cl::opt<bool> EnableStPairSuppress("arm64-stp-suppress", cl::Hidden,
  28                                           cl::desc("Suppress STP for ARM64"),
  29                                           cl::init(true));
  30
  31 static cl::opt<bool>
  32 EnablePromoteConstant("arm64-promote-const", cl::Hidden,
  33                       cl::desc("Enable the promote constant pass"),
  34                       cl::init(true));
  35
  36 static cl::opt<bool>
  37 EnableCollectLOH("arm64-collect-loh", cl::Hidden,
  38                  cl::desc("Enable the pass that emits the linker"
  39                           " optimization hints (LOH)"),
  40                  cl::init(true));
  41
  42 extern "C" void LLVMInitializeARM64Target() {
  43   // Register the target.
  44   RegisterTargetMachine<ARM64TargetMachine> X(TheARM64Target);
  45 }
  46
  47 /// TargetMachine ctor - Create an ARM64 architecture model.
  48 ///
  49 ARM64TargetMachine::ARM64TargetMachine(const Target &T, StringRef TT,
  50                                        StringRef CPU, StringRef FS,
  51                                        const TargetOptions &Options,
  52                                        Reloc::Model RM, CodeModel::Model CM,
  53                                        CodeGenOpt::Level OL)
  54     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
  55       Subtarget(TT, CPU, FS),
  56       DL(Subtarget.isTargetMachO() ? "e-m:o-i64:64-i128:128-n32:64-S128"
  57                                    : "e-m:e-i64:64-i128:128-n32:64-S128"),
  58       InstrInfo(Subtarget), TLInfo(*this), FrameLowering(*this, Subtarget),
  59       TSInfo(*this) {
  60   initAsmInfo();
  61 }
  62
  63 namespace {
  64 /// ARM64 Code Generator Pass Configuration Options.
  65 class ARM64PassConfig : public TargetPassConfig {
  66 public:
  67   ARM64PassConfig(ARM64TargetMachine *TM, PassManagerBase &PM)
  68       : TargetPassConfig(TM, PM) {}
  69
  70   ARM64TargetMachine &getARM64TargetMachine() const {
  71     return getTM<ARM64TargetMachine>();
  72   }
  73
  74   virtual bool addPreISel();
  75   virtual bool addInstSelector();
  76   virtual bool addILPOpts();
  77   virtual bool addPreRegAlloc();
  78   virtual bool addPostRegAlloc();
  79   virtual bool addPreSched2();
  80   virtual bool addPreEmitPass();
  81 };
  82 } // namespace
  83
  84 void ARM64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
  85   // Add first the target-independent BasicTTI pass, then our ARM64 pass. This
  86   // allows the ARM64 pass to delegate to the target independent layer when
  87   // appropriate.
  88   PM.add(createBasicTargetTransformInfoPass(this));
  89   PM.add(createARM64TargetTransformInfoPass(this));
  90 }
  91
  92 TargetPassConfig *ARM64TargetMachine::createPassConfig(PassManagerBase &PM) {
  93   return new ARM64PassConfig(this, PM);
  94 }
  95
  96 // Pass Pipeline Configuration
  97 bool ARM64PassConfig::addPreISel() {
  98   // Run promote constant before global merge, so that the promoted constants
  99   // get a chance to be merged
 100   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
 101     addPass(createARM64PromoteConstantPass());
 102   if (TM->getOptLevel() != CodeGenOpt::None)
 103     addPass(createGlobalMergePass(TM));
 104   if (TM->getOptLevel() != CodeGenOpt::None)
 105     addPass(createARM64AddressTypePromotionPass());
 106   return false;
 107 }
 108
 109 bool ARM64PassConfig::addInstSelector() {
 110   addPass(createARM64ISelDag(getARM64TargetMachine(), getOptLevel()));
 111
 112   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
 113   // references to _TLS_MODULE_BASE_ as possible.
 114   if (TM->getSubtarget<ARM64Subtarget>().isTargetELF() &&
 115       getOptLevel() != CodeGenOpt::None)
 116     addPass(createARM64CleanupLocalDynamicTLSPass());
 117
 118   return false;
 119 }
 120
 121 bool ARM64PassConfig::addILPOpts() {
 122   if (EnableCCMP)
 123     addPass(createARM64ConditionalCompares());
 124   addPass(&EarlyIfConverterID);
 125   if (EnableStPairSuppress)
 126     addPass(createARM64StorePairSuppressPass());
 127   return true;
 128 }
 129
 130 bool ARM64PassConfig::addPreRegAlloc() {
 131   // Use AdvSIMD scalar instructions whenever profitable.
 132   addPass(createARM64AdvSIMDScalar());
 133   return true;
 134 }
 135
 136 bool ARM64PassConfig::addPostRegAlloc() {
 137   // Change dead register definitions to refer to the zero register.
 138   addPass(createARM64DeadRegisterDefinitions());
 139   return true;
 140 }
 141
 142 bool ARM64PassConfig::addPreSched2() {
 143   // Expand some pseudo instructions to allow proper scheduling.
 144   addPass(createARM64ExpandPseudoPass());
 145   // Use load/store pair instructions when possible.
 146   addPass(createARM64LoadStoreOptimizationPass());
 147   return true;
 148 }
 149
 150 bool ARM64PassConfig::addPreEmitPass() {
 151   // Relax conditional branch instructions if they're otherwise out of
 152   // range of their destination.
 153   addPass(createARM64BranchRelaxation());
 154   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH)
 155     addPass(createARM64CollectLOHPass());
 156   return true;
 157 }