lib/Target/ARM/Thumb2RegisterInfo.cpp

   1 //===- Thumb2RegisterInfo.cpp - Thumb-2 Register Information ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Thumb-2 implementation of the TargetRegisterInfo
  11 // class.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "ARM.h"
  16 #include "ARMAddressingModes.h"
  17 #include "ARMBaseInstrInfo.h"
  18 #include "ARMMachineFunctionInfo.h"
  19 #include "ARMSubtarget.h"
  20 #include "Thumb2InstrInfo.h"
  21 #include "Thumb2RegisterInfo.h"
  22 #include "llvm/Constants.h"
  23 #include "llvm/DerivedTypes.h"
  24 #include "llvm/Function.h"
  25 #include "llvm/LLVMContext.h"
  26 #include "llvm/CodeGen/MachineConstantPool.h"
  27 #include "llvm/CodeGen/MachineFrameInfo.h"
  28 #include "llvm/CodeGen/MachineFunction.h"
  29 #include "llvm/CodeGen/MachineInstrBuilder.h"
  30 #include "llvm/CodeGen/MachineLocation.h"
  31 #include "llvm/CodeGen/MachineRegisterInfo.h"
  32 #include "llvm/Target/TargetFrameInfo.h"
  33 #include "llvm/Target/TargetMachine.h"
  34 #include "llvm/ADT/BitVector.h"
  35 #include "llvm/ADT/SmallVector.h"
  36 #include "llvm/Support/ErrorHandling.h"
  37 using namespace llvm;
  38
  39 Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
  40                                        const ARMSubtarget &sti)
  41   : ARMBaseRegisterInfo(tii, sti) {
  42 }
  43
  44 /// emitLoadConstPool - Emits a load from constpool to materialize the
  45 /// specified immediate.
  46 void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
  47                                            MachineBasicBlock::iterator &MBBI,
  48                                            DebugLoc dl,
  49                                            unsigned DestReg, unsigned SubIdx,
  50                                            int Val,
  51                                            ARMCC::CondCodes Pred,
  52                                            unsigned PredReg) const {
  53   MachineFunction &MF = *MBB.getParent();
  54   MachineConstantPool *ConstantPool = MF.getConstantPool();
  55   const Constant *C = ConstantInt::get(
  56            Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
  57   unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
  58
  59   BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
  60     .addReg(DestReg, getDefRegState(true), SubIdx)
  61     .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0);
  62 }