1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "thumb2-it"
12 #include "ARMMachineFunctionInfo.h"
13 #include "Thumb2InstrInfo.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/Support/Compiler.h"
18 #include "llvm/ADT/Statistic.h"
21 STATISTIC(NumITs, "Number of IT blocks inserted");
24 struct VISIBILITY_HIDDEN Thumb2ITBlockPass : public MachineFunctionPass {
26 Thumb2ITBlockPass() : MachineFunctionPass(&ID) {}
28 const Thumb2InstrInfo *TII;
31 virtual bool runOnMachineFunction(MachineFunction &Fn);
33 virtual const char *getPassName() const {
34 return "Thumb IT blocks insertion pass";
38 bool InsertITBlocks(MachineBasicBlock &MBB);
40 char Thumb2ITBlockPass::ID = 0;
43 static ARMCC::CondCodes getPredicate(const MachineInstr *MI, unsigned &PredReg){
44 unsigned Opc = MI->getOpcode();
45 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
47 return llvm::getInstrPredicate(MI, PredReg);
50 bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
51 bool Modified = false;
53 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
55 MachineInstr *MI = &*MBBI;
56 DebugLoc dl = MI->getDebugLoc();
58 ARMCC::CondCodes CC = getPredicate(MI, PredReg);
60 // Splitting t2MOVi32imm into a pair of t2MOVi16 + t2MOVTi16 here.
61 // The only reason it was a single instruction was so it could be
62 // re-materialized. We want to split it before this and the thumb2
63 // size reduction pass to make sure the IT mask is correct and expose
64 // width reduction opportunities. It doesn't make sense to do this in a
65 // separate pass so here it is.
66 if (MI->getOpcode() == ARM::t2MOVi32imm) {
67 unsigned DstReg = MI->getOperand(0).getReg();
68 bool DstDead = MI->getOperand(0).isDead(); // Is this possible?
69 unsigned Imm = MI->getOperand(1).getImm();
70 unsigned Lo16 = Imm & 0xffff;
71 unsigned Hi16 = (Imm >> 16) & 0xffff;
72 BuildMI(MBB, MBBI, dl, TII->get(ARM::t2MOVi16), DstReg)
73 .addImm(Lo16).addImm(CC).addReg(PredReg);
74 BuildMI(MBB, MBBI, dl, TII->get(ARM::t2MOVTi16))
75 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead))
76 .addReg(DstReg).addImm(Hi16).addImm(CC).addReg(PredReg);
79 MI->eraseFromParent();
83 if (CC == ARMCC::AL) {
88 // Insert an IT instruction.
89 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
94 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
95 unsigned Mask = 0, Pos = 3;
96 while (MBBI != E && Pos) {
98 ARMCC::CondCodes NCC = getPredicate(&*MBBI, Dummy);
101 } else if (NCC != CC)
115 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
116 const TargetMachine &TM = Fn.getTarget();
117 AFI = Fn.getInfo<ARMFunctionInfo>();
118 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
120 if (!AFI->isThumbFunction())
123 bool Modified = false;
124 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
126 MachineBasicBlock &MBB = *MFI;
127 Modified |= InsertITBlocks(MBB);
133 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
135 FunctionPass *llvm::createThumb2ITBlockPass() {
136 return new Thumb2ITBlockPass();