1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "thumb2-it"
12 #include "ARMMachineFunctionInfo.h"
13 #include "Thumb2InstrInfo.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/CodeGen/MachineInstrBundle.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/Statistic.h"
23 STATISTIC(NumITs, "Number of IT blocks inserted");
24 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
27 class Thumb2ITBlockPass : public MachineFunctionPass {
32 Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
34 const Thumb2InstrInfo *TII;
35 const TargetRegisterInfo *TRI;
38 virtual bool runOnMachineFunction(MachineFunction &Fn);
40 virtual const char *getPassName() const {
41 return "Thumb IT blocks insertion pass";
45 bool MoveCopyOutOfITBlock(MachineInstr *MI,
46 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
47 SmallSet<unsigned, 4> &Defs,
48 SmallSet<unsigned, 4> &Uses);
49 bool InsertITInstructions(MachineBasicBlock &MBB);
51 char Thumb2ITBlockPass::ID = 0;
54 /// TrackDefUses - Tracking what registers are being defined and used by
55 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
56 /// in the IT block that are defined before the IT instruction.
57 static void TrackDefUses(MachineInstr *MI,
58 SmallSet<unsigned, 4> &Defs,
59 SmallSet<unsigned, 4> &Uses,
60 const TargetRegisterInfo *TRI) {
61 SmallVector<unsigned, 4> LocalDefs;
62 SmallVector<unsigned, 4> LocalUses;
64 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
65 MachineOperand &MO = MI->getOperand(i);
68 unsigned Reg = MO.getReg();
69 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
72 LocalUses.push_back(Reg);
74 LocalDefs.push_back(Reg);
77 for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
78 unsigned Reg = LocalUses[i];
80 for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
85 for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
86 unsigned Reg = LocalDefs[i];
88 for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
96 static bool isCopy(MachineInstr *MI) {
97 switch (MI->getOpcode()) {
109 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
110 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
111 SmallSet<unsigned, 4> &Defs,
112 SmallSet<unsigned, 4> &Uses) {
115 // llvm models select's as two-address instructions. That means a copy
116 // is inserted before a t2MOVccr, etc. If the copy is scheduled in
117 // between selects we would end up creating multiple IT blocks.
118 assert(MI->getOperand(0).getSubReg() == 0 &&
119 MI->getOperand(1).getSubReg() == 0 &&
120 "Sub-register indices still around?");
122 unsigned DstReg = MI->getOperand(0).getReg();
123 unsigned SrcReg = MI->getOperand(1).getReg();
125 // First check if it's safe to move it.
126 if (Uses.count(DstReg) || Defs.count(SrcReg))
129 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
137 // we don't want this to be converted to:
145 const MCInstrDesc &MCID = MI->getDesc();
146 if (MI->hasOptionalDef() &&
147 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
150 // Then peek at the next instruction to see if it's predicated on CC or OCC.
151 // If not, then there is nothing to be gained by moving the copy.
152 MachineBasicBlock::iterator I = MI; ++I;
153 MachineBasicBlock::iterator E = MI->getParent()->end();
154 while (I != E && I->isDebugValue())
157 unsigned NPredReg = 0;
158 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
159 if (NCC == CC || NCC == OCC)
165 bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
166 bool Modified = false;
168 SmallSet<unsigned, 4> Defs;
169 SmallSet<unsigned, 4> Uses;
170 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
172 MachineInstr *MI = &*MBBI;
173 DebugLoc dl = MI->getDebugLoc();
174 unsigned PredReg = 0;
175 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
176 if (CC == ARMCC::AL) {
183 TrackDefUses(MI, Defs, Uses, TRI);
185 // Insert an IT instruction.
186 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
189 // Add implicit use of ITSTATE to IT block instructions.
190 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
191 true/*isImp*/, false/*isKill*/));
193 MachineInstr *LastITMI = MI;
194 MachineBasicBlock::iterator InsertPos = MIB;
198 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
199 unsigned Mask = 0, Pos = 3;
200 // Branches, including tricky ones like LDM_RET, need to end an IT
201 // block so check the instruction we just put in the block.
202 for (; MBBI != E && Pos &&
203 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
204 if (MBBI->isDebugValue())
207 MachineInstr *NMI = &*MBBI;
210 unsigned NPredReg = 0;
211 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg);
212 if (NCC == CC || NCC == OCC) {
213 Mask |= (NCC & 1) << Pos;
214 // Add implicit use of ITSTATE.
215 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
216 true/*isImp*/, false/*isKill*/));
219 if (NCC == ARMCC::AL &&
220 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
223 MBB.insert(InsertPos, NMI);
229 TrackDefUses(NMI, Defs, Uses, TRI);
235 // Tag along (firstcond[0] << 4) with the mask.
236 Mask |= (CC & 1) << 4;
239 // Last instruction in IT block kills ITSTATE.
240 LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
242 // Finalize the bundle.
243 MachineBasicBlock::instr_iterator LI = LastITMI;
244 finalizeBundle(MBB, InsertPos.getInstrIterator(), llvm::next(LI));
253 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
254 const TargetMachine &TM = Fn.getTarget();
255 AFI = Fn.getInfo<ARMFunctionInfo>();
256 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
257 TRI = TM.getRegisterInfo();
259 if (!AFI->isThumbFunction())
262 // IT block insertion invalidates accurate register liveness.
263 Fn.getRegInfo().invalidateLiveness();
265 bool Modified = false;
266 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
267 MachineBasicBlock &MBB = *MFI;
269 Modified |= InsertITInstructions(MBB);
273 AFI->setHasITBlocks(true);
278 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
280 FunctionPass *llvm::createThumb2ITBlockPass() {
281 return new Thumb2ITBlockPass();