1 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1InstrInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/MC/MCInst.h"
26 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
27 : ARMBaseInstrInfo(STI), RI(*this, STI) {
30 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
31 void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
32 NopInst.setOpcode(ARM::tMOVr);
33 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
34 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
35 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
36 NopInst.addOperand(MCOperand::CreateReg(0));
39 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
43 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator I, DebugLoc DL,
45 unsigned DestReg, unsigned SrcReg,
47 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
48 .addReg(SrcReg, getKillRegState(KillSrc)));
49 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
50 "Thumb1 can only copy GPR registers");
53 void Thumb1InstrInfo::
54 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
55 unsigned SrcReg, bool isKill, int FI,
56 const TargetRegisterClass *RC,
57 const TargetRegisterInfo *TRI) const {
58 assert((RC == ARM::tGPRRegisterClass ||
59 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
60 isARMLowRegister(SrcReg))) && "Unknown regclass!");
62 if (RC == ARM::tGPRRegisterClass ||
63 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
64 isARMLowRegister(SrcReg))) {
66 if (I != MBB.end()) DL = I->getDebugLoc();
68 MachineFunction &MF = *MBB.getParent();
69 MachineFrameInfo &MFI = *MF.getFrameInfo();
70 MachineMemOperand *MMO =
71 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
72 MachineMemOperand::MOStore,
73 MFI.getObjectSize(FI),
74 MFI.getObjectAlignment(FI));
75 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
76 .addReg(SrcReg, getKillRegState(isKill))
77 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
81 void Thumb1InstrInfo::
82 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
83 unsigned DestReg, int FI,
84 const TargetRegisterClass *RC,
85 const TargetRegisterInfo *TRI) const {
86 assert((RC == ARM::tGPRRegisterClass ||
87 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
88 isARMLowRegister(DestReg))) && "Unknown regclass!");
90 if (RC == ARM::tGPRRegisterClass ||
91 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
92 isARMLowRegister(DestReg))) {
94 if (I != MBB.end()) DL = I->getDebugLoc();
96 MachineFunction &MF = *MBB.getParent();
97 MachineFrameInfo &MFI = *MF.getFrameInfo();
98 MachineMemOperand *MMO =
99 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
100 MachineMemOperand::MOLoad,
101 MFI.getObjectSize(FI),
102 MFI.getObjectAlignment(FI));
103 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
104 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));