1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1InstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "Thumb1InstrInfo.h"
28 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
29 : ARMBaseInstrInfo(STI), RI(*this, STI) {
32 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
36 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator I, DebugLoc DL,
38 unsigned DestReg, unsigned SrcReg,
40 bool tDest = ARM::tGPRRegClass.contains(DestReg);
41 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
42 unsigned Opc = ARM::tMOVgpr2gpr;
46 Opc = ARM::tMOVtgpr2gpr;
48 Opc = ARM::tMOVgpr2tgpr;
50 BuildMI(MBB, I, DL, get(Opc), DestReg)
51 .addReg(SrcReg, getKillRegState(KillSrc));
52 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
53 "Thumb1 can only copy GPR registers");
56 bool Thumb1InstrInfo::
57 canFoldMemoryOperand(const MachineInstr *MI,
58 const SmallVectorImpl<unsigned> &Ops) const {
59 if (Ops.size() != 1) return false;
61 unsigned OpNum = Ops[0];
62 unsigned Opc = MI->getOpcode();
66 case ARM::tMOVtgpr2gpr:
67 case ARM::tMOVgpr2tgpr:
68 case ARM::tMOVgpr2gpr: {
69 if (OpNum == 0) { // move -> store
70 unsigned SrcReg = MI->getOperand(1).getReg();
71 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
72 !isARMLowRegister(SrcReg))
73 // tSpill cannot take a high register operand.
75 } else { // move -> load
76 unsigned DstReg = MI->getOperand(0).getReg();
77 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
78 !isARMLowRegister(DstReg))
79 // tRestore cannot target a high register operand.
89 void Thumb1InstrInfo::
90 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
91 unsigned SrcReg, bool isKill, int FI,
92 const TargetRegisterClass *RC,
93 const TargetRegisterInfo *TRI) const {
94 assert((RC == ARM::tGPRRegisterClass ||
95 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
96 isARMLowRegister(SrcReg))) && "Unknown regclass!");
98 if (RC == ARM::tGPRRegisterClass ||
99 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
100 isARMLowRegister(SrcReg))) {
102 if (I != MBB.end()) DL = I->getDebugLoc();
104 MachineFunction &MF = *MBB.getParent();
105 MachineFrameInfo &MFI = *MF.getFrameInfo();
106 MachineMemOperand *MMO =
107 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
108 MachineMemOperand::MOStore, 0,
109 MFI.getObjectSize(FI),
110 MFI.getObjectAlignment(FI));
111 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
112 .addReg(SrcReg, getKillRegState(isKill))
113 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
117 void Thumb1InstrInfo::
118 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
119 unsigned DestReg, int FI,
120 const TargetRegisterClass *RC,
121 const TargetRegisterInfo *TRI) const {
122 assert((RC == ARM::tGPRRegisterClass ||
123 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
124 isARMLowRegister(DestReg))) && "Unknown regclass!");
126 if (RC == ARM::tGPRRegisterClass ||
127 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
128 isARMLowRegister(DestReg))) {
130 if (I != MBB.end()) DL = I->getDebugLoc();
132 MachineFunction &MF = *MBB.getParent();
133 MachineFrameInfo &MFI = *MF.getFrameInfo();
134 MachineMemOperand *MMO =
135 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
136 MachineMemOperand::MOLoad, 0,
137 MFI.getObjectSize(FI),
138 MFI.getObjectAlignment(FI));
139 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
140 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
144 bool Thumb1InstrInfo::
145 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
146 MachineBasicBlock::iterator MI,
147 const std::vector<CalleeSavedInfo> &CSI,
148 const TargetRegisterInfo *TRI) const {
153 if (MI != MBB.end()) DL = MI->getDebugLoc();
155 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
157 for (unsigned i = CSI.size(); i != 0; --i) {
158 unsigned Reg = CSI[i-1].getReg();
161 // Add the callee-saved register as live-in unless it's LR and
162 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
163 // then it's already added to the function and entry block live-in sets.
164 if (Reg == ARM::LR) {
165 MachineFunction &MF = *MBB.getParent();
166 if (MF.getFrameInfo()->isReturnAddressTaken() &&
167 MF.getRegInfo().isLiveIn(Reg))
174 MIB.addReg(Reg, getKillRegState(isKill));
179 bool Thumb1InstrInfo::
180 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
181 MachineBasicBlock::iterator MI,
182 const std::vector<CalleeSavedInfo> &CSI,
183 const TargetRegisterInfo *TRI) const {
184 MachineFunction &MF = *MBB.getParent();
185 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
189 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
190 DebugLoc DL = MI->getDebugLoc();
191 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
194 bool NumRegs = false;
195 for (unsigned i = CSI.size(); i != 0; --i) {
196 unsigned Reg = CSI[i-1].getReg();
197 if (Reg == ARM::LR) {
198 // Special epilogue for vararg functions. See emitEpilogue
202 (*MIB).setDesc(get(ARM::tPOP_RET));
205 MIB.addReg(Reg, getDefRegState(true));
209 // It's illegal to emit pop instruction without operands.
211 MBB.insert(MI, &*MIB);
213 MF.DeleteMachineInstr(MIB);
218 MachineInstr *Thumb1InstrInfo::
219 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
220 const SmallVectorImpl<unsigned> &Ops, int FI) const {
221 if (Ops.size() != 1) return NULL;
223 unsigned OpNum = Ops[0];
224 unsigned Opc = MI->getOpcode();
225 MachineInstr *NewMI = NULL;
229 case ARM::tMOVtgpr2gpr:
230 case ARM::tMOVgpr2tgpr:
231 case ARM::tMOVgpr2gpr: {
232 if (OpNum == 0) { // move -> store
233 unsigned SrcReg = MI->getOperand(1).getReg();
234 bool isKill = MI->getOperand(1).isKill();
235 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
236 !isARMLowRegister(SrcReg))
237 // tSpill cannot take a high register operand.
239 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
240 .addReg(SrcReg, getKillRegState(isKill))
241 .addFrameIndex(FI).addImm(0));
242 } else { // move -> load
243 unsigned DstReg = MI->getOperand(0).getReg();
244 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
245 !isARMLowRegister(DstReg))
246 // tRestore cannot target a high register operand.
248 bool isDead = MI->getOperand(0).isDead();
249 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
251 RegState::Define | getDeadRegState(isDead))
252 .addFrameIndex(FI).addImm(0));