1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalValue.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "Thumb1InstrInfo.h"
32 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
33 : ARMBaseInstrInfo(STI), RI(*this, STI) {
36 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
41 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
42 if (MBB.empty()) return false;
44 switch (MBB.back().getOpcode()) {
46 case ARM::tBX_RET_vararg:
59 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator I,
61 unsigned DestReg, unsigned SrcReg,
62 const TargetRegisterClass *DestRC,
63 const TargetRegisterClass *SrcRC) const {
64 DebugLoc DL = DebugLoc::getUnknownLoc();
65 if (I != MBB.end()) DL = I->getDebugLoc();
67 if (DestRC == ARM::GPRRegisterClass) {
68 if (SrcRC == ARM::GPRRegisterClass) {
69 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
71 } else if (SrcRC == ARM::tGPRRegisterClass) {
72 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
75 } else if (DestRC == ARM::tGPRRegisterClass) {
76 if (SrcRC == ARM::GPRRegisterClass) {
77 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
79 } else if (SrcRC == ARM::tGPRRegisterClass) {
80 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
88 bool Thumb1InstrInfo::
89 canFoldMemoryOperand(const MachineInstr *MI,
90 const SmallVectorImpl<unsigned> &Ops) const {
91 if (Ops.size() != 1) return false;
93 unsigned OpNum = Ops[0];
94 unsigned Opc = MI->getOpcode();
98 case ARM::tMOVtgpr2gpr:
99 case ARM::tMOVgpr2tgpr:
100 case ARM::tMOVgpr2gpr: {
101 if (OpNum == 0) { // move -> store
102 unsigned SrcReg = MI->getOperand(1).getReg();
103 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
104 !isARMLowRegister(SrcReg))
105 // tSpill cannot take a high register operand.
107 } else { // move -> load
108 unsigned DstReg = MI->getOperand(0).getReg();
109 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
110 !isARMLowRegister(DstReg))
111 // tRestore cannot target a high register operand.
121 void Thumb1InstrInfo::
122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
123 unsigned SrcReg, bool isKill, int FI,
124 const TargetRegisterClass *RC) const {
125 DebugLoc DL = DebugLoc::getUnknownLoc();
126 if (I != MBB.end()) DL = I->getDebugLoc();
128 assert((RC == ARM::tGPRRegisterClass ||
129 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
130 isARMLowRegister(SrcReg))) && "Unknown regclass!");
132 if (RC == ARM::tGPRRegisterClass) {
133 MachineFunction &MF = *MBB.getParent();
134 MachineFrameInfo &MFI = *MF.getFrameInfo();
135 MachineMemOperand *MMO =
136 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
137 MachineMemOperand::MOStore, 0,
138 MFI.getObjectSize(FI),
139 MFI.getObjectAlignment(FI));
140 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
141 .addReg(SrcReg, getKillRegState(isKill))
142 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
146 void Thumb1InstrInfo::
147 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
148 unsigned DestReg, int FI,
149 const TargetRegisterClass *RC) const {
150 DebugLoc DL = DebugLoc::getUnknownLoc();
151 if (I != MBB.end()) DL = I->getDebugLoc();
153 assert((RC == ARM::tGPRRegisterClass ||
154 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
155 isARMLowRegister(DestReg))) && "Unknown regclass!");
157 if (RC == ARM::tGPRRegisterClass) {
158 MachineFunction &MF = *MBB.getParent();
159 MachineFrameInfo &MFI = *MF.getFrameInfo();
160 MachineMemOperand *MMO =
161 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
162 MachineMemOperand::MOLoad, 0,
163 MFI.getObjectSize(FI),
164 MFI.getObjectAlignment(FI));
165 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
166 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
170 bool Thumb1InstrInfo::
171 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
172 MachineBasicBlock::iterator MI,
173 const std::vector<CalleeSavedInfo> &CSI) const {
177 DebugLoc DL = DebugLoc::getUnknownLoc();
178 if (MI != MBB.end()) DL = MI->getDebugLoc();
180 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
182 MIB.addReg(0); // No write back.
183 for (unsigned i = CSI.size(); i != 0; --i) {
184 unsigned Reg = CSI[i-1].getReg();
185 // Add the callee-saved register as live-in. It's killed at the spill.
187 MIB.addReg(Reg, RegState::Kill);
192 bool Thumb1InstrInfo::
193 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
194 MachineBasicBlock::iterator MI,
195 const std::vector<CalleeSavedInfo> &CSI) const {
196 MachineFunction &MF = *MBB.getParent();
197 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
201 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
202 DebugLoc DL = MI->getDebugLoc();
203 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
205 MIB.addReg(0); // No write back.
208 for (unsigned i = CSI.size(); i != 0; --i) {
209 unsigned Reg = CSI[i-1].getReg();
210 if (Reg == ARM::LR) {
211 // Special epilogue for vararg functions. See emitEpilogue
215 (*MIB).setDesc(get(ARM::tPOP_RET));
218 MIB.addReg(Reg, getDefRegState(true));
222 // It's illegal to emit pop instruction without operands.
224 MBB.insert(MI, &*MIB);
229 MachineInstr *Thumb1InstrInfo::
230 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
231 const SmallVectorImpl<unsigned> &Ops, int FI) const {
232 if (Ops.size() != 1) return NULL;
234 unsigned OpNum = Ops[0];
235 unsigned Opc = MI->getOpcode();
236 MachineInstr *NewMI = NULL;
240 case ARM::tMOVtgpr2gpr:
241 case ARM::tMOVgpr2tgpr:
242 case ARM::tMOVgpr2gpr: {
243 if (OpNum == 0) { // move -> store
244 unsigned SrcReg = MI->getOperand(1).getReg();
245 bool isKill = MI->getOperand(1).isKill();
246 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
247 !isARMLowRegister(SrcReg))
248 // tSpill cannot take a high register operand.
250 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
251 .addReg(SrcReg, getKillRegState(isKill))
252 .addFrameIndex(FI).addImm(0));
253 } else { // move -> load
254 unsigned DstReg = MI->getOperand(0).getReg();
255 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
256 !isARMLowRegister(DstReg))
257 // tRestore cannot target a high register operand.
259 bool isDead = MI->getOperand(0).isDead();
260 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
262 RegState::Define | getDeadRegState(isDead))
263 .addFrameIndex(FI).addImm(0));
272 void Thumb1InstrInfo::reMaterialize(MachineBasicBlock &MBB,
273 MachineBasicBlock::iterator I,
274 unsigned DestReg, unsigned SubIdx,
275 const MachineInstr *Orig) const {
276 DebugLoc dl = Orig->getDebugLoc();
277 unsigned Opcode = Orig->getOpcode();
280 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
281 MI->getOperand(0).setReg(DestReg);
285 case ARM::tLDRpci_pic: {
286 MachineFunction &MF = *MBB.getParent();
287 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
288 MachineConstantPool *MCP = MF.getConstantPool();
289 unsigned CPI = Orig->getOperand(1).getIndex();
290 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
291 assert(MCPE.isMachineConstantPoolEntry() &&
292 "Expecting a machine constantpool entry!");
293 ARMConstantPoolValue *ACPV =
294 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
295 unsigned PCLabelId = AFI->createConstPoolEntryUId();
296 ARMConstantPoolValue *NewCPV = 0;
297 if (ACPV->isGlobalValue())
298 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
300 else if (ACPV->isExtSymbol())
301 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
302 ACPV->getSymbol(), PCLabelId, 4);
303 else if (ACPV->isBlockAddress())
304 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
305 ARMCP::CPBlockAddress, 4);
307 llvm_unreachable("Unexpected ARM constantpool value type!!");
308 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
309 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
311 .addConstantPoolIndex(CPI).addImm(PCLabelId);
312 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
317 MachineInstr *NewMI = prior(I);
318 NewMI->getOperand(0).setSubReg(SubIdx);