lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

   1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
  15 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
  16
  17 #include "llvm/Support/DataTypes.h"
  18 #include <string>
  19
  20 namespace llvm {
  21 class formatted_raw_ostream;
  22 class MCAsmBackend;
  23 class MCCodeEmitter;
  24 class MCContext;
  25 class MCInstrInfo;
  26 class MCInstPrinter;
  27 class MCObjectWriter;
  28 class MCRegisterInfo;
  29 class MCSubtargetInfo;
  30 class MCStreamer;
  31 class MCRelocationInfo;
  32 class MCTargetStreamer;
  33 class StringRef;
  34 class Target;
  35 class Triple;
  36 class raw_ostream;
  37
  38 extern Target TheARMLETarget, TheThumbLETarget;
  39 extern Target TheARMBETarget, TheThumbBETarget;
  40
  41 namespace ARM_MC {
  42   std::string ParseARMTriple(StringRef TT, StringRef CPU);
  43
  44   /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
  45   /// This is exposed so Asm parser, etc. do not need to go through
  46   /// TargetRegistry.
  47   MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
  48                                             StringRef FS);
  49 }
  50
  51 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
  52 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
  53                                              formatted_raw_ostream &OS,
  54                                              MCInstPrinter *InstPrint,
  55                                              bool isVerboseAsm);
  56 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
  57                                                 const MCSubtargetInfo &STI);
  58
  59 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
  60                                         const MCRegisterInfo &MRI,
  61                                         MCContext &Ctx);
  62
  63 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
  64                                         const MCRegisterInfo &MRI,
  65                                         MCContext &Ctx);
  66
  67 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  68                                   StringRef TT, StringRef CPU,
  69                                   bool IsLittleEndian);
  70
  71 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  72                                   StringRef TT, StringRef CPU);
  73
  74 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  75                                   StringRef TT, StringRef CPU);
  76
  77 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  78                                       StringRef TT, StringRef CPU);
  79
  80 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  81                                       StringRef TT, StringRef CPU);
  82
  83 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
  84 // object file.
  85 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
  86                                      raw_ostream &OS, MCCodeEmitter *Emitter,
  87                                      bool RelaxAll);
  88
  89 /// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
  90 MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
  91                                          uint8_t OSABI,
  92                                          bool IsLittleEndian);
  93
  94 /// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
  95 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
  96                                           bool Is64Bit,
  97                                           uint32_t CPUType,
  98                                           uint32_t CPUSubtype);
  99
 100 /// createARMWinCOFFObjectWriter - Construct an ARM PE/COFF object writer.
 101 MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
 102
 103 /// createARMMachORelocationInfo - Construct ARM Mach-O relocation info.
 104 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
 105 } // End llvm namespace
 106
 107 // Defines symbolic names for ARM registers.  This defines a mapping from
 108 // register name to register number.
 109 //
 110 #define GET_REGINFO_ENUM
 111 #include "ARMGenRegisterInfo.inc"
 112
 113 // Defines symbolic names for the ARM instructions.
 114 //
 115 #define GET_INSTRINFO_ENUM
 116 #include "ARMGenInstrInfo.inc"
 117
 118 #define GET_SUBTARGETINFO_ENUM
 119 #include "ARMGenSubtargetInfo.inc"
 120
 121 #endif