lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

   1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMMCTARGETDESC_H
  15 #define ARMMCTARGETDESC_H
  16
  17 #include "llvm/Support/DataTypes.h"
  18 #include <string>
  19
  20 namespace llvm {
  21 class formatted_raw_ostream;
  22 class MCAsmBackend;
  23 class MCCodeEmitter;
  24 class MCContext;
  25 class MCInstrInfo;
  26 class MCInstPrinter;
  27 class MCObjectWriter;
  28 class MCRegisterInfo;
  29 class MCSubtargetInfo;
  30 class MCStreamer;
  31 class MCRelocationInfo;
  32 class StringRef;
  33 class Target;
  34 class raw_ostream;
  35
  36 extern Target TheARMLETarget, TheThumbLETarget;
  37 extern Target TheARMBETarget, TheThumbBETarget;
  38
  39 namespace ARM_MC {
  40   std::string ParseARMTriple(StringRef TT, StringRef CPU);
  41
  42   /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
  43   /// This is exposed so Asm parser, etc. do not need to go through
  44   /// TargetRegistry.
  45   MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
  46                                             StringRef FS);
  47 }
  48
  49 MCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
  50                                 bool isVerboseAsm, bool useDwarfDirectory,
  51                                 MCInstPrinter *InstPrint, MCCodeEmitter *CE,
  52                                 MCAsmBackend *TAB, bool ShowInst);
  53
  54 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
  55                                         const MCRegisterInfo &MRI,
  56                                         const MCSubtargetInfo &STI,
  57                                         MCContext &Ctx);
  58
  59 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
  60                                         const MCRegisterInfo &MRI,
  61                                         const MCSubtargetInfo &STI,
  62                                         MCContext &Ctx);
  63
  64 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  65                                   StringRef TT, StringRef CPU,
  66                                   bool IsLittleEndian);
  67
  68 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  69                                   StringRef TT, StringRef CPU);
  70
  71 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  72                                   StringRef TT, StringRef CPU);
  73
  74 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  75                                       StringRef TT, StringRef CPU);
  76
  77 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  78                                       StringRef TT, StringRef CPU);
  79
  80 /// createARMWinCOFFStreamer - Construct a PE/COFF machine code streamer which
  81 /// will generate a PE/COFF object file.
  82 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
  83                                      MCCodeEmitter &Emitter, raw_ostream &OS);
  84
  85 /// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
  86 MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
  87                                          uint8_t OSABI,
  88                                          bool IsLittleEndian);
  89
  90 /// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
  91 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
  92                                           bool Is64Bit,
  93                                           uint32_t CPUType,
  94                                           uint32_t CPUSubtype);
  95
  96 /// createARMWinCOFFObjectWriter - Construct an ARM PE/COFF object writer.
  97 MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
  98
  99 /// createARMMachORelocationInfo - Construct ARM Mach-O relocation info.
 100 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
 101 } // End llvm namespace
 102
 103 // Defines symbolic names for ARM registers.  This defines a mapping from
 104 // register name to register number.
 105 //
 106 #define GET_REGINFO_ENUM
 107 #include "ARMGenRegisterInfo.inc"
 108
 109 // Defines symbolic names for the ARM instructions.
 110 //
 111 #define GET_INSTRINFO_ENUM
 112 #include "ARMGenInstrInfo.inc"
 113
 114 #define GET_SUBTARGETINFO_ENUM
 115 #include "ARMGenSubtargetInfo.inc"
 116
 117 #endif