1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMMCTARGETDESC_H
15 #define ARMMCTARGETDESC_H
17 #include "llvm/Support/DataTypes.h"
21 class formatted_raw_ostream;
29 class MCSubtargetInfo;
31 class MCRelocationInfo;
36 extern Target TheARMleTarget, TheThumbleTarget;
37 extern Target TheARMbeTarget, TheThumbbeTarget;
40 std::string ParseARMTriple(StringRef TT, StringRef CPU);
42 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
43 /// This is exposed so Asm parser, etc. do not need to go through
45 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
49 MCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
50 bool isVerboseAsm, bool useCFI,
51 bool useDwarfDirectory,
52 MCInstPrinter *InstPrint, MCCodeEmitter *CE,
53 MCAsmBackend *TAB, bool ShowInst);
55 MCCodeEmitter *createARMleMCCodeEmitter(const MCInstrInfo &MCII,
56 const MCRegisterInfo &MRI,
57 const MCSubtargetInfo &STI,
60 MCCodeEmitter *createARMbeMCCodeEmitter(const MCInstrInfo &MCII,
61 const MCRegisterInfo &MRI,
62 const MCSubtargetInfo &STI,
65 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
66 StringRef TT, StringRef CPU,
69 MCAsmBackend *createARMleAsmBackend(const Target &T, const MCRegisterInfo &MRI,
70 StringRef TT, StringRef CPU);
72 MCAsmBackend *createARMbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
73 StringRef TT, StringRef CPU);
75 MCAsmBackend *createThumbleAsmBackend(const Target &T, const MCRegisterInfo &MRI,
76 StringRef TT, StringRef CPU);
78 MCAsmBackend *createThumbbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
79 StringRef TT, StringRef CPU);
81 /// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
82 MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
86 /// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
87 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
93 /// createARMMachORelocationInfo - Construct ARM Mach-O relocation info.
94 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
95 } // End llvm namespace
97 // Defines symbolic names for ARM registers. This defines a mapping from
98 // register name to register number.
100 #define GET_REGINFO_ENUM
101 #include "ARMGenRegisterInfo.inc"
103 // Defines symbolic names for the ARM instructions.
105 #define GET_INSTRINFO_ENUM
106 #include "ARMGenInstrInfo.inc"
108 #define GET_SUBTARGETINFO_ENUM
109 #include "ARMGenSubtargetInfo.inc"