lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

   1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMMCTARGETDESC_H
  15 #define ARMMCTARGETDESC_H
  16
  17 #include "llvm/Support/DataTypes.h"
  18 #include <string>
  19
  20 namespace llvm {
  21 class formatted_raw_ostream;
  22 class MCAsmBackend;
  23 class MCCodeEmitter;
  24 class MCContext;
  25 class MCInstrInfo;
  26 class MCInstPrinter;
  27 class MCObjectWriter;
  28 class MCRegisterInfo;
  29 class MCSubtargetInfo;
  30 class MCStreamer;
  31 class MCRelocationInfo;
  32 class StringRef;
  33 class Target;
  34 class raw_ostream;
  35
  36 extern Target TheARMLETarget, TheThumbLETarget;
  37 extern Target TheARMBETarget, TheThumbBETarget;
  38
  39 namespace ARM_MC {
  40   std::string ParseARMTriple(StringRef TT, StringRef CPU);
  41
  42   /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
  43   /// This is exposed so Asm parser, etc. do not need to go through
  44   /// TargetRegistry.
  45   MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
  46                                             StringRef FS);
  47 }
  48
  49 MCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
  50                                 bool isVerboseAsm, bool useCFI,
  51                                 bool useDwarfDirectory,
  52                                 MCInstPrinter *InstPrint, MCCodeEmitter *CE,
  53                                 MCAsmBackend *TAB, bool ShowInst);
  54
  55 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
  56                                         const MCRegisterInfo &MRI,
  57                                         const MCSubtargetInfo &STI,
  58                                         MCContext &Ctx);
  59
  60 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
  61                                         const MCRegisterInfo &MRI,
  62                                         const MCSubtargetInfo &STI,
  63                                         MCContext &Ctx);
  64
  65 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  66                                   StringRef TT, StringRef CPU,
  67                                   bool IsLittleEndian);
  68
  69 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  70                                   StringRef TT, StringRef CPU);
  71
  72 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  73                                   StringRef TT, StringRef CPU);
  74
  75 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  76                                       StringRef TT, StringRef CPU);
  77
  78 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  79                                       StringRef TT, StringRef CPU);
  80
  81 /// createARMWinCOFFStreamer - Construct a PE/COFF machine code streamer which
  82 /// will generate a PE/COFF object file.
  83 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
  84                                      MCCodeEmitter &Emitter, raw_ostream &OS);
  85
  86 /// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
  87 MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
  88                                          uint8_t OSABI,
  89                                          bool IsLittleEndian);
  90
  91 /// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
  92 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
  93                                           bool Is64Bit,
  94                                           uint32_t CPUType,
  95                                           uint32_t CPUSubtype);
  96
  97 /// createARMWinCOFFObjectWriter - Construct an ARM PE/COFF object writer.
  98 MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
  99
 100 /// createARMMachORelocationInfo - Construct ARM Mach-O relocation info.
 101 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
 102 } // End llvm namespace
 103
 104 // Defines symbolic names for ARM registers.  This defines a mapping from
 105 // register name to register number.
 106 //
 107 #define GET_REGINFO_ENUM
 108 #include "ARMGenRegisterInfo.inc"
 109
 110 // Defines symbolic names for the ARM instructions.
 111 //
 112 #define GET_INSTRINFO_ENUM
 113 #include "ARMGenInstrInfo.inc"
 114
 115 #define GET_SUBTARGETINFO_ENUM
 116 #include "ARMGenSubtargetInfo.inc"
 117
 118 #endif