lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

   1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMBaseInfo.h"
  15 #include "ARMMCAsmInfo.h"
  16 #include "ARMMCTargetDesc.h"
  17 #include "InstPrinter/ARMInstPrinter.h"
  18 #include "llvm/ADT/Triple.h"
  19 #include "llvm/MC/MCCodeGenInfo.h"
  20 #include "llvm/MC/MCELFStreamer.h"
  21 #include "llvm/MC/MCInstrAnalysis.h"
  22 #include "llvm/MC/MCInstrInfo.h"
  23 #include "llvm/MC/MCRegisterInfo.h"
  24 #include "llvm/MC/MCStreamer.h"
  25 #include "llvm/MC/MCSubtargetInfo.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/TargetRegistry.h"
  28
  29 using namespace llvm;
  30
  31 #define GET_REGINFO_MC_DESC
  32 #include "ARMGenRegisterInfo.inc"
  33
  34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  35                                   std::string &Info) {
  36   if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
  37       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
  38       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
  39       // Checks for the deprecated CP15ISB encoding:
  40       // mcr p15, #0, rX, c7, c5, #4
  41       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
  42     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
  43       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
  44         Info = "deprecated since v7, use 'isb'";
  45         return true;
  46       }
  47
  48       // Checks for the deprecated CP15DSB encoding:
  49       // mcr p15, #0, rX, c7, c10, #4
  50       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
  51         Info = "deprecated since v7, use 'dsb'";
  52         return true;
  53       }
  54     }
  55     // Checks for the deprecated CP15DMB encoding:
  56     // mcr p15, #0, rX, c7, c10, #5
  57     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
  58         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
  59       Info = "deprecated since v7, use 'dmb'";
  60       return true;
  61     }
  62   }
  63   return false;
  64 }
  65
  66 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  67                                  std::string &Info) {
  68   if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && MI.getOperand(1).isImm() &&
  69       MI.getOperand(1).getImm() != 8) {
  70     Info = "applying IT instruction to more than one subsequent instruction is "
  71            "deprecated";
  72     return true;
  73   }
  74
  75   return false;
  76 }
  77
  78 #define GET_INSTRINFO_MC_DESC
  79 #include "ARMGenInstrInfo.inc"
  80
  81 #define GET_SUBTARGETINFO_MC_DESC
  82 #include "ARMGenSubtargetInfo.inc"
  83
  84
  85 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
  86   Triple triple(TT);
  87
  88   bool isThumb = triple.getArch() == Triple::thumb ||
  89                  triple.getArch() == Triple::thumbeb;
  90
  91   bool NoCPU = CPU == "generic" || CPU.empty();
  92   std::string ARMArchFeature;
  93   switch (triple.getSubArch()) {
  94   default:
  95     llvm_unreachable("invalid sub-architecture for ARM");
  96   case Triple::ARMSubArch_v8:
  97     if (NoCPU)
  98       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
  99       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
 100       //      FeatureT2XtPk, FeatureCrypto, FeatureCRC
 101       ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
 102                        "+trustzone,+t2xtpk,+crypto,+crc";
 103     else
 104       // Use CPU to figure out the exact features
 105       ARMArchFeature = "+v8";
 106     break;
 107   case Triple::ARMSubArch_v7m:
 108     isThumb = true;
 109     if (NoCPU)
 110       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
 111       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
 112     else
 113       // Use CPU to figure out the exact features.
 114       ARMArchFeature = "+v7";
 115     break;
 116   case Triple::ARMSubArch_v7em:
 117     if (NoCPU)
 118       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
 119       //       FeatureT2XtPk, FeatureMClass
 120       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
 121     else
 122       // Use CPU to figure out the exact features.
 123       ARMArchFeature = "+v7";
 124     break;
 125   case Triple::ARMSubArch_v7s:
 126     if (NoCPU)
 127       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
 128       //      Swift
 129       ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
 130     else
 131       // Use CPU to figure out the exact features.
 132       ARMArchFeature = "+v7";
 133     break;
 134   case Triple::ARMSubArch_v7:
 135     // v7 CPUs have lots of different feature sets. If no CPU is specified,
 136     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
 137     // the "minimum" feature set and use CPU string to figure out the exact
 138     // features.
 139     if (NoCPU)
 140       // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
 141       ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
 142     else
 143       // Use CPU to figure out the exact features.
 144       ARMArchFeature = "+v7";
 145     break;
 146   case Triple::ARMSubArch_v6t2:
 147     ARMArchFeature = "+v6t2";
 148     break;
 149   case Triple::ARMSubArch_v6m:
 150     isThumb = true;
 151     if (NoCPU)
 152       // v6m: FeatureNoARM, FeatureMClass
 153       ARMArchFeature = "+v6m,+noarm,+mclass";
 154     else
 155       ARMArchFeature = "+v6";
 156     break;
 157   case Triple::ARMSubArch_v6:
 158     ARMArchFeature = "+v6";
 159     break;
 160   case Triple::ARMSubArch_v5te:
 161     ARMArchFeature = "+v5te";
 162     break;
 163   case Triple::ARMSubArch_v5:
 164     ARMArchFeature = "+v5t";
 165     break;
 166   case Triple::ARMSubArch_v4t:
 167     ARMArchFeature = "+v4t";
 168     break;
 169   case Triple::NoSubArch:
 170     break;
 171   }
 172
 173   if (isThumb) {
 174     if (ARMArchFeature.empty())
 175       ARMArchFeature = "+thumb-mode";
 176     else
 177       ARMArchFeature += ",+thumb-mode";
 178   }
 179
 180   if (triple.isOSNaCl()) {
 181     if (ARMArchFeature.empty())
 182       ARMArchFeature = "+nacl-trap";
 183     else
 184       ARMArchFeature += ",+nacl-trap";
 185   }
 186
 187   return ARMArchFeature;
 188 }
 189
 190 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
 191                                                   StringRef FS) {
 192   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
 193   if (!FS.empty()) {
 194     if (!ArchFS.empty())
 195       ArchFS = ArchFS + "," + FS.str();
 196     else
 197       ArchFS = FS;
 198   }
 199
 200   MCSubtargetInfo *X = new MCSubtargetInfo();
 201   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
 202   return X;
 203 }
 204
 205 static MCInstrInfo *createARMMCInstrInfo() {
 206   MCInstrInfo *X = new MCInstrInfo();
 207   InitARMMCInstrInfo(X);
 208   return X;
 209 }
 210
 211 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
 212   MCRegisterInfo *X = new MCRegisterInfo();
 213   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
 214   return X;
 215 }
 216
 217 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
 218   Triple TheTriple(TT);
 219
 220   MCAsmInfo *MAI;
 221   if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
 222     MAI = new ARMMCAsmInfoDarwin(TT);
 223   else if (TheTriple.isWindowsItaniumEnvironment())
 224     MAI = new ARMCOFFMCAsmInfoGNU();
 225   else if (TheTriple.isWindowsMSVCEnvironment())
 226     MAI = new ARMCOFFMCAsmInfoMicrosoft();
 227   else
 228     MAI = new ARMELFMCAsmInfo(TT);
 229
 230   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
 231   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
 232
 233   return MAI;
 234 }
 235
 236 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
 237                                              CodeModel::Model CM,
 238                                              CodeGenOpt::Level OL) {
 239   MCCodeGenInfo *X = new MCCodeGenInfo();
 240   if (RM == Reloc::Default) {
 241     Triple TheTriple(TT);
 242     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
 243     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
 244   }
 245   X->InitMCCodeGenInfo(RM, CM, OL);
 246   return X;
 247 }
 248
 249 // This is duplicated code. Refactor this.
 250 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
 251                                     MCContext &Ctx, MCAsmBackend &MAB,
 252                                     raw_ostream &OS, MCCodeEmitter *Emitter,
 253                                     const MCSubtargetInfo &STI, bool RelaxAll) {
 254   Triple TheTriple(TT);
 255
 256   switch (TheTriple.getObjectFormat()) {
 257   default: llvm_unreachable("unsupported object format");
 258   case Triple::MachO: {
 259     MCStreamer *S = createMachOStreamer(Ctx, MAB, OS, Emitter, false);
 260     new ARMTargetStreamer(*S);
 261     return S;
 262   }
 263   case Triple::COFF:
 264     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
 265     return createARMWinCOFFStreamer(Ctx, MAB, *Emitter, OS);
 266   case Triple::ELF:
 267     return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
 268                                 TheTriple.getArch() == Triple::thumb);
 269   }
 270 }
 271
 272 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
 273                                              unsigned SyntaxVariant,
 274                                              const MCAsmInfo &MAI,
 275                                              const MCInstrInfo &MII,
 276                                              const MCRegisterInfo &MRI,
 277                                              const MCSubtargetInfo &STI) {
 278   if (SyntaxVariant == 0)
 279     return new ARMInstPrinter(MAI, MII, MRI, STI);
 280   return nullptr;
 281 }
 282
 283 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
 284                                                    MCContext &Ctx) {
 285   Triple TheTriple(TT);
 286   if (TheTriple.isOSBinFormatMachO())
 287     return createARMMachORelocationInfo(Ctx);
 288   // Default to the stock relocation info.
 289   return llvm::createMCRelocationInfo(TT, Ctx);
 290 }
 291
 292 namespace {
 293
 294 class ARMMCInstrAnalysis : public MCInstrAnalysis {
 295 public:
 296   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 297
 298   bool isUnconditionalBranch(const MCInst &Inst) const override {
 299     // BCCs with the "always" predicate are unconditional branches.
 300     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 301       return true;
 302     return MCInstrAnalysis::isUnconditionalBranch(Inst);
 303   }
 304
 305   bool isConditionalBranch(const MCInst &Inst) const override {
 306     // BCCs with the "always" predicate are unconditional branches.
 307     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 308       return false;
 309     return MCInstrAnalysis::isConditionalBranch(Inst);
 310   }
 311
 312   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
 313                       uint64_t Size, uint64_t &Target) const override {
 314     // We only handle PCRel branches for now.
 315     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
 316       return false;
 317
 318     int64_t Imm = Inst.getOperand(0).getImm();
 319     // FIXME: This is not right for thumb.
 320     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
 321     return true;
 322   }
 323 };
 324
 325 }
 326
 327 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
 328   return new ARMMCInstrAnalysis(Info);
 329 }
 330
 331 // Force static initialization.
 332 extern "C" void LLVMInitializeARMTargetMC() {
 333   // Register the MC asm info.
 334   RegisterMCAsmInfoFn X(TheARMLETarget, createARMMCAsmInfo);
 335   RegisterMCAsmInfoFn Y(TheARMBETarget, createARMMCAsmInfo);
 336   RegisterMCAsmInfoFn A(TheThumbLETarget, createARMMCAsmInfo);
 337   RegisterMCAsmInfoFn B(TheThumbBETarget, createARMMCAsmInfo);
 338
 339   // Register the MC codegen info.
 340   TargetRegistry::RegisterMCCodeGenInfo(TheARMLETarget, createARMMCCodeGenInfo);
 341   TargetRegistry::RegisterMCCodeGenInfo(TheARMBETarget, createARMMCCodeGenInfo);
 342   TargetRegistry::RegisterMCCodeGenInfo(TheThumbLETarget,
 343                                         createARMMCCodeGenInfo);
 344   TargetRegistry::RegisterMCCodeGenInfo(TheThumbBETarget,
 345                                         createARMMCCodeGenInfo);
 346
 347   // Register the MC instruction info.
 348   TargetRegistry::RegisterMCInstrInfo(TheARMLETarget, createARMMCInstrInfo);
 349   TargetRegistry::RegisterMCInstrInfo(TheARMBETarget, createARMMCInstrInfo);
 350   TargetRegistry::RegisterMCInstrInfo(TheThumbLETarget, createARMMCInstrInfo);
 351   TargetRegistry::RegisterMCInstrInfo(TheThumbBETarget, createARMMCInstrInfo);
 352
 353   // Register the MC register info.
 354   TargetRegistry::RegisterMCRegInfo(TheARMLETarget, createARMMCRegisterInfo);
 355   TargetRegistry::RegisterMCRegInfo(TheARMBETarget, createARMMCRegisterInfo);
 356   TargetRegistry::RegisterMCRegInfo(TheThumbLETarget, createARMMCRegisterInfo);
 357   TargetRegistry::RegisterMCRegInfo(TheThumbBETarget, createARMMCRegisterInfo);
 358
 359   // Register the MC subtarget info.
 360   TargetRegistry::RegisterMCSubtargetInfo(TheARMLETarget,
 361                                           ARM_MC::createARMMCSubtargetInfo);
 362   TargetRegistry::RegisterMCSubtargetInfo(TheARMBETarget,
 363                                           ARM_MC::createARMMCSubtargetInfo);
 364   TargetRegistry::RegisterMCSubtargetInfo(TheThumbLETarget,
 365                                           ARM_MC::createARMMCSubtargetInfo);
 366   TargetRegistry::RegisterMCSubtargetInfo(TheThumbBETarget,
 367                                           ARM_MC::createARMMCSubtargetInfo);
 368
 369   // Register the MC instruction analyzer.
 370   TargetRegistry::RegisterMCInstrAnalysis(TheARMLETarget,
 371                                           createARMMCInstrAnalysis);
 372   TargetRegistry::RegisterMCInstrAnalysis(TheARMBETarget,
 373                                           createARMMCInstrAnalysis);
 374   TargetRegistry::RegisterMCInstrAnalysis(TheThumbLETarget,
 375                                           createARMMCInstrAnalysis);
 376   TargetRegistry::RegisterMCInstrAnalysis(TheThumbBETarget,
 377                                           createARMMCInstrAnalysis);
 378
 379   // Register the MC Code Emitter
 380   TargetRegistry::RegisterMCCodeEmitter(TheARMLETarget,
 381                                         createARMLEMCCodeEmitter);
 382   TargetRegistry::RegisterMCCodeEmitter(TheARMBETarget,
 383                                         createARMBEMCCodeEmitter);
 384   TargetRegistry::RegisterMCCodeEmitter(TheThumbLETarget,
 385                                         createARMLEMCCodeEmitter);
 386   TargetRegistry::RegisterMCCodeEmitter(TheThumbBETarget,
 387                                         createARMBEMCCodeEmitter);
 388
 389   // Register the asm backend.
 390   TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
 391   TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
 392   TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
 393                                        createThumbLEAsmBackend);
 394   TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
 395                                        createThumbBEAsmBackend);
 396
 397   // Register the object streamer.
 398   TargetRegistry::RegisterMCObjectStreamer(TheARMLETarget, createMCStreamer);
 399   TargetRegistry::RegisterMCObjectStreamer(TheARMBETarget, createMCStreamer);
 400   TargetRegistry::RegisterMCObjectStreamer(TheThumbLETarget, createMCStreamer);
 401   TargetRegistry::RegisterMCObjectStreamer(TheThumbBETarget, createMCStreamer);
 402
 403   // Register the asm streamer.
 404   TargetRegistry::RegisterAsmStreamer(TheARMLETarget, createMCAsmStreamer);
 405   TargetRegistry::RegisterAsmStreamer(TheARMBETarget, createMCAsmStreamer);
 406   TargetRegistry::RegisterAsmStreamer(TheThumbLETarget, createMCAsmStreamer);
 407   TargetRegistry::RegisterAsmStreamer(TheThumbBETarget, createMCAsmStreamer);
 408
 409   // Register the null streamer.
 410   TargetRegistry::RegisterNullStreamer(TheARMLETarget, createARMNullStreamer);
 411   TargetRegistry::RegisterNullStreamer(TheARMBETarget, createARMNullStreamer);
 412   TargetRegistry::RegisterNullStreamer(TheThumbLETarget, createARMNullStreamer);
 413   TargetRegistry::RegisterNullStreamer(TheThumbBETarget, createARMNullStreamer);
 414
 415   // Register the MCInstPrinter.
 416   TargetRegistry::RegisterMCInstPrinter(TheARMLETarget, createARMMCInstPrinter);
 417   TargetRegistry::RegisterMCInstPrinter(TheARMBETarget, createARMMCInstPrinter);
 418   TargetRegistry::RegisterMCInstPrinter(TheThumbLETarget,
 419                                         createARMMCInstPrinter);
 420   TargetRegistry::RegisterMCInstPrinter(TheThumbBETarget,
 421                                         createARMMCInstPrinter);
 422
 423   // Register the MC relocation info.
 424   TargetRegistry::RegisterMCRelocationInfo(TheARMLETarget,
 425                                            createARMMCRelocationInfo);
 426   TargetRegistry::RegisterMCRelocationInfo(TheARMBETarget,
 427                                            createARMMCRelocationInfo);
 428   TargetRegistry::RegisterMCRelocationInfo(TheThumbLETarget,
 429                                            createARMMCRelocationInfo);
 430   TargetRegistry::RegisterMCRelocationInfo(TheThumbBETarget,
 431                                            createARMMCRelocationInfo);
 432 }