1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/ARMMCTargetDesc.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
33 #define DEBUG_TYPE "mccodeemitter"
35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
36 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
39 class ARMMCCodeEmitter : public MCCodeEmitter {
40 ARMMCCodeEmitter(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
41 void operator=(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
42 const MCInstrInfo &MCII;
47 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
48 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
51 ~ARMMCCodeEmitter() {}
53 bool isThumb(const MCSubtargetInfo &STI) const {
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
56 bool isThumb2(const MCSubtargetInfo &STI) const {
57 return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
59 bool isTargetMachO(const MCSubtargetInfo &STI) const {
60 Triple TT(STI.getTargetTriple());
61 return TT.isOSBinFormatMachO();
64 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
66 // getBinaryCodeForInstr - TableGen'erated function for getting the
67 // binary encoding for an instruction.
68 uint64_t getBinaryCodeForInstr(const MCInst &MI,
69 SmallVectorImpl<MCFixup> &Fixups,
70 const MCSubtargetInfo &STI) const;
72 /// getMachineOpValue - Return binary encoding of operand. If the machine
73 /// operand requires relocation, record the relocation and return zero.
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &STI) const;
78 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
79 /// the specified operand. This is used for operands with :lower16: and
80 /// :upper16: prefixes.
81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
82 SmallVectorImpl<MCFixup> &Fixups,
83 const MCSubtargetInfo &STI) const;
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
86 unsigned &Reg, unsigned &Imm,
87 SmallVectorImpl<MCFixup> &Fixups,
88 const MCSubtargetInfo &STI) const;
90 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups,
94 const MCSubtargetInfo &STI) const;
96 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
97 /// BLX branch target.
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
99 SmallVectorImpl<MCFixup> &Fixups,
100 const MCSubtargetInfo &STI) const;
102 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 SmallVectorImpl<MCFixup> &Fixups,
105 const MCSubtargetInfo &STI) const;
107 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 SmallVectorImpl<MCFixup> &Fixups,
110 const MCSubtargetInfo &STI) const;
112 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
114 SmallVectorImpl<MCFixup> &Fixups,
115 const MCSubtargetInfo &STI) const;
117 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups,
121 const MCSubtargetInfo &STI) const;
123 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
124 /// immediate Thumb2 direct branch target.
125 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
126 SmallVectorImpl<MCFixup> &Fixups,
127 const MCSubtargetInfo &STI) const;
129 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132 SmallVectorImpl<MCFixup> &Fixups,
133 const MCSubtargetInfo &STI) const;
134 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups,
136 const MCSubtargetInfo &STI) const;
137 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
138 SmallVectorImpl<MCFixup> &Fixups,
139 const MCSubtargetInfo &STI) const;
141 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
142 /// ADR label target.
143 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI) const;
146 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups,
148 const MCSubtargetInfo &STI) const;
149 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups,
151 const MCSubtargetInfo &STI) const;
154 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
156 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
157 SmallVectorImpl<MCFixup> &Fixups,
158 const MCSubtargetInfo &STI) const;
160 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
161 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
162 SmallVectorImpl<MCFixup> &Fixups,
163 const MCSubtargetInfo &STI) const;
165 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
167 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
168 SmallVectorImpl<MCFixup> &Fixups,
169 const MCSubtargetInfo &STI) const;
171 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
173 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
174 SmallVectorImpl<MCFixup> &Fixups,
175 const MCSubtargetInfo &STI) const;
177 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
179 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
180 SmallVectorImpl<MCFixup> &Fixups,
181 const MCSubtargetInfo &STI) const;
184 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
185 /// operand as needed by load/store instructions.
186 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
187 SmallVectorImpl<MCFixup> &Fixups,
188 const MCSubtargetInfo &STI) const;
190 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
191 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
192 SmallVectorImpl<MCFixup> &Fixups,
193 const MCSubtargetInfo &STI) const {
194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
196 default: llvm_unreachable("Unknown addressing sub-mode!");
197 case ARM_AM::da: return 0;
198 case ARM_AM::ia: return 1;
199 case ARM_AM::db: return 2;
200 case ARM_AM::ib: return 3;
203 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
207 case ARM_AM::no_shift:
208 case ARM_AM::lsl: return 0;
209 case ARM_AM::lsr: return 1;
210 case ARM_AM::asr: return 2;
212 case ARM_AM::rrx: return 3;
214 llvm_unreachable("Invalid ShiftOpc!");
217 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
218 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
219 SmallVectorImpl<MCFixup> &Fixups,
220 const MCSubtargetInfo &STI) const;
222 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
223 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
224 SmallVectorImpl<MCFixup> &Fixups,
225 const MCSubtargetInfo &STI) const;
227 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
228 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
229 SmallVectorImpl<MCFixup> &Fixups,
230 const MCSubtargetInfo &STI) const;
232 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
233 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
234 SmallVectorImpl<MCFixup> &Fixups,
235 const MCSubtargetInfo &STI) const;
237 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
238 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
239 SmallVectorImpl<MCFixup> &Fixups,
240 const MCSubtargetInfo &STI) const;
242 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
244 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
245 SmallVectorImpl<MCFixup> &Fixups,
246 const MCSubtargetInfo &STI) const;
248 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
249 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
250 SmallVectorImpl<MCFixup> &Fixups,
251 const MCSubtargetInfo &STI) const;
253 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
254 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
255 SmallVectorImpl<MCFixup> &Fixups,
256 const MCSubtargetInfo &STI) const;
258 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
259 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
260 SmallVectorImpl<MCFixup> &Fixups,
261 const MCSubtargetInfo &STI) const;
263 /// getCCOutOpValue - Return encoding of the 's' bit.
264 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
265 SmallVectorImpl<MCFixup> &Fixups,
266 const MCSubtargetInfo &STI) const {
267 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
269 return MI.getOperand(Op).getReg() == ARM::CPSR;
272 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
273 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
274 SmallVectorImpl<MCFixup> &Fixups,
275 const MCSubtargetInfo &STI) const {
277 const MCOperand &MO = MI.getOperand(Op);
279 // We expect MO to be an immediate or an expression,
280 // if it is an immediate - that's fine, just encode the value.
281 // Otherwise - create a Fixup.
283 const MCExpr *Expr = MO.getExpr();
284 // In instruction code this value always encoded as lowest 12 bits,
285 // so we don't have to perform any specific adjustments.
286 // Due to requirements of relocatable records we have to use FK_Data_4.
287 // See ARMELFObjectWriter::ExplicitRelSym and
288 // ARMELFObjectWriter::GetRelocTypeInner for more details.
289 MCFixupKind Kind = MCFixupKind(FK_Data_4);
290 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
294 unsigned SoImm = MO.getImm();
295 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
296 assert(SoImmVal != -1 && "Not a valid so_imm value!");
298 // Encode rotate_imm.
299 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
300 << ARMII::SoRotImmShift;
303 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
307 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
308 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
309 SmallVectorImpl<MCFixup> &Fixups,
310 const MCSubtargetInfo &STI) const {
311 unsigned SoImm = MI.getOperand(Op).getImm();
312 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
313 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
317 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
318 SmallVectorImpl<MCFixup> &Fixups,
319 const MCSubtargetInfo &STI) const;
320 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
321 SmallVectorImpl<MCFixup> &Fixups,
322 const MCSubtargetInfo &STI) const;
323 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
324 SmallVectorImpl<MCFixup> &Fixups,
325 const MCSubtargetInfo &STI) const;
326 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
327 SmallVectorImpl<MCFixup> &Fixups,
328 const MCSubtargetInfo &STI) const;
330 /// getSORegOpValue - Return an encoded so_reg shifted register value.
331 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
332 SmallVectorImpl<MCFixup> &Fixups,
333 const MCSubtargetInfo &STI) const;
334 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
335 SmallVectorImpl<MCFixup> &Fixups,
336 const MCSubtargetInfo &STI) const;
337 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
338 SmallVectorImpl<MCFixup> &Fixups,
339 const MCSubtargetInfo &STI) const;
341 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
342 SmallVectorImpl<MCFixup> &Fixups,
343 const MCSubtargetInfo &STI) const {
344 return 64 - MI.getOperand(Op).getImm();
347 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
348 SmallVectorImpl<MCFixup> &Fixups,
349 const MCSubtargetInfo &STI) const;
351 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
352 SmallVectorImpl<MCFixup> &Fixups,
353 const MCSubtargetInfo &STI) const;
354 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
355 SmallVectorImpl<MCFixup> &Fixups,
356 const MCSubtargetInfo &STI) const;
357 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
358 SmallVectorImpl<MCFixup> &Fixups,
359 const MCSubtargetInfo &STI) const;
360 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
361 SmallVectorImpl<MCFixup> &Fixups,
362 const MCSubtargetInfo &STI) const;
363 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
364 SmallVectorImpl<MCFixup> &Fixups,
365 const MCSubtargetInfo &STI) const;
367 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
368 SmallVectorImpl<MCFixup> &Fixups,
369 const MCSubtargetInfo &STI) const;
370 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
371 SmallVectorImpl<MCFixup> &Fixups,
372 const MCSubtargetInfo &STI) const;
373 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
374 SmallVectorImpl<MCFixup> &Fixups,
375 const MCSubtargetInfo &STI) const;
376 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
377 SmallVectorImpl<MCFixup> &Fixups,
378 const MCSubtargetInfo &STI) const;
380 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
381 SmallVectorImpl<MCFixup> &Fixups,
382 const MCSubtargetInfo &STI) const;
384 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
385 unsigned EncodedValue,
386 const MCSubtargetInfo &STI) const;
387 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
388 unsigned EncodedValue,
389 const MCSubtargetInfo &STI) const;
390 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
391 unsigned EncodedValue,
392 const MCSubtargetInfo &STI) const;
393 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
394 unsigned EncodedValue,
395 const MCSubtargetInfo &STI) const;
397 unsigned VFPThumb2PostEncoder(const MCInst &MI,
398 unsigned EncodedValue,
399 const MCSubtargetInfo &STI) const;
401 void EmitByte(unsigned char C, raw_ostream &OS) const {
405 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
406 // Output the constant in little endian byte order.
407 for (unsigned i = 0; i != Size; ++i) {
408 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
409 EmitByte((Val >> Shift) & 0xff, OS);
413 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
414 SmallVectorImpl<MCFixup> &Fixups,
415 const MCSubtargetInfo &STI) const override;
418 } // end anonymous namespace
420 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
421 const MCRegisterInfo &MRI,
422 const MCSubtargetInfo &STI,
424 return new ARMMCCodeEmitter(MCII, Ctx, true);
427 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
428 const MCRegisterInfo &MRI,
429 const MCSubtargetInfo &STI,
431 return new ARMMCCodeEmitter(MCII, Ctx, false);
434 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
435 /// instructions, and rewrite them to their Thumb2 form if we are currently in
437 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
438 unsigned EncodedValue,
439 const MCSubtargetInfo &STI) const {
441 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
442 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
444 unsigned Bit24 = EncodedValue & 0x01000000;
445 unsigned Bit28 = Bit24 << 4;
446 EncodedValue &= 0xEFFFFFFF;
447 EncodedValue |= Bit28;
448 EncodedValue |= 0x0F000000;
454 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
455 /// instructions, and rewrite them to their Thumb2 form if we are currently in
457 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
458 unsigned EncodedValue,
459 const MCSubtargetInfo &STI) const {
461 EncodedValue &= 0xF0FFFFFF;
462 EncodedValue |= 0x09000000;
468 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
469 /// instructions, and rewrite them to their Thumb2 form if we are currently in
471 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
472 unsigned EncodedValue,
473 const MCSubtargetInfo &STI) const {
475 EncodedValue &= 0x00FFFFFF;
476 EncodedValue |= 0xEE000000;
482 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
483 /// if we are in Thumb2.
484 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
485 unsigned EncodedValue,
486 const MCSubtargetInfo &STI) const {
488 EncodedValue |= 0xC000000; // Set bits 27-26
494 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
495 /// them to their Thumb2 form if we are currently in Thumb2 mode.
496 unsigned ARMMCCodeEmitter::
497 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
498 const MCSubtargetInfo &STI) const {
500 EncodedValue &= 0x0FFFFFFF;
501 EncodedValue |= 0xE0000000;
506 /// getMachineOpValue - Return binary encoding of operand. If the machine
507 /// operand requires relocation, record the relocation and return zero.
508 unsigned ARMMCCodeEmitter::
509 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
510 SmallVectorImpl<MCFixup> &Fixups,
511 const MCSubtargetInfo &STI) const {
513 unsigned Reg = MO.getReg();
514 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
516 // Q registers are encoded as 2x their register number.
520 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
521 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
522 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
523 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
526 } else if (MO.isImm()) {
527 return static_cast<unsigned>(MO.getImm());
528 } else if (MO.isFPImm()) {
529 return static_cast<unsigned>(APFloat(MO.getFPImm())
530 .bitcastToAPInt().getHiBits(32).getLimitedValue());
533 llvm_unreachable("Unable to encode MCOperand!");
536 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
537 bool ARMMCCodeEmitter::
538 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
539 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
540 const MCSubtargetInfo &STI) const {
541 const MCOperand &MO = MI.getOperand(OpIdx);
542 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
544 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
546 int32_t SImm = MO1.getImm();
549 // Special value for #-0
550 if (SImm == INT32_MIN) {
555 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
565 /// getBranchTargetOpValue - Helper function to get the branch target operand,
566 /// which is either an immediate or requires a fixup.
567 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
569 SmallVectorImpl<MCFixup> &Fixups,
570 const MCSubtargetInfo &STI) {
571 const MCOperand &MO = MI.getOperand(OpIdx);
573 // If the destination is an immediate, we have nothing to do.
574 if (MO.isImm()) return MO.getImm();
575 assert(MO.isExpr() && "Unexpected branch target type!");
576 const MCExpr *Expr = MO.getExpr();
577 MCFixupKind Kind = MCFixupKind(FixupKind);
578 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
580 // All of the information is in the fixup.
584 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
585 // determined by negating them and XOR'ing them with bit 23.
586 static int32_t encodeThumbBLOffset(int32_t offset) {
588 uint32_t S = (offset & 0x800000) >> 23;
589 uint32_t J1 = (offset & 0x400000) >> 22;
590 uint32_t J2 = (offset & 0x200000) >> 21;
603 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
604 uint32_t ARMMCCodeEmitter::
605 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
606 SmallVectorImpl<MCFixup> &Fixups,
607 const MCSubtargetInfo &STI) const {
608 const MCOperand MO = MI.getOperand(OpIdx);
610 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
612 return encodeThumbBLOffset(MO.getImm());
615 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
616 /// BLX branch target.
617 uint32_t ARMMCCodeEmitter::
618 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
619 SmallVectorImpl<MCFixup> &Fixups,
620 const MCSubtargetInfo &STI) const {
621 const MCOperand MO = MI.getOperand(OpIdx);
623 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
625 return encodeThumbBLOffset(MO.getImm());
628 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
629 uint32_t ARMMCCodeEmitter::
630 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
631 SmallVectorImpl<MCFixup> &Fixups,
632 const MCSubtargetInfo &STI) const {
633 const MCOperand MO = MI.getOperand(OpIdx);
635 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
637 return (MO.getImm() >> 1);
640 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
641 uint32_t ARMMCCodeEmitter::
642 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
643 SmallVectorImpl<MCFixup> &Fixups,
644 const MCSubtargetInfo &STI) const {
645 const MCOperand MO = MI.getOperand(OpIdx);
647 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
649 return (MO.getImm() >> 1);
652 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
653 uint32_t ARMMCCodeEmitter::
654 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
655 SmallVectorImpl<MCFixup> &Fixups,
656 const MCSubtargetInfo &STI) const {
657 const MCOperand MO = MI.getOperand(OpIdx);
659 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
660 return (MO.getImm() >> 1);
663 /// Return true if this branch has a non-always predication
664 static bool HasConditionalBranch(const MCInst &MI) {
665 int NumOp = MI.getNumOperands();
667 for (int i = 0; i < NumOp-1; ++i) {
668 const MCOperand &MCOp1 = MI.getOperand(i);
669 const MCOperand &MCOp2 = MI.getOperand(i + 1);
670 if (MCOp1.isImm() && MCOp2.isReg() &&
671 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
672 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
680 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
682 uint32_t ARMMCCodeEmitter::
683 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
684 SmallVectorImpl<MCFixup> &Fixups,
685 const MCSubtargetInfo &STI) const {
686 // FIXME: This really, really shouldn't use TargetMachine. We don't want
687 // coupling between MC and TM anywhere we can help it.
690 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
691 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
694 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
696 uint32_t ARMMCCodeEmitter::
697 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
698 SmallVectorImpl<MCFixup> &Fixups,
699 const MCSubtargetInfo &STI) const {
700 const MCOperand MO = MI.getOperand(OpIdx);
702 if (HasConditionalBranch(MI))
703 return ::getBranchTargetOpValue(MI, OpIdx,
704 ARM::fixup_arm_condbranch, Fixups, STI);
705 return ::getBranchTargetOpValue(MI, OpIdx,
706 ARM::fixup_arm_uncondbranch, Fixups, STI);
709 return MO.getImm() >> 2;
712 uint32_t ARMMCCodeEmitter::
713 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
714 SmallVectorImpl<MCFixup> &Fixups,
715 const MCSubtargetInfo &STI) const {
716 const MCOperand MO = MI.getOperand(OpIdx);
718 if (HasConditionalBranch(MI))
719 return ::getBranchTargetOpValue(MI, OpIdx,
720 ARM::fixup_arm_condbl, Fixups, STI);
721 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
724 return MO.getImm() >> 2;
727 uint32_t ARMMCCodeEmitter::
728 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
729 SmallVectorImpl<MCFixup> &Fixups,
730 const MCSubtargetInfo &STI) const {
731 const MCOperand MO = MI.getOperand(OpIdx);
733 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
735 return MO.getImm() >> 1;
738 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
739 /// immediate branch target.
740 uint32_t ARMMCCodeEmitter::
741 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
742 SmallVectorImpl<MCFixup> &Fixups,
743 const MCSubtargetInfo &STI) const {
745 const MCOperand MO = MI.getOperand(OpIdx);
748 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
750 Val = MO.getImm() >> 1;
752 bool I = (Val & 0x800000);
753 bool J1 = (Val & 0x400000);
754 bool J2 = (Val & 0x200000);
768 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
769 /// ADR label target.
770 uint32_t ARMMCCodeEmitter::
771 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
772 SmallVectorImpl<MCFixup> &Fixups,
773 const MCSubtargetInfo &STI) const {
774 const MCOperand MO = MI.getOperand(OpIdx);
776 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
778 int64_t offset = MO.getImm();
779 uint32_t Val = 0x2000;
782 if (offset == INT32_MIN) {
785 } else if (offset < 0) {
788 SoImmVal = ARM_AM::getSOImmVal(offset);
792 SoImmVal = ARM_AM::getSOImmVal(offset);
795 SoImmVal = ARM_AM::getSOImmVal(offset);
799 SoImmVal = ARM_AM::getSOImmVal(offset);
803 assert(SoImmVal != -1 && "Not a valid so_imm value!");
809 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
811 uint32_t ARMMCCodeEmitter::
812 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
813 SmallVectorImpl<MCFixup> &Fixups,
814 const MCSubtargetInfo &STI) const {
815 const MCOperand MO = MI.getOperand(OpIdx);
817 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
819 int32_t Val = MO.getImm();
820 if (Val == INT32_MIN)
829 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
831 uint32_t ARMMCCodeEmitter::
832 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
833 SmallVectorImpl<MCFixup> &Fixups,
834 const MCSubtargetInfo &STI) const {
835 const MCOperand MO = MI.getOperand(OpIdx);
837 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
842 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
844 uint32_t ARMMCCodeEmitter::
845 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
846 SmallVectorImpl<MCFixup> &,
847 const MCSubtargetInfo &STI) const {
851 const MCOperand &MO1 = MI.getOperand(OpIdx);
852 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
853 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
854 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
855 return (Rm << 3) | Rn;
858 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
859 uint32_t ARMMCCodeEmitter::
860 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
861 SmallVectorImpl<MCFixup> &Fixups,
862 const MCSubtargetInfo &STI) const {
864 // {12} = (U)nsigned (add == '1', sub == '0')
868 // If The first operand isn't a register, we have a label reference.
869 const MCOperand &MO = MI.getOperand(OpIdx);
871 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
875 const MCExpr *Expr = MO.getExpr();
876 isAdd = false ; // 'U' bit is set as part of the fixup.
880 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
882 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
883 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
885 ++MCNumCPRelocations;
888 int32_t Offset = MO.getImm();
889 if (Offset == INT32_MIN) {
892 } else if (Offset < 0) {
899 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
901 uint32_t Binary = Imm12 & 0xfff;
902 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
905 Binary |= (Reg << 13);
909 /// getT2Imm8s4OpValue - Return encoding info for
910 /// '+/- imm8<<2' operand.
911 uint32_t ARMMCCodeEmitter::
912 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
913 SmallVectorImpl<MCFixup> &Fixups,
914 const MCSubtargetInfo &STI) const {
915 // FIXME: The immediate operand should have already been encoded like this
916 // before ever getting here. The encoder method should just need to combine
917 // the MI operands for the register and the offset into a single
918 // representation for the complex operand in the .td file. This isn't just
919 // style, unfortunately. As-is, we can't represent the distinct encoding
922 // {8} = (U)nsigned (add == '1', sub == '0')
924 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
925 bool isAdd = Imm8 >= 0;
927 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
929 Imm8 = -(uint32_t)Imm8;
934 uint32_t Binary = Imm8 & 0xff;
935 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
941 /// getT2AddrModeImm8s4OpValue - Return encoding info for
942 /// 'reg +/- imm8<<2' operand.
943 uint32_t ARMMCCodeEmitter::
944 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
945 SmallVectorImpl<MCFixup> &Fixups,
946 const MCSubtargetInfo &STI) const {
948 // {8} = (U)nsigned (add == '1', sub == '0')
952 // If The first operand isn't a register, we have a label reference.
953 const MCOperand &MO = MI.getOperand(OpIdx);
955 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
957 isAdd = false ; // 'U' bit is set as part of the fixup.
959 assert(MO.isExpr() && "Unexpected machine operand type!");
960 const MCExpr *Expr = MO.getExpr();
961 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
962 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
964 ++MCNumCPRelocations;
966 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
968 // FIXME: The immediate operand should have already been encoded like this
969 // before ever getting here. The encoder method should just need to combine
970 // the MI operands for the register and the offset into a single
971 // representation for the complex operand in the .td file. This isn't just
972 // style, unfortunately. As-is, we can't represent the distinct encoding
974 uint32_t Binary = (Imm8 >> 2) & 0xff;
975 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
978 Binary |= (Reg << 9);
982 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
983 /// 'reg + imm8<<2' operand.
984 uint32_t ARMMCCodeEmitter::
985 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
986 SmallVectorImpl<MCFixup> &Fixups,
987 const MCSubtargetInfo &STI) const {
990 const MCOperand &MO = MI.getOperand(OpIdx);
991 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
992 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
993 unsigned Imm8 = MO1.getImm();
994 return (Reg << 8) | Imm8;
998 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
999 SmallVectorImpl<MCFixup> &Fixups,
1000 const MCSubtargetInfo &STI) const {
1001 // {20-16} = imm{15-12}
1002 // {11-0} = imm{11-0}
1003 const MCOperand &MO = MI.getOperand(OpIdx);
1005 // Hi / lo 16 bits already extracted during earlier passes.
1006 return static_cast<unsigned>(MO.getImm());
1008 // Handle :upper16: and :lower16: assembly prefixes.
1009 const MCExpr *E = MO.getExpr();
1011 if (E->getKind() == MCExpr::Target) {
1012 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1013 E = ARM16Expr->getSubExpr();
1015 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1016 const int64_t Value = MCE->getValue();
1017 if (Value > UINT32_MAX)
1018 report_fatal_error("constant value truncated (limited to 32-bit)");
1020 switch (ARM16Expr->getKind()) {
1021 case ARMMCExpr::VK_ARM_HI16:
1022 return (int32_t(Value) & 0xffff0000) >> 16;
1023 case ARMMCExpr::VK_ARM_LO16:
1024 return (int32_t(Value) & 0x0000ffff);
1025 default: llvm_unreachable("Unsupported ARMFixup");
1029 switch (ARM16Expr->getKind()) {
1030 default: llvm_unreachable("Unsupported ARMFixup");
1031 case ARMMCExpr::VK_ARM_HI16:
1032 Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movt_hi16
1033 : ARM::fixup_arm_movt_hi16);
1035 case ARMMCExpr::VK_ARM_LO16:
1036 Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movw_lo16
1037 : ARM::fixup_arm_movw_lo16);
1041 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
1044 // If the expression doesn't have :upper16: or :lower16: on it,
1045 // it's just a plain immediate expression, previously those evaluated to
1046 // the lower 16 bits of the expression regardless of whether
1047 // we have a movt or a movw, but that led to misleadingly results.
1048 // This is now disallowed in the the AsmParser in validateInstruction()
1049 // so this should never happen.
1050 assert(0 && "expression without :upper16: or :lower16:");
1054 uint32_t ARMMCCodeEmitter::
1055 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1056 SmallVectorImpl<MCFixup> &Fixups,
1057 const MCSubtargetInfo &STI) const {
1058 const MCOperand &MO = MI.getOperand(OpIdx);
1059 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1060 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1061 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1062 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1063 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1064 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1065 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1066 unsigned SBits = getShiftOp(ShOp);
1068 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1069 // amount. However, it would be an easy mistake to make so check here.
1070 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1079 uint32_t Binary = Rm;
1081 Binary |= SBits << 5;
1082 Binary |= ShImm << 7;
1088 uint32_t ARMMCCodeEmitter::
1089 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
1090 SmallVectorImpl<MCFixup> &Fixups,
1091 const MCSubtargetInfo &STI) const {
1093 // {13} 1 == imm12, 0 == Rm
1096 const MCOperand &MO = MI.getOperand(OpIdx);
1097 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1098 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
1103 uint32_t ARMMCCodeEmitter::
1104 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1105 SmallVectorImpl<MCFixup> &Fixups,
1106 const MCSubtargetInfo &STI) const {
1107 // {13} 1 == imm12, 0 == Rm
1110 const MCOperand &MO = MI.getOperand(OpIdx);
1111 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1112 unsigned Imm = MO1.getImm();
1113 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1114 bool isReg = MO.getReg() != 0;
1115 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1116 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1118 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1119 Binary <<= 7; // Shift amount is bits [11:7]
1120 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1121 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1123 return Binary | (isAdd << 12) | (isReg << 13);
1126 uint32_t ARMMCCodeEmitter::
1127 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1128 SmallVectorImpl<MCFixup> &Fixups,
1129 const MCSubtargetInfo &STI) const {
1132 const MCOperand &MO = MI.getOperand(OpIdx);
1133 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1134 bool isAdd = MO1.getImm() != 0;
1135 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1138 uint32_t ARMMCCodeEmitter::
1139 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1140 SmallVectorImpl<MCFixup> &Fixups,
1141 const MCSubtargetInfo &STI) const {
1142 // {9} 1 == imm8, 0 == Rm
1144 // {7-4} imm7_4/zero
1146 const MCOperand &MO = MI.getOperand(OpIdx);
1147 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1148 unsigned Imm = MO1.getImm();
1149 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1150 bool isImm = MO.getReg() == 0;
1151 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1152 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1154 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1155 return Imm8 | (isAdd << 8) | (isImm << 9);
1158 uint32_t ARMMCCodeEmitter::
1159 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1160 SmallVectorImpl<MCFixup> &Fixups,
1161 const MCSubtargetInfo &STI) const {
1162 // {13} 1 == imm8, 0 == Rm
1165 // {7-4} imm7_4/zero
1167 const MCOperand &MO = MI.getOperand(OpIdx);
1168 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1169 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1171 // If The first operand isn't a register, we have a label reference.
1173 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1175 assert(MO.isExpr() && "Unexpected machine operand type!");
1176 const MCExpr *Expr = MO.getExpr();
1177 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1178 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1180 ++MCNumCPRelocations;
1181 return (Rn << 9) | (1 << 13);
1183 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1184 unsigned Imm = MO2.getImm();
1185 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1186 bool isImm = MO1.getReg() == 0;
1187 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1188 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1190 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1191 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1194 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1195 uint32_t ARMMCCodeEmitter::
1196 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1197 SmallVectorImpl<MCFixup> &Fixups,
1198 const MCSubtargetInfo &STI) const {
1201 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1202 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1203 "Unexpected base register!");
1205 // The immediate is already shifted for the implicit zeroes, so no change
1207 return MO1.getImm() & 0xff;
1210 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1211 uint32_t ARMMCCodeEmitter::
1212 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1213 SmallVectorImpl<MCFixup> &Fixups,
1214 const MCSubtargetInfo &STI) const {
1218 const MCOperand &MO = MI.getOperand(OpIdx);
1219 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1220 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1221 unsigned Imm5 = MO1.getImm();
1222 return ((Imm5 & 0x1f) << 3) | Rn;
1225 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1226 uint32_t ARMMCCodeEmitter::
1227 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1228 SmallVectorImpl<MCFixup> &Fixups,
1229 const MCSubtargetInfo &STI) const {
1230 const MCOperand MO = MI.getOperand(OpIdx);
1232 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1233 return (MO.getImm() >> 2);
1236 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1237 uint32_t ARMMCCodeEmitter::
1238 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1239 SmallVectorImpl<MCFixup> &Fixups,
1240 const MCSubtargetInfo &STI) const {
1242 // {8} = (U)nsigned (add == '1', sub == '0')
1246 // If The first operand isn't a register, we have a label reference.
1247 const MCOperand &MO = MI.getOperand(OpIdx);
1249 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1251 isAdd = false; // 'U' bit is handled as part of the fixup.
1253 assert(MO.isExpr() && "Unexpected machine operand type!");
1254 const MCExpr *Expr = MO.getExpr();
1257 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1259 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1260 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1262 ++MCNumCPRelocations;
1264 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1265 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1268 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1269 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1272 Binary |= (Reg << 9);
1276 unsigned ARMMCCodeEmitter::
1277 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1278 SmallVectorImpl<MCFixup> &Fixups,
1279 const MCSubtargetInfo &STI) const {
1280 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1281 // shifted. The second is Rs, the amount to shift by, and the third specifies
1282 // the type of the shift.
1290 const MCOperand &MO = MI.getOperand(OpIdx);
1291 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1292 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1293 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1296 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1298 // Encode the shift opcode.
1300 unsigned Rs = MO1.getReg();
1302 // Set shift operand (bit[7:4]).
1308 default: llvm_unreachable("Unknown shift opc!");
1309 case ARM_AM::lsl: SBits = 0x1; break;
1310 case ARM_AM::lsr: SBits = 0x3; break;
1311 case ARM_AM::asr: SBits = 0x5; break;
1312 case ARM_AM::ror: SBits = 0x7; break;
1316 Binary |= SBits << 4;
1318 // Encode the shift operation Rs.
1319 // Encode Rs bit[11:8].
1320 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1321 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1324 unsigned ARMMCCodeEmitter::
1325 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1326 SmallVectorImpl<MCFixup> &Fixups,
1327 const MCSubtargetInfo &STI) const {
1328 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1329 // shifted. The second is the amount to shift by.
1336 const MCOperand &MO = MI.getOperand(OpIdx);
1337 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1338 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1341 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1343 // Encode the shift opcode.
1346 // Set shift operand (bit[6:4]).
1351 // RRX - 110 and bit[11:8] clear.
1353 default: llvm_unreachable("Unknown shift opc!");
1354 case ARM_AM::lsl: SBits = 0x0; break;
1355 case ARM_AM::lsr: SBits = 0x2; break;
1356 case ARM_AM::asr: SBits = 0x4; break;
1357 case ARM_AM::ror: SBits = 0x6; break;
1363 // Encode shift_imm bit[11:7].
1364 Binary |= SBits << 4;
1365 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1366 assert(Offset < 32 && "Offset must be in range 0-31!");
1367 return Binary | (Offset << 7);
1371 unsigned ARMMCCodeEmitter::
1372 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1373 SmallVectorImpl<MCFixup> &Fixups,
1374 const MCSubtargetInfo &STI) const {
1375 const MCOperand &MO1 = MI.getOperand(OpNum);
1376 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1377 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1379 // Encoded as [Rn, Rm, imm].
1380 // FIXME: Needs fixup support.
1381 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1383 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1385 Value |= MO3.getImm();
1390 unsigned ARMMCCodeEmitter::
1391 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1392 SmallVectorImpl<MCFixup> &Fixups,
1393 const MCSubtargetInfo &STI) const {
1394 const MCOperand &MO1 = MI.getOperand(OpNum);
1395 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1397 // FIXME: Needs fixup support.
1398 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1400 // Even though the immediate is 8 bits long, we need 9 bits in order
1401 // to represent the (inverse of the) sign bit.
1403 int32_t tmp = (int32_t)MO2.getImm();
1407 Value |= 256; // Set the ADD bit
1412 unsigned ARMMCCodeEmitter::
1413 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1414 SmallVectorImpl<MCFixup> &Fixups,
1415 const MCSubtargetInfo &STI) const {
1416 const MCOperand &MO1 = MI.getOperand(OpNum);
1418 // FIXME: Needs fixup support.
1420 int32_t tmp = (int32_t)MO1.getImm();
1424 Value |= 256; // Set the ADD bit
1429 unsigned ARMMCCodeEmitter::
1430 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1431 SmallVectorImpl<MCFixup> &Fixups,
1432 const MCSubtargetInfo &STI) const {
1433 const MCOperand &MO1 = MI.getOperand(OpNum);
1435 // FIXME: Needs fixup support.
1437 int32_t tmp = (int32_t)MO1.getImm();
1441 Value |= 4096; // Set the ADD bit
1442 Value |= tmp & 4095;
1446 unsigned ARMMCCodeEmitter::
1447 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1448 SmallVectorImpl<MCFixup> &Fixups,
1449 const MCSubtargetInfo &STI) const {
1450 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1451 // shifted. The second is the amount to shift by.
1458 const MCOperand &MO = MI.getOperand(OpIdx);
1459 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1460 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1463 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1465 // Encode the shift opcode.
1467 // Set shift operand (bit[6:4]).
1473 default: llvm_unreachable("Unknown shift opc!");
1474 case ARM_AM::lsl: SBits = 0x0; break;
1475 case ARM_AM::lsr: SBits = 0x2; break;
1476 case ARM_AM::asr: SBits = 0x4; break;
1477 case ARM_AM::rrx: // FALLTHROUGH
1478 case ARM_AM::ror: SBits = 0x6; break;
1481 Binary |= SBits << 4;
1482 if (SOpc == ARM_AM::rrx)
1485 // Encode shift_imm bit[11:7].
1486 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1489 unsigned ARMMCCodeEmitter::
1490 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1491 SmallVectorImpl<MCFixup> &Fixups,
1492 const MCSubtargetInfo &STI) const {
1493 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1495 const MCOperand &MO = MI.getOperand(Op);
1496 uint32_t v = ~MO.getImm();
1497 uint32_t lsb = countTrailingZeros(v);
1498 uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1499 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1500 return lsb | (msb << 5);
1503 unsigned ARMMCCodeEmitter::
1504 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1505 SmallVectorImpl<MCFixup> &Fixups,
1506 const MCSubtargetInfo &STI) const {
1509 // {7-0} = Number of registers
1512 // {15-0} = Bitfield of GPRs.
1513 unsigned Reg = MI.getOperand(Op).getReg();
1514 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1515 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1517 unsigned Binary = 0;
1519 if (SPRRegs || DPRRegs) {
1521 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1522 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1523 Binary |= (RegNo & 0x1f) << 8;
1527 Binary |= NumRegs * 2;
1529 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1530 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1531 Binary |= 1 << RegNo;
1538 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1539 /// with the alignment operand.
1540 unsigned ARMMCCodeEmitter::
1541 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1542 SmallVectorImpl<MCFixup> &Fixups,
1543 const MCSubtargetInfo &STI) const {
1544 const MCOperand &Reg = MI.getOperand(Op);
1545 const MCOperand &Imm = MI.getOperand(Op + 1);
1547 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1550 switch (Imm.getImm()) {
1554 case 8: Align = 0x01; break;
1555 case 16: Align = 0x02; break;
1556 case 32: Align = 0x03; break;
1559 return RegNo | (Align << 4);
1562 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1563 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1564 unsigned ARMMCCodeEmitter::
1565 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1566 SmallVectorImpl<MCFixup> &Fixups,
1567 const MCSubtargetInfo &STI) const {
1568 const MCOperand &Reg = MI.getOperand(Op);
1569 const MCOperand &Imm = MI.getOperand(Op + 1);
1571 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1574 switch (Imm.getImm()) {
1578 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1579 case 2: Align = 0x00; break;
1580 case 4: Align = 0x03; break;
1583 return RegNo | (Align << 4);
1587 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1588 /// alignment operand for use in VLD-dup instructions. This is the same as
1589 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1590 /// different for VLD4-dup.
1591 unsigned ARMMCCodeEmitter::
1592 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1593 SmallVectorImpl<MCFixup> &Fixups,
1594 const MCSubtargetInfo &STI) const {
1595 const MCOperand &Reg = MI.getOperand(Op);
1596 const MCOperand &Imm = MI.getOperand(Op + 1);
1598 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1601 switch (Imm.getImm()) {
1605 case 8: Align = 0x01; break;
1606 case 16: Align = 0x03; break;
1609 return RegNo | (Align << 4);
1612 unsigned ARMMCCodeEmitter::
1613 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1614 SmallVectorImpl<MCFixup> &Fixups,
1615 const MCSubtargetInfo &STI) const {
1616 const MCOperand &MO = MI.getOperand(Op);
1617 if (MO.getReg() == 0) return 0x0D;
1618 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1621 unsigned ARMMCCodeEmitter::
1622 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1623 SmallVectorImpl<MCFixup> &Fixups,
1624 const MCSubtargetInfo &STI) const {
1625 return 8 - MI.getOperand(Op).getImm();
1628 unsigned ARMMCCodeEmitter::
1629 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1630 SmallVectorImpl<MCFixup> &Fixups,
1631 const MCSubtargetInfo &STI) const {
1632 return 16 - MI.getOperand(Op).getImm();
1635 unsigned ARMMCCodeEmitter::
1636 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1637 SmallVectorImpl<MCFixup> &Fixups,
1638 const MCSubtargetInfo &STI) const {
1639 return 32 - MI.getOperand(Op).getImm();
1642 unsigned ARMMCCodeEmitter::
1643 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1644 SmallVectorImpl<MCFixup> &Fixups,
1645 const MCSubtargetInfo &STI) const {
1646 return 64 - MI.getOperand(Op).getImm();
1649 void ARMMCCodeEmitter::
1650 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1651 SmallVectorImpl<MCFixup> &Fixups,
1652 const MCSubtargetInfo &STI) const {
1653 // Pseudo instructions don't get encoded.
1654 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1655 uint64_t TSFlags = Desc.TSFlags;
1656 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1660 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1661 Size = Desc.getSize();
1663 llvm_unreachable("Unexpected instruction size!");
1665 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1666 // Thumb 32-bit wide instructions need to emit the high order halfword
1668 if (isThumb(STI) && Size == 4) {
1669 EmitConstant(Binary >> 16, 2, OS);
1670 EmitConstant(Binary & 0xffff, 2, OS);
1672 EmitConstant(Binary, Size, OS);
1673 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1676 #include "ARMGenMCCodeEmitter.inc"