1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/raw_ostream.h"
32 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
36 class ARMMCCodeEmitter : public MCCodeEmitter {
37 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39 const MCInstrInfo &MCII;
40 const MCSubtargetInfo &STI;
43 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
45 : MCII(mcii), STI(sti) {
48 ~ARMMCCodeEmitter() {}
50 bool isThumb() const {
51 // FIXME: Can tablegen auto-generate this?
52 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
54 bool isThumb2() const {
55 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
57 bool isTargetDarwin() const {
58 Triple TT(STI.getTargetTriple());
59 Triple::OSType OS = TT.getOS();
60 return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
63 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
65 // getBinaryCodeForInstr - TableGen'erated function for getting the
66 // binary encoding for an instruction.
67 uint64_t getBinaryCodeForInstr(const MCInst &MI,
68 SmallVectorImpl<MCFixup> &Fixups) const;
70 /// getMachineOpValue - Return binary encoding of operand. If the machine
71 /// operand requires relocation, record the relocation and return zero.
72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73 SmallVectorImpl<MCFixup> &Fixups) const;
75 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76 /// the specified operand. This is used for operands with :lower16: and
77 /// :upper16: prefixes.
78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82 unsigned &Reg, unsigned &Imm,
83 SmallVectorImpl<MCFixup> &Fixups) const;
85 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88 SmallVectorImpl<MCFixup> &Fixups) const;
90 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91 /// BLX branch target.
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups) const;
95 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97 SmallVectorImpl<MCFixup> &Fixups) const;
99 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101 SmallVectorImpl<MCFixup> &Fixups) const;
103 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113 /// immediate Thumb2 direct branch target.
114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups) const;
121 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
122 SmallVectorImpl<MCFixup> &Fixups) const;
123 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 SmallVectorImpl<MCFixup> &Fixups) const;
126 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
127 /// ADR label target.
128 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
130 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131 SmallVectorImpl<MCFixup> &Fixups) const;
132 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups) const;
136 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
138 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
139 SmallVectorImpl<MCFixup> &Fixups) const;
141 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
142 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
143 SmallVectorImpl<MCFixup> &Fixups)const;
145 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
147 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
148 SmallVectorImpl<MCFixup> &Fixups) const;
150 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
152 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
153 SmallVectorImpl<MCFixup> &Fixups) const;
155 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
157 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
158 SmallVectorImpl<MCFixup> &Fixups) const;
161 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
162 /// operand as needed by load/store instructions.
163 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
164 SmallVectorImpl<MCFixup> &Fixups) const;
166 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
167 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
168 SmallVectorImpl<MCFixup> &Fixups) const {
169 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
171 default: llvm_unreachable("Unknown addressing sub-mode!");
172 case ARM_AM::da: return 0;
173 case ARM_AM::ia: return 1;
174 case ARM_AM::db: return 2;
175 case ARM_AM::ib: return 3;
178 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
180 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
182 case ARM_AM::no_shift:
183 case ARM_AM::lsl: return 0;
184 case ARM_AM::lsr: return 1;
185 case ARM_AM::asr: return 2;
187 case ARM_AM::rrx: return 3;
189 llvm_unreachable("Invalid ShiftOpc!");
192 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
193 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
194 SmallVectorImpl<MCFixup> &Fixups) const;
196 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
197 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
198 SmallVectorImpl<MCFixup> &Fixups) const;
200 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
201 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
202 SmallVectorImpl<MCFixup> &Fixups) const;
204 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
205 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
206 SmallVectorImpl<MCFixup> &Fixups) const;
208 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
209 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
210 SmallVectorImpl<MCFixup> &Fixups) const;
212 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
214 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
215 SmallVectorImpl<MCFixup> &Fixups) const;
217 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
218 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
219 SmallVectorImpl<MCFixup> &Fixups) const;
221 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
222 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
223 SmallVectorImpl<MCFixup> &Fixups) const;
225 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
226 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
227 SmallVectorImpl<MCFixup> &Fixups) const;
229 /// getCCOutOpValue - Return encoding of the 's' bit.
230 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
231 SmallVectorImpl<MCFixup> &Fixups) const {
232 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
234 return MI.getOperand(Op).getReg() == ARM::CPSR;
237 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
238 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
239 SmallVectorImpl<MCFixup> &Fixups) const {
240 unsigned SoImm = MI.getOperand(Op).getImm();
241 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
242 assert(SoImmVal != -1 && "Not a valid so_imm value!");
244 // Encode rotate_imm.
245 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
246 << ARMII::SoRotImmShift;
249 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
253 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
254 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
255 SmallVectorImpl<MCFixup> &Fixups) const {
256 unsigned SoImm = MI.getOperand(Op).getImm();
257 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
258 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
262 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
263 SmallVectorImpl<MCFixup> &Fixups) const;
264 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
265 SmallVectorImpl<MCFixup> &Fixups) const;
266 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
267 SmallVectorImpl<MCFixup> &Fixups) const;
268 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
269 SmallVectorImpl<MCFixup> &Fixups) const;
271 /// getSORegOpValue - Return an encoded so_reg shifted register value.
272 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
273 SmallVectorImpl<MCFixup> &Fixups) const;
274 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
275 SmallVectorImpl<MCFixup> &Fixups) const;
276 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
277 SmallVectorImpl<MCFixup> &Fixups) const;
279 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
280 SmallVectorImpl<MCFixup> &Fixups) const {
281 return 64 - MI.getOperand(Op).getImm();
284 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
285 SmallVectorImpl<MCFixup> &Fixups) const;
287 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
288 SmallVectorImpl<MCFixup> &Fixups) const;
289 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
290 SmallVectorImpl<MCFixup> &Fixups) const;
291 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
292 SmallVectorImpl<MCFixup> &Fixups) const;
293 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
294 SmallVectorImpl<MCFixup> &Fixups) const;
295 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
296 SmallVectorImpl<MCFixup> &Fixups) const;
298 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
299 SmallVectorImpl<MCFixup> &Fixups) const;
300 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
301 SmallVectorImpl<MCFixup> &Fixups) const;
302 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
303 SmallVectorImpl<MCFixup> &Fixups) const;
304 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
305 SmallVectorImpl<MCFixup> &Fixups) const;
307 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
308 SmallVectorImpl<MCFixup> &Fixups) const;
310 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
311 unsigned EncodedValue) const;
312 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
313 unsigned EncodedValue) const;
314 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
315 unsigned EncodedValue) const;
317 unsigned VFPThumb2PostEncoder(const MCInst &MI,
318 unsigned EncodedValue) const;
320 void EmitByte(unsigned char C, raw_ostream &OS) const {
324 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
325 // Output the constant in little endian byte order.
326 for (unsigned i = 0; i != Size; ++i) {
327 EmitByte(Val & 255, OS);
332 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
333 SmallVectorImpl<MCFixup> &Fixups) const;
336 } // end anonymous namespace
338 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
339 const MCSubtargetInfo &STI,
341 return new ARMMCCodeEmitter(MCII, STI, Ctx);
344 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
345 /// instructions, and rewrite them to their Thumb2 form if we are currently in
347 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
348 unsigned EncodedValue) const {
350 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
351 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
353 unsigned Bit24 = EncodedValue & 0x01000000;
354 unsigned Bit28 = Bit24 << 4;
355 EncodedValue &= 0xEFFFFFFF;
356 EncodedValue |= Bit28;
357 EncodedValue |= 0x0F000000;
363 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
364 /// instructions, and rewrite them to their Thumb2 form if we are currently in
366 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
367 unsigned EncodedValue) const {
369 EncodedValue &= 0xF0FFFFFF;
370 EncodedValue |= 0x09000000;
376 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
377 /// instructions, and rewrite them to their Thumb2 form if we are currently in
379 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
380 unsigned EncodedValue) const {
382 EncodedValue &= 0x00FFFFFF;
383 EncodedValue |= 0xEE000000;
389 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
390 /// them to their Thumb2 form if we are currently in Thumb2 mode.
391 unsigned ARMMCCodeEmitter::
392 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
394 EncodedValue &= 0x0FFFFFFF;
395 EncodedValue |= 0xE0000000;
400 /// getMachineOpValue - Return binary encoding of operand. If the machine
401 /// operand requires relocation, record the relocation and return zero.
402 unsigned ARMMCCodeEmitter::
403 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
404 SmallVectorImpl<MCFixup> &Fixups) const {
406 unsigned Reg = MO.getReg();
407 unsigned RegNo = getARMRegisterNumbering(Reg);
409 // Q registers are encoded as 2x their register number.
413 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
414 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
415 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
416 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
419 } else if (MO.isImm()) {
420 return static_cast<unsigned>(MO.getImm());
421 } else if (MO.isFPImm()) {
422 return static_cast<unsigned>(APFloat(MO.getFPImm())
423 .bitcastToAPInt().getHiBits(32).getLimitedValue());
426 llvm_unreachable("Unable to encode MCOperand!");
429 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
430 bool ARMMCCodeEmitter::
431 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
432 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
433 const MCOperand &MO = MI.getOperand(OpIdx);
434 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
436 Reg = getARMRegisterNumbering(MO.getReg());
438 int32_t SImm = MO1.getImm();
441 // Special value for #-0
442 if (SImm == INT32_MIN) {
447 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
457 /// getBranchTargetOpValue - Helper function to get the branch target operand,
458 /// which is either an immediate or requires a fixup.
459 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
461 SmallVectorImpl<MCFixup> &Fixups) {
462 const MCOperand &MO = MI.getOperand(OpIdx);
464 // If the destination is an immediate, we have nothing to do.
465 if (MO.isImm()) return MO.getImm();
466 assert(MO.isExpr() && "Unexpected branch target type!");
467 const MCExpr *Expr = MO.getExpr();
468 MCFixupKind Kind = MCFixupKind(FixupKind);
469 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
471 // All of the information is in the fixup.
475 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
476 // determined by negating them and XOR'ing them with bit 23.
477 static int32_t encodeThumbBLOffset(int32_t offset) {
479 uint32_t S = (offset & 0x800000) >> 23;
480 uint32_t J1 = (offset & 0x400000) >> 22;
481 uint32_t J2 = (offset & 0x200000) >> 21;
494 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
495 uint32_t ARMMCCodeEmitter::
496 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
497 SmallVectorImpl<MCFixup> &Fixups) const {
498 const MCOperand MO = MI.getOperand(OpIdx);
500 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
502 return encodeThumbBLOffset(MO.getImm());
505 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
506 /// BLX branch target.
507 uint32_t ARMMCCodeEmitter::
508 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
509 SmallVectorImpl<MCFixup> &Fixups) const {
510 const MCOperand MO = MI.getOperand(OpIdx);
512 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
514 return encodeThumbBLOffset(MO.getImm());
517 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
518 uint32_t ARMMCCodeEmitter::
519 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
520 SmallVectorImpl<MCFixup> &Fixups) const {
521 const MCOperand MO = MI.getOperand(OpIdx);
523 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
525 return (MO.getImm() >> 1);
528 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
529 uint32_t ARMMCCodeEmitter::
530 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
531 SmallVectorImpl<MCFixup> &Fixups) const {
532 const MCOperand MO = MI.getOperand(OpIdx);
534 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
536 return (MO.getImm() >> 1);
539 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
540 uint32_t ARMMCCodeEmitter::
541 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
542 SmallVectorImpl<MCFixup> &Fixups) const {
543 const MCOperand MO = MI.getOperand(OpIdx);
545 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
546 return (MO.getImm() >> 1);
549 /// Return true if this branch has a non-always predication
550 static bool HasConditionalBranch(const MCInst &MI) {
551 int NumOp = MI.getNumOperands();
553 for (int i = 0; i < NumOp-1; ++i) {
554 const MCOperand &MCOp1 = MI.getOperand(i);
555 const MCOperand &MCOp2 = MI.getOperand(i + 1);
556 if (MCOp1.isImm() && MCOp2.isReg() &&
557 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
558 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
566 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
568 uint32_t ARMMCCodeEmitter::
569 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
570 SmallVectorImpl<MCFixup> &Fixups) const {
571 // FIXME: This really, really shouldn't use TargetMachine. We don't want
572 // coupling between MC and TM anywhere we can help it.
575 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
576 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
579 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
581 uint32_t ARMMCCodeEmitter::
582 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
583 SmallVectorImpl<MCFixup> &Fixups) const {
584 const MCOperand MO = MI.getOperand(OpIdx);
586 if (HasConditionalBranch(MI))
587 return ::getBranchTargetOpValue(MI, OpIdx,
588 ARM::fixup_arm_condbranch, Fixups);
589 return ::getBranchTargetOpValue(MI, OpIdx,
590 ARM::fixup_arm_uncondbranch, Fixups);
593 return MO.getImm() >> 2;
596 uint32_t ARMMCCodeEmitter::
597 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
598 SmallVectorImpl<MCFixup> &Fixups) const {
599 const MCOperand MO = MI.getOperand(OpIdx);
601 if (HasConditionalBranch(MI))
602 return ::getBranchTargetOpValue(MI, OpIdx,
603 ARM::fixup_arm_condbl, Fixups);
604 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups);
607 return MO.getImm() >> 2;
610 uint32_t ARMMCCodeEmitter::
611 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
612 SmallVectorImpl<MCFixup> &Fixups) const {
613 const MCOperand MO = MI.getOperand(OpIdx);
615 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups);
617 return MO.getImm() >> 1;
620 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
621 /// immediate branch target.
622 uint32_t ARMMCCodeEmitter::
623 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
624 SmallVectorImpl<MCFixup> &Fixups) const {
626 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
627 bool I = (Val & 0x800000);
628 bool J1 = (Val & 0x400000);
629 bool J2 = (Val & 0x200000);
643 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
645 uint32_t ARMMCCodeEmitter::
646 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
647 SmallVectorImpl<MCFixup> &Fixups) const {
648 const MCOperand MO = MI.getOperand(OpIdx);
650 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
652 int32_t offset = MO.getImm();
653 uint32_t Val = 0x2000;
662 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
664 uint32_t ARMMCCodeEmitter::
665 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
666 SmallVectorImpl<MCFixup> &Fixups) const {
667 const MCOperand MO = MI.getOperand(OpIdx);
669 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
671 int32_t Val = MO.getImm();
679 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
681 uint32_t ARMMCCodeEmitter::
682 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
683 SmallVectorImpl<MCFixup> &Fixups) const {
684 const MCOperand MO = MI.getOperand(OpIdx);
686 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
691 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
693 uint32_t ARMMCCodeEmitter::
694 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
695 SmallVectorImpl<MCFixup> &) const {
699 const MCOperand &MO1 = MI.getOperand(OpIdx);
700 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
701 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
702 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
703 return (Rm << 3) | Rn;
706 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
707 uint32_t ARMMCCodeEmitter::
708 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
709 SmallVectorImpl<MCFixup> &Fixups) const {
711 // {12} = (U)nsigned (add == '1', sub == '0')
715 // If The first operand isn't a register, we have a label reference.
716 const MCOperand &MO = MI.getOperand(OpIdx);
718 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
720 isAdd = false ; // 'U' bit is set as part of the fixup.
723 const MCExpr *Expr = MO.getExpr();
727 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
729 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
730 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
732 ++MCNumCPRelocations;
735 int32_t Offset = MO.getImm();
736 // FIXME: Handle #-0.
744 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
746 uint32_t Binary = Imm12 & 0xfff;
747 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
750 Binary |= (Reg << 13);
754 /// getT2Imm8s4OpValue - Return encoding info for
755 /// '+/- imm8<<2' operand.
756 uint32_t ARMMCCodeEmitter::
757 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
758 SmallVectorImpl<MCFixup> &Fixups) const {
759 // FIXME: The immediate operand should have already been encoded like this
760 // before ever getting here. The encoder method should just need to combine
761 // the MI operands for the register and the offset into a single
762 // representation for the complex operand in the .td file. This isn't just
763 // style, unfortunately. As-is, we can't represent the distinct encoding
766 // {8} = (U)nsigned (add == '1', sub == '0')
768 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
769 bool isAdd = Imm8 >= 0;
771 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
778 uint32_t Binary = Imm8 & 0xff;
779 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
785 /// getT2AddrModeImm8s4OpValue - Return encoding info for
786 /// 'reg +/- imm8<<2' operand.
787 uint32_t ARMMCCodeEmitter::
788 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
789 SmallVectorImpl<MCFixup> &Fixups) const {
791 // {8} = (U)nsigned (add == '1', sub == '0')
795 // If The first operand isn't a register, we have a label reference.
796 const MCOperand &MO = MI.getOperand(OpIdx);
798 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
800 isAdd = false ; // 'U' bit is set as part of the fixup.
802 assert(MO.isExpr() && "Unexpected machine operand type!");
803 const MCExpr *Expr = MO.getExpr();
804 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
805 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
807 ++MCNumCPRelocations;
809 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
811 // FIXME: The immediate operand should have already been encoded like this
812 // before ever getting here. The encoder method should just need to combine
813 // the MI operands for the register and the offset into a single
814 // representation for the complex operand in the .td file. This isn't just
815 // style, unfortunately. As-is, we can't represent the distinct encoding
817 uint32_t Binary = (Imm8 >> 2) & 0xff;
818 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
821 Binary |= (Reg << 9);
825 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
826 /// 'reg + imm8<<2' operand.
827 uint32_t ARMMCCodeEmitter::
828 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
829 SmallVectorImpl<MCFixup> &Fixups) const {
832 const MCOperand &MO = MI.getOperand(OpIdx);
833 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
834 unsigned Reg = getARMRegisterNumbering(MO.getReg());
835 unsigned Imm8 = MO1.getImm();
836 return (Reg << 8) | Imm8;
839 // FIXME: This routine assumes that a binary
840 // expression will always result in a PCRel expression
841 // In reality, its only true if one or more subexpressions
842 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
843 // but this is good enough for now.
844 static bool EvaluateAsPCRel(const MCExpr *Expr) {
845 switch (Expr->getKind()) {
846 default: llvm_unreachable("Unexpected expression type");
847 case MCExpr::SymbolRef: return false;
848 case MCExpr::Binary: return true;
853 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
854 SmallVectorImpl<MCFixup> &Fixups) const {
855 // {20-16} = imm{15-12}
856 // {11-0} = imm{11-0}
857 const MCOperand &MO = MI.getOperand(OpIdx);
859 // Hi / lo 16 bits already extracted during earlier passes.
860 return static_cast<unsigned>(MO.getImm());
862 // Handle :upper16: and :lower16: assembly prefixes.
863 const MCExpr *E = MO.getExpr();
864 if (E->getKind() == MCExpr::Target) {
865 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
866 E = ARM16Expr->getSubExpr();
869 switch (ARM16Expr->getKind()) {
870 default: llvm_unreachable("Unsupported ARMFixup");
871 case ARMMCExpr::VK_ARM_HI16:
872 if (!isTargetDarwin() && EvaluateAsPCRel(E))
873 Kind = MCFixupKind(isThumb2()
874 ? ARM::fixup_t2_movt_hi16_pcrel
875 : ARM::fixup_arm_movt_hi16_pcrel);
877 Kind = MCFixupKind(isThumb2()
878 ? ARM::fixup_t2_movt_hi16
879 : ARM::fixup_arm_movt_hi16);
881 case ARMMCExpr::VK_ARM_LO16:
882 if (!isTargetDarwin() && EvaluateAsPCRel(E))
883 Kind = MCFixupKind(isThumb2()
884 ? ARM::fixup_t2_movw_lo16_pcrel
885 : ARM::fixup_arm_movw_lo16_pcrel);
887 Kind = MCFixupKind(isThumb2()
888 ? ARM::fixup_t2_movw_lo16
889 : ARM::fixup_arm_movw_lo16);
892 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
896 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
899 uint32_t ARMMCCodeEmitter::
900 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
901 SmallVectorImpl<MCFixup> &Fixups) const {
902 const MCOperand &MO = MI.getOperand(OpIdx);
903 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
904 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
905 unsigned Rn = getARMRegisterNumbering(MO.getReg());
906 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
907 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
908 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
909 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
910 unsigned SBits = getShiftOp(ShOp);
919 uint32_t Binary = Rm;
921 Binary |= SBits << 5;
922 Binary |= ShImm << 7;
928 uint32_t ARMMCCodeEmitter::
929 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
930 SmallVectorImpl<MCFixup> &Fixups) const {
932 // {13} 1 == imm12, 0 == Rm
935 const MCOperand &MO = MI.getOperand(OpIdx);
936 unsigned Rn = getARMRegisterNumbering(MO.getReg());
937 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
942 uint32_t ARMMCCodeEmitter::
943 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
944 SmallVectorImpl<MCFixup> &Fixups) const {
945 // {13} 1 == imm12, 0 == Rm
948 const MCOperand &MO = MI.getOperand(OpIdx);
949 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
950 unsigned Imm = MO1.getImm();
951 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
952 bool isReg = MO.getReg() != 0;
953 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
954 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
956 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
957 Binary <<= 7; // Shift amount is bits [11:7]
958 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
959 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
961 return Binary | (isAdd << 12) | (isReg << 13);
964 uint32_t ARMMCCodeEmitter::
965 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
966 SmallVectorImpl<MCFixup> &Fixups) const {
969 const MCOperand &MO = MI.getOperand(OpIdx);
970 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
971 bool isAdd = MO1.getImm() != 0;
972 return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
975 uint32_t ARMMCCodeEmitter::
976 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
977 SmallVectorImpl<MCFixup> &Fixups) const {
978 // {9} 1 == imm8, 0 == Rm
982 const MCOperand &MO = MI.getOperand(OpIdx);
983 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
984 unsigned Imm = MO1.getImm();
985 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
986 bool isImm = MO.getReg() == 0;
987 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
988 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
990 Imm8 = getARMRegisterNumbering(MO.getReg());
991 return Imm8 | (isAdd << 8) | (isImm << 9);
994 uint32_t ARMMCCodeEmitter::
995 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
996 SmallVectorImpl<MCFixup> &Fixups) const {
997 // {13} 1 == imm8, 0 == Rm
1000 // {7-4} imm7_4/zero
1002 const MCOperand &MO = MI.getOperand(OpIdx);
1003 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1004 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1006 // If The first operand isn't a register, we have a label reference.
1008 unsigned Rn = getARMRegisterNumbering(ARM::PC); // Rn is PC.
1010 assert(MO.isExpr() && "Unexpected machine operand type!");
1011 const MCExpr *Expr = MO.getExpr();
1012 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1013 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1015 ++MCNumCPRelocations;
1016 return (Rn << 9) | (1 << 13);
1018 unsigned Rn = getARMRegisterNumbering(MO.getReg());
1019 unsigned Imm = MO2.getImm();
1020 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1021 bool isImm = MO1.getReg() == 0;
1022 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1023 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1025 Imm8 = getARMRegisterNumbering(MO1.getReg());
1026 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1029 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1030 uint32_t ARMMCCodeEmitter::
1031 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1032 SmallVectorImpl<MCFixup> &Fixups) const {
1035 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1036 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1037 "Unexpected base register!");
1039 // The immediate is already shifted for the implicit zeroes, so no change
1041 return MO1.getImm() & 0xff;
1044 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1045 uint32_t ARMMCCodeEmitter::
1046 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1047 SmallVectorImpl<MCFixup> &Fixups) const {
1051 const MCOperand &MO = MI.getOperand(OpIdx);
1052 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1053 unsigned Rn = getARMRegisterNumbering(MO.getReg());
1054 unsigned Imm5 = MO1.getImm();
1055 return ((Imm5 & 0x1f) << 3) | Rn;
1058 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1059 uint32_t ARMMCCodeEmitter::
1060 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1061 SmallVectorImpl<MCFixup> &Fixups) const {
1062 const MCOperand MO = MI.getOperand(OpIdx);
1064 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1065 return (MO.getImm() >> 2);
1068 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1069 uint32_t ARMMCCodeEmitter::
1070 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1071 SmallVectorImpl<MCFixup> &Fixups) const {
1073 // {8} = (U)nsigned (add == '1', sub == '0')
1077 // If The first operand isn't a register, we have a label reference.
1078 const MCOperand &MO = MI.getOperand(OpIdx);
1080 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
1082 isAdd = false; // 'U' bit is handled as part of the fixup.
1084 assert(MO.isExpr() && "Unexpected machine operand type!");
1085 const MCExpr *Expr = MO.getExpr();
1088 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1090 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1091 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1093 ++MCNumCPRelocations;
1095 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1096 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1099 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1100 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1103 Binary |= (Reg << 9);
1107 unsigned ARMMCCodeEmitter::
1108 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1109 SmallVectorImpl<MCFixup> &Fixups) const {
1110 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1111 // shifted. The second is Rs, the amount to shift by, and the third specifies
1112 // the type of the shift.
1120 const MCOperand &MO = MI.getOperand(OpIdx);
1121 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1122 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1123 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1126 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1128 // Encode the shift opcode.
1130 unsigned Rs = MO1.getReg();
1132 // Set shift operand (bit[7:4]).
1138 default: llvm_unreachable("Unknown shift opc!");
1139 case ARM_AM::lsl: SBits = 0x1; break;
1140 case ARM_AM::lsr: SBits = 0x3; break;
1141 case ARM_AM::asr: SBits = 0x5; break;
1142 case ARM_AM::ror: SBits = 0x7; break;
1146 Binary |= SBits << 4;
1148 // Encode the shift operation Rs.
1149 // Encode Rs bit[11:8].
1150 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1151 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1154 unsigned ARMMCCodeEmitter::
1155 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1156 SmallVectorImpl<MCFixup> &Fixups) const {
1157 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1158 // shifted. The second is the amount to shift by.
1165 const MCOperand &MO = MI.getOperand(OpIdx);
1166 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1167 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1170 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1172 // Encode the shift opcode.
1175 // Set shift operand (bit[6:4]).
1180 // RRX - 110 and bit[11:8] clear.
1182 default: llvm_unreachable("Unknown shift opc!");
1183 case ARM_AM::lsl: SBits = 0x0; break;
1184 case ARM_AM::lsr: SBits = 0x2; break;
1185 case ARM_AM::asr: SBits = 0x4; break;
1186 case ARM_AM::ror: SBits = 0x6; break;
1192 // Encode shift_imm bit[11:7].
1193 Binary |= SBits << 4;
1194 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1195 assert(Offset < 32 && "Offset must be in range 0-31!");
1196 return Binary | (Offset << 7);
1200 unsigned ARMMCCodeEmitter::
1201 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1202 SmallVectorImpl<MCFixup> &Fixups) const {
1203 const MCOperand &MO1 = MI.getOperand(OpNum);
1204 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1205 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1207 // Encoded as [Rn, Rm, imm].
1208 // FIXME: Needs fixup support.
1209 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1211 Value |= getARMRegisterNumbering(MO2.getReg());
1213 Value |= MO3.getImm();
1218 unsigned ARMMCCodeEmitter::
1219 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1220 SmallVectorImpl<MCFixup> &Fixups) const {
1221 const MCOperand &MO1 = MI.getOperand(OpNum);
1222 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1224 // FIXME: Needs fixup support.
1225 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1227 // Even though the immediate is 8 bits long, we need 9 bits in order
1228 // to represent the (inverse of the) sign bit.
1230 int32_t tmp = (int32_t)MO2.getImm();
1234 Value |= 256; // Set the ADD bit
1239 unsigned ARMMCCodeEmitter::
1240 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1241 SmallVectorImpl<MCFixup> &Fixups) const {
1242 const MCOperand &MO1 = MI.getOperand(OpNum);
1244 // FIXME: Needs fixup support.
1246 int32_t tmp = (int32_t)MO1.getImm();
1250 Value |= 256; // Set the ADD bit
1255 unsigned ARMMCCodeEmitter::
1256 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1257 SmallVectorImpl<MCFixup> &Fixups) const {
1258 const MCOperand &MO1 = MI.getOperand(OpNum);
1260 // FIXME: Needs fixup support.
1262 int32_t tmp = (int32_t)MO1.getImm();
1266 Value |= 4096; // Set the ADD bit
1267 Value |= tmp & 4095;
1271 unsigned ARMMCCodeEmitter::
1272 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1273 SmallVectorImpl<MCFixup> &Fixups) const {
1274 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1275 // shifted. The second is the amount to shift by.
1282 const MCOperand &MO = MI.getOperand(OpIdx);
1283 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1284 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1287 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1289 // Encode the shift opcode.
1291 // Set shift operand (bit[6:4]).
1297 default: llvm_unreachable("Unknown shift opc!");
1298 case ARM_AM::lsl: SBits = 0x0; break;
1299 case ARM_AM::lsr: SBits = 0x2; break;
1300 case ARM_AM::asr: SBits = 0x4; break;
1301 case ARM_AM::rrx: // FALLTHROUGH
1302 case ARM_AM::ror: SBits = 0x6; break;
1305 Binary |= SBits << 4;
1306 if (SOpc == ARM_AM::rrx)
1309 // Encode shift_imm bit[11:7].
1310 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1313 unsigned ARMMCCodeEmitter::
1314 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1315 SmallVectorImpl<MCFixup> &Fixups) const {
1316 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1318 const MCOperand &MO = MI.getOperand(Op);
1319 uint32_t v = ~MO.getImm();
1320 uint32_t lsb = CountTrailingZeros_32(v);
1321 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1322 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1323 return lsb | (msb << 5);
1326 unsigned ARMMCCodeEmitter::
1327 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1328 SmallVectorImpl<MCFixup> &Fixups) const {
1331 // {7-0} = Number of registers
1334 // {15-0} = Bitfield of GPRs.
1335 unsigned Reg = MI.getOperand(Op).getReg();
1336 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1337 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1339 unsigned Binary = 0;
1341 if (SPRRegs || DPRRegs) {
1343 unsigned RegNo = getARMRegisterNumbering(Reg);
1344 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1345 Binary |= (RegNo & 0x1f) << 8;
1349 Binary |= NumRegs * 2;
1351 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1352 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1353 Binary |= 1 << RegNo;
1360 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1361 /// with the alignment operand.
1362 unsigned ARMMCCodeEmitter::
1363 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1364 SmallVectorImpl<MCFixup> &Fixups) const {
1365 const MCOperand &Reg = MI.getOperand(Op);
1366 const MCOperand &Imm = MI.getOperand(Op + 1);
1368 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1371 switch (Imm.getImm()) {
1375 case 8: Align = 0x01; break;
1376 case 16: Align = 0x02; break;
1377 case 32: Align = 0x03; break;
1380 return RegNo | (Align << 4);
1383 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1384 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1385 unsigned ARMMCCodeEmitter::
1386 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1387 SmallVectorImpl<MCFixup> &Fixups) const {
1388 const MCOperand &Reg = MI.getOperand(Op);
1389 const MCOperand &Imm = MI.getOperand(Op + 1);
1391 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1394 switch (Imm.getImm()) {
1398 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1399 case 2: Align = 0x00; break;
1400 case 4: Align = 0x03; break;
1403 return RegNo | (Align << 4);
1407 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1408 /// alignment operand for use in VLD-dup instructions. This is the same as
1409 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1410 /// different for VLD4-dup.
1411 unsigned ARMMCCodeEmitter::
1412 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1413 SmallVectorImpl<MCFixup> &Fixups) const {
1414 const MCOperand &Reg = MI.getOperand(Op);
1415 const MCOperand &Imm = MI.getOperand(Op + 1);
1417 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1420 switch (Imm.getImm()) {
1424 case 8: Align = 0x01; break;
1425 case 16: Align = 0x03; break;
1428 return RegNo | (Align << 4);
1431 unsigned ARMMCCodeEmitter::
1432 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1433 SmallVectorImpl<MCFixup> &Fixups) const {
1434 const MCOperand &MO = MI.getOperand(Op);
1435 if (MO.getReg() == 0) return 0x0D;
1436 return getARMRegisterNumbering(MO.getReg());
1439 unsigned ARMMCCodeEmitter::
1440 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1441 SmallVectorImpl<MCFixup> &Fixups) const {
1442 return 8 - MI.getOperand(Op).getImm();
1445 unsigned ARMMCCodeEmitter::
1446 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1447 SmallVectorImpl<MCFixup> &Fixups) const {
1448 return 16 - MI.getOperand(Op).getImm();
1451 unsigned ARMMCCodeEmitter::
1452 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1453 SmallVectorImpl<MCFixup> &Fixups) const {
1454 return 32 - MI.getOperand(Op).getImm();
1457 unsigned ARMMCCodeEmitter::
1458 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1459 SmallVectorImpl<MCFixup> &Fixups) const {
1460 return 64 - MI.getOperand(Op).getImm();
1463 void ARMMCCodeEmitter::
1464 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1465 SmallVectorImpl<MCFixup> &Fixups) const {
1466 // Pseudo instructions don't get encoded.
1467 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1468 uint64_t TSFlags = Desc.TSFlags;
1469 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1473 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1474 Size = Desc.getSize();
1476 llvm_unreachable("Unexpected instruction size!");
1478 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1479 // Thumb 32-bit wide instructions need to emit the high order halfword
1481 if (isThumb() && Size == 4) {
1482 EmitConstant(Binary >> 16, 2, OS);
1483 EmitConstant(Binary & 0xffff, 2, OS);
1485 EmitConstant(Binary, Size, OS);
1486 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1489 #include "ARMGenMCCodeEmitter.inc"