1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/raw_ostream.h"
32 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
36 class ARMMCCodeEmitter : public MCCodeEmitter {
37 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39 const MCInstrInfo &MCII;
40 const MCSubtargetInfo &STI;
43 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
45 : MCII(mcii), STI(sti) {
48 ~ARMMCCodeEmitter() {}
50 bool isThumb() const {
51 // FIXME: Can tablegen auto-generate this?
52 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
54 bool isThumb2() const {
55 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
57 bool isTargetDarwin() const {
58 Triple TT(STI.getTargetTriple());
59 Triple::OSType OS = TT.getOS();
60 return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
63 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
65 // getBinaryCodeForInstr - TableGen'erated function for getting the
66 // binary encoding for an instruction.
67 unsigned getBinaryCodeForInstr(const MCInst &MI,
68 SmallVectorImpl<MCFixup> &Fixups) const;
70 /// getMachineOpValue - Return binary encoding of operand. If the machine
71 /// operand requires relocation, record the relocation and return zero.
72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73 SmallVectorImpl<MCFixup> &Fixups) const;
75 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76 /// the specified operand. This is used for operands with :lower16: and
77 /// :upper16: prefixes.
78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82 unsigned &Reg, unsigned &Imm,
83 SmallVectorImpl<MCFixup> &Fixups) const;
85 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88 SmallVectorImpl<MCFixup> &Fixups) const;
90 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91 /// BLX branch target.
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups) const;
95 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97 SmallVectorImpl<MCFixup> &Fixups) const;
99 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101 SmallVectorImpl<MCFixup> &Fixups) const;
103 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113 /// immediate Thumb2 direct branch target.
114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups) const;
121 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
122 SmallVectorImpl<MCFixup> &Fixups) const;
124 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
125 /// ADR label target.
126 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
127 SmallVectorImpl<MCFixup> &Fixups) const;
128 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
130 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131 SmallVectorImpl<MCFixup> &Fixups) const;
134 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
136 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
137 SmallVectorImpl<MCFixup> &Fixups) const;
139 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
140 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups)const;
143 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
145 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
146 SmallVectorImpl<MCFixup> &Fixups) const;
148 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
150 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
151 SmallVectorImpl<MCFixup> &Fixups) const;
153 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
155 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
156 SmallVectorImpl<MCFixup> &Fixups) const;
159 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
160 /// operand as needed by load/store instructions.
161 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
162 SmallVectorImpl<MCFixup> &Fixups) const;
164 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
165 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups) const {
167 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
169 default: assert(0 && "Unknown addressing sub-mode!");
170 case ARM_AM::da: return 0;
171 case ARM_AM::ia: return 1;
172 case ARM_AM::db: return 2;
173 case ARM_AM::ib: return 3;
176 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
178 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
180 default: llvm_unreachable("Unknown shift opc!");
181 case ARM_AM::no_shift:
182 case ARM_AM::lsl: return 0;
183 case ARM_AM::lsr: return 1;
184 case ARM_AM::asr: return 2;
186 case ARM_AM::rrx: return 3;
191 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
192 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
193 SmallVectorImpl<MCFixup> &Fixups) const;
195 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
196 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
197 SmallVectorImpl<MCFixup> &Fixups) const;
199 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
200 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
201 SmallVectorImpl<MCFixup> &Fixups) const;
203 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
204 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
205 SmallVectorImpl<MCFixup> &Fixups) const;
207 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
208 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
209 SmallVectorImpl<MCFixup> &Fixups) const;
211 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
213 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
214 SmallVectorImpl<MCFixup> &Fixups) const;
216 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
217 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
218 SmallVectorImpl<MCFixup> &Fixups) const;
220 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
221 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
222 SmallVectorImpl<MCFixup> &Fixups) const;
224 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
225 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
226 SmallVectorImpl<MCFixup> &Fixups) const;
228 /// getCCOutOpValue - Return encoding of the 's' bit.
229 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
230 SmallVectorImpl<MCFixup> &Fixups) const {
231 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
233 return MI.getOperand(Op).getReg() == ARM::CPSR;
236 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
237 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
238 SmallVectorImpl<MCFixup> &Fixups) const {
239 unsigned SoImm = MI.getOperand(Op).getImm();
240 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
241 assert(SoImmVal != -1 && "Not a valid so_imm value!");
243 // Encode rotate_imm.
244 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
245 << ARMII::SoRotImmShift;
248 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
252 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
253 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
254 SmallVectorImpl<MCFixup> &Fixups) const {
255 unsigned SoImm = MI.getOperand(Op).getImm();
256 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
257 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
261 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
262 SmallVectorImpl<MCFixup> &Fixups) const;
263 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
264 SmallVectorImpl<MCFixup> &Fixups) const;
265 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
266 SmallVectorImpl<MCFixup> &Fixups) const;
267 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
268 SmallVectorImpl<MCFixup> &Fixups) const;
270 /// getSORegOpValue - Return an encoded so_reg shifted register value.
271 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
272 SmallVectorImpl<MCFixup> &Fixups) const;
273 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
274 SmallVectorImpl<MCFixup> &Fixups) const;
275 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
276 SmallVectorImpl<MCFixup> &Fixups) const;
278 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
279 SmallVectorImpl<MCFixup> &Fixups) const {
280 return 64 - MI.getOperand(Op).getImm();
283 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
284 SmallVectorImpl<MCFixup> &Fixups) const;
286 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
287 SmallVectorImpl<MCFixup> &Fixups) const;
288 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
289 SmallVectorImpl<MCFixup> &Fixups) const;
290 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
291 SmallVectorImpl<MCFixup> &Fixups) const;
292 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
293 SmallVectorImpl<MCFixup> &Fixups) const;
294 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
295 SmallVectorImpl<MCFixup> &Fixups) const;
297 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
298 SmallVectorImpl<MCFixup> &Fixups) const;
299 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
300 SmallVectorImpl<MCFixup> &Fixups) const;
301 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
302 SmallVectorImpl<MCFixup> &Fixups) const;
303 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
304 SmallVectorImpl<MCFixup> &Fixups) const;
306 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
307 SmallVectorImpl<MCFixup> &Fixups) const;
309 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
310 unsigned EncodedValue) const;
311 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
312 unsigned EncodedValue) const;
313 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
314 unsigned EncodedValue) const;
316 unsigned VFPThumb2PostEncoder(const MCInst &MI,
317 unsigned EncodedValue) const;
319 void EmitByte(unsigned char C, raw_ostream &OS) const {
323 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
324 // Output the constant in little endian byte order.
325 for (unsigned i = 0; i != Size; ++i) {
326 EmitByte(Val & 255, OS);
331 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
332 SmallVectorImpl<MCFixup> &Fixups) const;
335 } // end anonymous namespace
337 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
338 const MCSubtargetInfo &STI,
340 return new ARMMCCodeEmitter(MCII, STI, Ctx);
343 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
344 /// instructions, and rewrite them to their Thumb2 form if we are currently in
346 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
347 unsigned EncodedValue) const {
349 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
350 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
352 unsigned Bit24 = EncodedValue & 0x01000000;
353 unsigned Bit28 = Bit24 << 4;
354 EncodedValue &= 0xEFFFFFFF;
355 EncodedValue |= Bit28;
356 EncodedValue |= 0x0F000000;
362 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
363 /// instructions, and rewrite them to their Thumb2 form if we are currently in
365 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
366 unsigned EncodedValue) const {
368 EncodedValue &= 0xF0FFFFFF;
369 EncodedValue |= 0x09000000;
375 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
376 /// instructions, and rewrite them to their Thumb2 form if we are currently in
378 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
379 unsigned EncodedValue) const {
381 EncodedValue &= 0x00FFFFFF;
382 EncodedValue |= 0xEE000000;
388 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
389 /// them to their Thumb2 form if we are currently in Thumb2 mode.
390 unsigned ARMMCCodeEmitter::
391 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
393 EncodedValue &= 0x0FFFFFFF;
394 EncodedValue |= 0xE0000000;
399 /// getMachineOpValue - Return binary encoding of operand. If the machine
400 /// operand requires relocation, record the relocation and return zero.
401 unsigned ARMMCCodeEmitter::
402 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
403 SmallVectorImpl<MCFixup> &Fixups) const {
405 unsigned Reg = MO.getReg();
406 unsigned RegNo = getARMRegisterNumbering(Reg);
408 // Q registers are encoded as 2x their register number.
412 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
413 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
414 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
415 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
418 } else if (MO.isImm()) {
419 return static_cast<unsigned>(MO.getImm());
420 } else if (MO.isFPImm()) {
421 return static_cast<unsigned>(APFloat(MO.getFPImm())
422 .bitcastToAPInt().getHiBits(32).getLimitedValue());
425 llvm_unreachable("Unable to encode MCOperand!");
429 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
430 bool ARMMCCodeEmitter::
431 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
432 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
433 const MCOperand &MO = MI.getOperand(OpIdx);
434 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
436 Reg = getARMRegisterNumbering(MO.getReg());
438 int32_t SImm = MO1.getImm();
441 // Special value for #-0
442 if (SImm == INT32_MIN) {
447 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
457 /// getBranchTargetOpValue - Helper function to get the branch target operand,
458 /// which is either an immediate or requires a fixup.
459 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
461 SmallVectorImpl<MCFixup> &Fixups) {
462 const MCOperand &MO = MI.getOperand(OpIdx);
464 // If the destination is an immediate, we have nothing to do.
465 if (MO.isImm()) return MO.getImm();
466 assert(MO.isExpr() && "Unexpected branch target type!");
467 const MCExpr *Expr = MO.getExpr();
468 MCFixupKind Kind = MCFixupKind(FixupKind);
469 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
471 // All of the information is in the fixup.
475 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
476 // determined by negating them and XOR'ing them with bit 23.
477 static int32_t encodeThumbBLOffset(int32_t offset) {
479 uint32_t S = (offset & 0x800000) >> 23;
480 uint32_t J1 = (offset & 0x400000) >> 22;
481 uint32_t J2 = (offset & 0x200000) >> 21;
494 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
495 uint32_t ARMMCCodeEmitter::
496 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
497 SmallVectorImpl<MCFixup> &Fixups) const {
498 const MCOperand MO = MI.getOperand(OpIdx);
500 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
502 return encodeThumbBLOffset(MO.getImm());
505 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
506 /// BLX branch target.
507 uint32_t ARMMCCodeEmitter::
508 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
509 SmallVectorImpl<MCFixup> &Fixups) const {
510 const MCOperand MO = MI.getOperand(OpIdx);
512 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
514 return encodeThumbBLOffset(MO.getImm());
517 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
518 uint32_t ARMMCCodeEmitter::
519 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
520 SmallVectorImpl<MCFixup> &Fixups) const {
521 const MCOperand MO = MI.getOperand(OpIdx);
523 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
525 return (MO.getImm() >> 1);
528 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
529 uint32_t ARMMCCodeEmitter::
530 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
531 SmallVectorImpl<MCFixup> &Fixups) const {
532 const MCOperand MO = MI.getOperand(OpIdx);
534 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
536 return (MO.getImm() >> 1);
539 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
540 uint32_t ARMMCCodeEmitter::
541 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
542 SmallVectorImpl<MCFixup> &Fixups) const {
543 const MCOperand MO = MI.getOperand(OpIdx);
545 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
546 return (MO.getImm() >> 1);
549 /// Return true if this branch has a non-always predication
550 static bool HasConditionalBranch(const MCInst &MI) {
551 int NumOp = MI.getNumOperands();
553 for (int i = 0; i < NumOp-1; ++i) {
554 const MCOperand &MCOp1 = MI.getOperand(i);
555 const MCOperand &MCOp2 = MI.getOperand(i + 1);
556 if (MCOp1.isImm() && MCOp2.isReg() &&
557 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
558 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
566 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
568 uint32_t ARMMCCodeEmitter::
569 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
570 SmallVectorImpl<MCFixup> &Fixups) const {
571 // FIXME: This really, really shouldn't use TargetMachine. We don't want
572 // coupling between MC and TM anywhere we can help it.
575 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
576 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
579 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
581 uint32_t ARMMCCodeEmitter::
582 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
583 SmallVectorImpl<MCFixup> &Fixups) const {
584 const MCOperand MO = MI.getOperand(OpIdx);
586 if (HasConditionalBranch(MI))
587 return ::getBranchTargetOpValue(MI, OpIdx,
588 ARM::fixup_arm_condbranch, Fixups);
589 return ::getBranchTargetOpValue(MI, OpIdx,
590 ARM::fixup_arm_uncondbranch, Fixups);
593 return MO.getImm() >> 2;
596 uint32_t ARMMCCodeEmitter::
597 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
598 SmallVectorImpl<MCFixup> &Fixups) const {
599 const MCOperand MO = MI.getOperand(OpIdx);
601 if (HasConditionalBranch(MI))
602 return ::getBranchTargetOpValue(MI, OpIdx,
603 ARM::fixup_arm_condbranch, Fixups);
604 return ::getBranchTargetOpValue(MI, OpIdx,
605 ARM::fixup_arm_uncondbranch, Fixups);
608 return MO.getImm() >> 1;
611 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
612 /// immediate branch target.
613 uint32_t ARMMCCodeEmitter::
614 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
615 SmallVectorImpl<MCFixup> &Fixups) const {
617 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
618 bool I = (Val & 0x800000);
619 bool J1 = (Val & 0x400000);
620 bool J2 = (Val & 0x200000);
634 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
636 uint32_t ARMMCCodeEmitter::
637 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
638 SmallVectorImpl<MCFixup> &Fixups) const {
639 const MCOperand MO = MI.getOperand(OpIdx);
641 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
643 int32_t offset = MO.getImm();
644 uint32_t Val = 0x2000;
653 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
655 uint32_t ARMMCCodeEmitter::
656 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
657 SmallVectorImpl<MCFixup> &Fixups) const {
658 const MCOperand MO = MI.getOperand(OpIdx);
660 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
662 int32_t Val = MO.getImm();
670 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
672 uint32_t ARMMCCodeEmitter::
673 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
674 SmallVectorImpl<MCFixup> &Fixups) const {
675 const MCOperand MO = MI.getOperand(OpIdx);
677 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
682 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
684 uint32_t ARMMCCodeEmitter::
685 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
686 SmallVectorImpl<MCFixup> &) const {
690 const MCOperand &MO1 = MI.getOperand(OpIdx);
691 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
692 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
693 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
694 return (Rm << 3) | Rn;
697 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
698 uint32_t ARMMCCodeEmitter::
699 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
700 SmallVectorImpl<MCFixup> &Fixups) const {
702 // {12} = (U)nsigned (add == '1', sub == '0')
706 // If The first operand isn't a register, we have a label reference.
707 const MCOperand &MO = MI.getOperand(OpIdx);
709 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
711 isAdd = false ; // 'U' bit is set as part of the fixup.
714 const MCExpr *Expr = MO.getExpr();
718 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
720 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
721 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
723 ++MCNumCPRelocations;
726 int32_t Offset = MO.getImm();
734 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
736 uint32_t Binary = Imm12 & 0xfff;
737 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
740 Binary |= (Reg << 13);
744 /// getT2Imm8s4OpValue - Return encoding info for
745 /// '+/- imm8<<2' operand.
746 uint32_t ARMMCCodeEmitter::
747 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
748 SmallVectorImpl<MCFixup> &Fixups) const {
749 // FIXME: The immediate operand should have already been encoded like this
750 // before ever getting here. The encoder method should just need to combine
751 // the MI operands for the register and the offset into a single
752 // representation for the complex operand in the .td file. This isn't just
753 // style, unfortunately. As-is, we can't represent the distinct encoding
756 // {8} = (U)nsigned (add == '1', sub == '0')
758 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
759 bool isAdd = Imm8 >= 0;
761 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
768 uint32_t Binary = Imm8 & 0xff;
769 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
775 /// getT2AddrModeImm8s4OpValue - Return encoding info for
776 /// 'reg +/- imm8<<2' operand.
777 uint32_t ARMMCCodeEmitter::
778 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
779 SmallVectorImpl<MCFixup> &Fixups) const {
781 // {8} = (U)nsigned (add == '1', sub == '0')
785 // If The first operand isn't a register, we have a label reference.
786 const MCOperand &MO = MI.getOperand(OpIdx);
788 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
790 isAdd = false ; // 'U' bit is set as part of the fixup.
792 assert(MO.isExpr() && "Unexpected machine operand type!");
793 const MCExpr *Expr = MO.getExpr();
794 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
795 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
797 ++MCNumCPRelocations;
799 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
801 // FIXME: The immediate operand should have already been encoded like this
802 // before ever getting here. The encoder method should just need to combine
803 // the MI operands for the register and the offset into a single
804 // representation for the complex operand in the .td file. This isn't just
805 // style, unfortunately. As-is, we can't represent the distinct encoding
807 uint32_t Binary = (Imm8 >> 2) & 0xff;
808 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
811 Binary |= (Reg << 9);
815 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
816 /// 'reg + imm8<<2' operand.
817 uint32_t ARMMCCodeEmitter::
818 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
819 SmallVectorImpl<MCFixup> &Fixups) const {
822 const MCOperand &MO = MI.getOperand(OpIdx);
823 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
824 unsigned Reg = getARMRegisterNumbering(MO.getReg());
825 unsigned Imm8 = MO1.getImm();
826 return (Reg << 8) | Imm8;
829 // FIXME: This routine assumes that a binary
830 // expression will always result in a PCRel expression
831 // In reality, its only true if one or more subexpressions
832 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
833 // but this is good enough for now.
834 static bool EvaluateAsPCRel(const MCExpr *Expr) {
835 switch (Expr->getKind()) {
836 default: assert(0 && "Unexpected expression type");
837 case MCExpr::SymbolRef: return false;
838 case MCExpr::Binary: return true;
843 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
844 SmallVectorImpl<MCFixup> &Fixups) const {
845 // {20-16} = imm{15-12}
846 // {11-0} = imm{11-0}
847 const MCOperand &MO = MI.getOperand(OpIdx);
849 // Hi / lo 16 bits already extracted during earlier passes.
850 return static_cast<unsigned>(MO.getImm());
852 // Handle :upper16: and :lower16: assembly prefixes.
853 const MCExpr *E = MO.getExpr();
854 if (E->getKind() == MCExpr::Target) {
855 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
856 E = ARM16Expr->getSubExpr();
859 switch (ARM16Expr->getKind()) {
860 default: assert(0 && "Unsupported ARMFixup");
861 case ARMMCExpr::VK_ARM_HI16:
862 if (!isTargetDarwin() && EvaluateAsPCRel(E))
863 Kind = MCFixupKind(isThumb2()
864 ? ARM::fixup_t2_movt_hi16_pcrel
865 : ARM::fixup_arm_movt_hi16_pcrel);
867 Kind = MCFixupKind(isThumb2()
868 ? ARM::fixup_t2_movt_hi16
869 : ARM::fixup_arm_movt_hi16);
871 case ARMMCExpr::VK_ARM_LO16:
872 if (!isTargetDarwin() && EvaluateAsPCRel(E))
873 Kind = MCFixupKind(isThumb2()
874 ? ARM::fixup_t2_movw_lo16_pcrel
875 : ARM::fixup_arm_movw_lo16_pcrel);
877 Kind = MCFixupKind(isThumb2()
878 ? ARM::fixup_t2_movw_lo16
879 : ARM::fixup_arm_movw_lo16);
882 Fixups.push_back(MCFixup::Create(0, E, Kind));
886 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
890 uint32_t ARMMCCodeEmitter::
891 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
892 SmallVectorImpl<MCFixup> &Fixups) const {
893 const MCOperand &MO = MI.getOperand(OpIdx);
894 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
895 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
896 unsigned Rn = getARMRegisterNumbering(MO.getReg());
897 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
898 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
899 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
900 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
901 unsigned SBits = getShiftOp(ShOp);
910 uint32_t Binary = Rm;
912 Binary |= SBits << 5;
913 Binary |= ShImm << 7;
919 uint32_t ARMMCCodeEmitter::
920 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
921 SmallVectorImpl<MCFixup> &Fixups) const {
923 // {13} 1 == imm12, 0 == Rm
926 const MCOperand &MO = MI.getOperand(OpIdx);
927 unsigned Rn = getARMRegisterNumbering(MO.getReg());
928 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
933 uint32_t ARMMCCodeEmitter::
934 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
935 SmallVectorImpl<MCFixup> &Fixups) const {
936 // {13} 1 == imm12, 0 == Rm
939 const MCOperand &MO = MI.getOperand(OpIdx);
940 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
941 unsigned Imm = MO1.getImm();
942 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
943 bool isReg = MO.getReg() != 0;
944 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
945 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
947 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
948 Binary <<= 7; // Shift amount is bits [11:7]
949 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
950 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
952 return Binary | (isAdd << 12) | (isReg << 13);
955 uint32_t ARMMCCodeEmitter::
956 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
957 SmallVectorImpl<MCFixup> &Fixups) const {
960 const MCOperand &MO = MI.getOperand(OpIdx);
961 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
962 bool isAdd = MO1.getImm() != 0;
963 return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
966 uint32_t ARMMCCodeEmitter::
967 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
968 SmallVectorImpl<MCFixup> &Fixups) const {
969 // {9} 1 == imm8, 0 == Rm
973 const MCOperand &MO = MI.getOperand(OpIdx);
974 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
975 unsigned Imm = MO1.getImm();
976 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
977 bool isImm = MO.getReg() == 0;
978 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
979 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
981 Imm8 = getARMRegisterNumbering(MO.getReg());
982 return Imm8 | (isAdd << 8) | (isImm << 9);
985 uint32_t ARMMCCodeEmitter::
986 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
987 SmallVectorImpl<MCFixup> &Fixups) const {
988 // {13} 1 == imm8, 0 == Rm
993 const MCOperand &MO = MI.getOperand(OpIdx);
994 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
995 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
996 unsigned Rn = getARMRegisterNumbering(MO.getReg());
997 unsigned Imm = MO2.getImm();
998 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
999 bool isImm = MO1.getReg() == 0;
1000 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1001 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1003 Imm8 = getARMRegisterNumbering(MO1.getReg());
1004 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1007 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1008 uint32_t ARMMCCodeEmitter::
1009 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1010 SmallVectorImpl<MCFixup> &Fixups) const {
1013 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1014 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1015 "Unexpected base register!");
1017 // The immediate is already shifted for the implicit zeroes, so no change
1019 return MO1.getImm() & 0xff;
1022 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1023 uint32_t ARMMCCodeEmitter::
1024 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1025 SmallVectorImpl<MCFixup> &Fixups) const {
1029 const MCOperand &MO = MI.getOperand(OpIdx);
1030 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1031 unsigned Rn = getARMRegisterNumbering(MO.getReg());
1032 unsigned Imm5 = MO1.getImm();
1033 return ((Imm5 & 0x1f) << 3) | Rn;
1036 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1037 uint32_t ARMMCCodeEmitter::
1038 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1039 SmallVectorImpl<MCFixup> &Fixups) const {
1040 const MCOperand MO = MI.getOperand(OpIdx);
1042 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1043 return (MO.getImm() >> 2);
1046 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1047 uint32_t ARMMCCodeEmitter::
1048 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1049 SmallVectorImpl<MCFixup> &Fixups) const {
1051 // {8} = (U)nsigned (add == '1', sub == '0')
1055 // If The first operand isn't a register, we have a label reference.
1056 const MCOperand &MO = MI.getOperand(OpIdx);
1058 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
1060 isAdd = false; // 'U' bit is handled as part of the fixup.
1062 assert(MO.isExpr() && "Unexpected machine operand type!");
1063 const MCExpr *Expr = MO.getExpr();
1066 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1068 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1069 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
1071 ++MCNumCPRelocations;
1073 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1074 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1077 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1078 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1081 Binary |= (Reg << 9);
1085 unsigned ARMMCCodeEmitter::
1086 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1087 SmallVectorImpl<MCFixup> &Fixups) const {
1088 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1089 // shifted. The second is Rs, the amount to shift by, and the third specifies
1090 // the type of the shift.
1098 const MCOperand &MO = MI.getOperand(OpIdx);
1099 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1100 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1101 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1104 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1106 // Encode the shift opcode.
1108 unsigned Rs = MO1.getReg();
1110 // Set shift operand (bit[7:4]).
1116 default: llvm_unreachable("Unknown shift opc!");
1117 case ARM_AM::lsl: SBits = 0x1; break;
1118 case ARM_AM::lsr: SBits = 0x3; break;
1119 case ARM_AM::asr: SBits = 0x5; break;
1120 case ARM_AM::ror: SBits = 0x7; break;
1124 Binary |= SBits << 4;
1126 // Encode the shift operation Rs.
1127 // Encode Rs bit[11:8].
1128 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1129 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1132 unsigned ARMMCCodeEmitter::
1133 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1134 SmallVectorImpl<MCFixup> &Fixups) const {
1135 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1136 // shifted. The second is the amount to shift by.
1143 const MCOperand &MO = MI.getOperand(OpIdx);
1144 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1145 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1148 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1150 // Encode the shift opcode.
1153 // Set shift operand (bit[6:4]).
1158 // RRX - 110 and bit[11:8] clear.
1160 default: llvm_unreachable("Unknown shift opc!");
1161 case ARM_AM::lsl: SBits = 0x0; break;
1162 case ARM_AM::lsr: SBits = 0x2; break;
1163 case ARM_AM::asr: SBits = 0x4; break;
1164 case ARM_AM::ror: SBits = 0x6; break;
1170 // Encode shift_imm bit[11:7].
1171 Binary |= SBits << 4;
1172 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1173 assert(Offset && "Offset must be in range 1-32!");
1174 if (Offset == 32) Offset = 0;
1175 return Binary | (Offset << 7);
1179 unsigned ARMMCCodeEmitter::
1180 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1181 SmallVectorImpl<MCFixup> &Fixups) const {
1182 const MCOperand &MO1 = MI.getOperand(OpNum);
1183 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1184 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1186 // Encoded as [Rn, Rm, imm].
1187 // FIXME: Needs fixup support.
1188 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1190 Value |= getARMRegisterNumbering(MO2.getReg());
1192 Value |= MO3.getImm();
1197 unsigned ARMMCCodeEmitter::
1198 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1199 SmallVectorImpl<MCFixup> &Fixups) const {
1200 const MCOperand &MO1 = MI.getOperand(OpNum);
1201 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1203 // FIXME: Needs fixup support.
1204 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1206 // Even though the immediate is 8 bits long, we need 9 bits in order
1207 // to represent the (inverse of the) sign bit.
1209 int32_t tmp = (int32_t)MO2.getImm();
1213 Value |= 256; // Set the ADD bit
1218 unsigned ARMMCCodeEmitter::
1219 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1220 SmallVectorImpl<MCFixup> &Fixups) const {
1221 const MCOperand &MO1 = MI.getOperand(OpNum);
1223 // FIXME: Needs fixup support.
1225 int32_t tmp = (int32_t)MO1.getImm();
1229 Value |= 256; // Set the ADD bit
1234 unsigned ARMMCCodeEmitter::
1235 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1236 SmallVectorImpl<MCFixup> &Fixups) const {
1237 const MCOperand &MO1 = MI.getOperand(OpNum);
1239 // FIXME: Needs fixup support.
1241 int32_t tmp = (int32_t)MO1.getImm();
1245 Value |= 4096; // Set the ADD bit
1246 Value |= tmp & 4095;
1250 unsigned ARMMCCodeEmitter::
1251 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1252 SmallVectorImpl<MCFixup> &Fixups) const {
1253 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1254 // shifted. The second is the amount to shift by.
1261 const MCOperand &MO = MI.getOperand(OpIdx);
1262 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1263 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1266 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1268 // Encode the shift opcode.
1270 // Set shift operand (bit[6:4]).
1276 default: llvm_unreachable("Unknown shift opc!");
1277 case ARM_AM::lsl: SBits = 0x0; break;
1278 case ARM_AM::lsr: SBits = 0x2; break;
1279 case ARM_AM::asr: SBits = 0x4; break;
1280 case ARM_AM::ror: SBits = 0x6; break;
1283 Binary |= SBits << 4;
1284 if (SOpc == ARM_AM::rrx)
1287 // Encode shift_imm bit[11:7].
1288 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1291 unsigned ARMMCCodeEmitter::
1292 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1293 SmallVectorImpl<MCFixup> &Fixups) const {
1294 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1296 const MCOperand &MO = MI.getOperand(Op);
1297 uint32_t v = ~MO.getImm();
1298 uint32_t lsb = CountTrailingZeros_32(v);
1299 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1300 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1301 return lsb | (msb << 5);
1304 unsigned ARMMCCodeEmitter::
1305 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1306 SmallVectorImpl<MCFixup> &Fixups) const {
1309 // {7-0} = Number of registers
1312 // {15-0} = Bitfield of GPRs.
1313 unsigned Reg = MI.getOperand(Op).getReg();
1314 bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1315 bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1317 unsigned Binary = 0;
1319 if (SPRRegs || DPRRegs) {
1321 unsigned RegNo = getARMRegisterNumbering(Reg);
1322 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1323 Binary |= (RegNo & 0x1f) << 8;
1327 Binary |= NumRegs * 2;
1329 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1330 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1331 Binary |= 1 << RegNo;
1338 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1339 /// with the alignment operand.
1340 unsigned ARMMCCodeEmitter::
1341 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1342 SmallVectorImpl<MCFixup> &Fixups) const {
1343 const MCOperand &Reg = MI.getOperand(Op);
1344 const MCOperand &Imm = MI.getOperand(Op + 1);
1346 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1349 switch (Imm.getImm()) {
1353 case 8: Align = 0x01; break;
1354 case 16: Align = 0x02; break;
1355 case 32: Align = 0x03; break;
1358 return RegNo | (Align << 4);
1361 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1362 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1363 unsigned ARMMCCodeEmitter::
1364 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1365 SmallVectorImpl<MCFixup> &Fixups) const {
1366 const MCOperand &Reg = MI.getOperand(Op);
1367 const MCOperand &Imm = MI.getOperand(Op + 1);
1369 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1372 switch (Imm.getImm()) {
1377 case 16: Align = 0x00; break;
1378 case 32: Align = 0x03; break;
1381 return RegNo | (Align << 4);
1385 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1386 /// alignment operand for use in VLD-dup instructions. This is the same as
1387 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1388 /// different for VLD4-dup.
1389 unsigned ARMMCCodeEmitter::
1390 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1391 SmallVectorImpl<MCFixup> &Fixups) const {
1392 const MCOperand &Reg = MI.getOperand(Op);
1393 const MCOperand &Imm = MI.getOperand(Op + 1);
1395 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1398 switch (Imm.getImm()) {
1402 case 8: Align = 0x01; break;
1403 case 16: Align = 0x03; break;
1406 return RegNo | (Align << 4);
1409 unsigned ARMMCCodeEmitter::
1410 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1411 SmallVectorImpl<MCFixup> &Fixups) const {
1412 const MCOperand &MO = MI.getOperand(Op);
1413 if (MO.getReg() == 0) return 0x0D;
1417 unsigned ARMMCCodeEmitter::
1418 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1419 SmallVectorImpl<MCFixup> &Fixups) const {
1420 return 8 - MI.getOperand(Op).getImm();
1423 unsigned ARMMCCodeEmitter::
1424 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1425 SmallVectorImpl<MCFixup> &Fixups) const {
1426 return 16 - MI.getOperand(Op).getImm();
1429 unsigned ARMMCCodeEmitter::
1430 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1431 SmallVectorImpl<MCFixup> &Fixups) const {
1432 return 32 - MI.getOperand(Op).getImm();
1435 unsigned ARMMCCodeEmitter::
1436 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1437 SmallVectorImpl<MCFixup> &Fixups) const {
1438 return 64 - MI.getOperand(Op).getImm();
1441 void ARMMCCodeEmitter::
1442 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1443 SmallVectorImpl<MCFixup> &Fixups) const {
1444 // Pseudo instructions don't get encoded.
1445 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1446 uint64_t TSFlags = Desc.TSFlags;
1447 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1451 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1452 Size = Desc.getSize();
1454 llvm_unreachable("Unexpected instruction size!");
1456 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1457 // Thumb 32-bit wide instructions need to emit the high order halfword
1459 if (isThumb() && Size == 4) {
1460 EmitConstant(Binary >> 16, 2, OS);
1461 EmitConstant(Binary & 0xffff, 2, OS);
1463 EmitConstant(Binary, Size, OS);
1464 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1467 #include "ARMGenMCCodeEmitter.inc"