1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/raw_ostream.h"
32 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
36 class ARMMCCodeEmitter : public MCCodeEmitter {
37 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39 const MCInstrInfo &MCII;
40 const MCSubtargetInfo &STI;
43 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
45 : MCII(mcii), STI(sti) {
48 ~ARMMCCodeEmitter() {}
50 bool isThumb() const {
51 // FIXME: Can tablegen auto-generate this?
52 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
54 bool isThumb2() const {
55 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
57 bool isTargetDarwin() const {
58 Triple TT(STI.getTargetTriple());
59 Triple::OSType OS = TT.getOS();
60 return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
63 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
65 // getBinaryCodeForInstr - TableGen'erated function for getting the
66 // binary encoding for an instruction.
67 unsigned getBinaryCodeForInstr(const MCInst &MI,
68 SmallVectorImpl<MCFixup> &Fixups) const;
70 /// getMachineOpValue - Return binary encoding of operand. If the machine
71 /// operand requires relocation, record the relocation and return zero.
72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73 SmallVectorImpl<MCFixup> &Fixups) const;
75 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76 /// the specified operand. This is used for operands with :lower16: and
77 /// :upper16: prefixes.
78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82 unsigned &Reg, unsigned &Imm,
83 SmallVectorImpl<MCFixup> &Fixups) const;
85 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88 SmallVectorImpl<MCFixup> &Fixups) const;
90 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91 /// BLX branch target.
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups) const;
95 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97 SmallVectorImpl<MCFixup> &Fixups) const;
99 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101 SmallVectorImpl<MCFixup> &Fixups) const;
103 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113 /// immediate Thumb2 direct branch target.
114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups) const;
122 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
123 /// ADR label target.
124 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
125 SmallVectorImpl<MCFixup> &Fixups) const;
126 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
127 SmallVectorImpl<MCFixup> &Fixups) const;
128 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
132 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
134 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups) const;
137 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
138 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
139 SmallVectorImpl<MCFixup> &Fixups)const;
141 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
143 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups) const;
147 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
148 /// operand as needed by load/store instructions.
149 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups) const;
152 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
153 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
154 SmallVectorImpl<MCFixup> &Fixups) const {
155 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
157 default: assert(0 && "Unknown addressing sub-mode!");
158 case ARM_AM::da: return 0;
159 case ARM_AM::ia: return 1;
160 case ARM_AM::db: return 2;
161 case ARM_AM::ib: return 3;
164 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
166 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
168 default: llvm_unreachable("Unknown shift opc!");
169 case ARM_AM::no_shift:
170 case ARM_AM::lsl: return 0;
171 case ARM_AM::lsr: return 1;
172 case ARM_AM::asr: return 2;
174 case ARM_AM::rrx: return 3;
179 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
180 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
181 SmallVectorImpl<MCFixup> &Fixups) const;
183 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
184 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
185 SmallVectorImpl<MCFixup> &Fixups) const;
187 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
188 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
189 SmallVectorImpl<MCFixup> &Fixups) const;
191 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
192 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
193 SmallVectorImpl<MCFixup> &Fixups) const;
195 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
197 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
198 SmallVectorImpl<MCFixup> &Fixups) const;
200 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
201 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
202 SmallVectorImpl<MCFixup> &Fixups) const;
204 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
205 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
206 SmallVectorImpl<MCFixup> &Fixups) const;
208 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
209 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
210 SmallVectorImpl<MCFixup> &Fixups) const;
212 /// getCCOutOpValue - Return encoding of the 's' bit.
213 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
214 SmallVectorImpl<MCFixup> &Fixups) const {
215 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
217 return MI.getOperand(Op).getReg() == ARM::CPSR;
220 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
221 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
222 SmallVectorImpl<MCFixup> &Fixups) const {
223 unsigned SoImm = MI.getOperand(Op).getImm();
224 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
225 assert(SoImmVal != -1 && "Not a valid so_imm value!");
227 // Encode rotate_imm.
228 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
229 << ARMII::SoRotImmShift;
232 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
236 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
237 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
238 SmallVectorImpl<MCFixup> &Fixups) const {
239 unsigned SoImm = MI.getOperand(Op).getImm();
240 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
241 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
245 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
246 SmallVectorImpl<MCFixup> &Fixups) const;
247 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
248 SmallVectorImpl<MCFixup> &Fixups) const;
249 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
250 SmallVectorImpl<MCFixup> &Fixups) const;
251 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
252 SmallVectorImpl<MCFixup> &Fixups) const;
254 /// getSORegOpValue - Return an encoded so_reg shifted register value.
255 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
256 SmallVectorImpl<MCFixup> &Fixups) const;
257 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
258 SmallVectorImpl<MCFixup> &Fixups) const;
259 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
260 SmallVectorImpl<MCFixup> &Fixups) const;
262 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
263 SmallVectorImpl<MCFixup> &Fixups) const {
264 return 64 - MI.getOperand(Op).getImm();
267 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
268 SmallVectorImpl<MCFixup> &Fixups) const;
270 unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
271 SmallVectorImpl<MCFixup> &Fixups) const;
273 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
274 SmallVectorImpl<MCFixup> &Fixups) const;
275 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
276 SmallVectorImpl<MCFixup> &Fixups) const;
277 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
278 SmallVectorImpl<MCFixup> &Fixups) const;
279 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
280 SmallVectorImpl<MCFixup> &Fixups) const;
281 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
282 SmallVectorImpl<MCFixup> &Fixups) const;
284 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
285 SmallVectorImpl<MCFixup> &Fixups) const;
286 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
287 SmallVectorImpl<MCFixup> &Fixups) const;
288 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
289 SmallVectorImpl<MCFixup> &Fixups) const;
290 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
291 SmallVectorImpl<MCFixup> &Fixups) const;
293 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
294 unsigned EncodedValue) const;
295 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
296 unsigned EncodedValue) const;
297 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
298 unsigned EncodedValue) const;
300 unsigned VFPThumb2PostEncoder(const MCInst &MI,
301 unsigned EncodedValue) const;
303 void EmitByte(unsigned char C, raw_ostream &OS) const {
307 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
308 // Output the constant in little endian byte order.
309 for (unsigned i = 0; i != Size; ++i) {
310 EmitByte(Val & 255, OS);
315 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
316 SmallVectorImpl<MCFixup> &Fixups) const;
319 } // end anonymous namespace
321 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
322 const MCSubtargetInfo &STI,
324 return new ARMMCCodeEmitter(MCII, STI, Ctx);
327 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
328 /// instructions, and rewrite them to their Thumb2 form if we are currently in
330 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
331 unsigned EncodedValue) const {
333 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
334 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
336 unsigned Bit24 = EncodedValue & 0x01000000;
337 unsigned Bit28 = Bit24 << 4;
338 EncodedValue &= 0xEFFFFFFF;
339 EncodedValue |= Bit28;
340 EncodedValue |= 0x0F000000;
346 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
347 /// instructions, and rewrite them to their Thumb2 form if we are currently in
349 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
350 unsigned EncodedValue) const {
352 EncodedValue &= 0xF0FFFFFF;
353 EncodedValue |= 0x09000000;
359 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
360 /// instructions, and rewrite them to their Thumb2 form if we are currently in
362 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
363 unsigned EncodedValue) const {
365 EncodedValue &= 0x00FFFFFF;
366 EncodedValue |= 0xEE000000;
372 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
373 /// them to their Thumb2 form if we are currently in Thumb2 mode.
374 unsigned ARMMCCodeEmitter::
375 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
377 EncodedValue &= 0x0FFFFFFF;
378 EncodedValue |= 0xE0000000;
383 /// getMachineOpValue - Return binary encoding of operand. If the machine
384 /// operand requires relocation, record the relocation and return zero.
385 unsigned ARMMCCodeEmitter::
386 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
387 SmallVectorImpl<MCFixup> &Fixups) const {
389 unsigned Reg = MO.getReg();
390 unsigned RegNo = getARMRegisterNumbering(Reg);
392 // Q registers are encoded as 2x their register number.
396 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
397 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
398 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
399 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
402 } else if (MO.isImm()) {
403 return static_cast<unsigned>(MO.getImm());
404 } else if (MO.isFPImm()) {
405 return static_cast<unsigned>(APFloat(MO.getFPImm())
406 .bitcastToAPInt().getHiBits(32).getLimitedValue());
409 llvm_unreachable("Unable to encode MCOperand!");
413 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
414 bool ARMMCCodeEmitter::
415 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
416 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
417 const MCOperand &MO = MI.getOperand(OpIdx);
418 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
420 Reg = getARMRegisterNumbering(MO.getReg());
422 int32_t SImm = MO1.getImm();
425 // Special value for #-0
426 if (SImm == INT32_MIN)
429 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
439 /// getBranchTargetOpValue - Helper function to get the branch target operand,
440 /// which is either an immediate or requires a fixup.
441 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
443 SmallVectorImpl<MCFixup> &Fixups) {
444 const MCOperand &MO = MI.getOperand(OpIdx);
446 // If the destination is an immediate, we have nothing to do.
447 if (MO.isImm()) return MO.getImm();
448 assert(MO.isExpr() && "Unexpected branch target type!");
449 const MCExpr *Expr = MO.getExpr();
450 MCFixupKind Kind = MCFixupKind(FixupKind);
451 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
453 // All of the information is in the fixup.
457 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
458 uint32_t ARMMCCodeEmitter::
459 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
460 SmallVectorImpl<MCFixup> &Fixups) const {
461 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
464 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
465 /// BLX branch target.
466 uint32_t ARMMCCodeEmitter::
467 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
468 SmallVectorImpl<MCFixup> &Fixups) const {
469 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
472 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
473 uint32_t ARMMCCodeEmitter::
474 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
475 SmallVectorImpl<MCFixup> &Fixups) const {
476 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
479 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
480 uint32_t ARMMCCodeEmitter::
481 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
482 SmallVectorImpl<MCFixup> &Fixups) const {
483 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
486 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
487 uint32_t ARMMCCodeEmitter::
488 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
489 SmallVectorImpl<MCFixup> &Fixups) const {
490 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
493 /// Return true if this branch has a non-always predication
494 static bool HasConditionalBranch(const MCInst &MI) {
495 int NumOp = MI.getNumOperands();
497 for (int i = 0; i < NumOp-1; ++i) {
498 const MCOperand &MCOp1 = MI.getOperand(i);
499 const MCOperand &MCOp2 = MI.getOperand(i + 1);
500 if (MCOp1.isImm() && MCOp2.isReg() &&
501 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
502 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
510 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
512 uint32_t ARMMCCodeEmitter::
513 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
514 SmallVectorImpl<MCFixup> &Fixups) const {
515 // FIXME: This really, really shouldn't use TargetMachine. We don't want
516 // coupling between MC and TM anywhere we can help it.
519 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
520 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
523 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
525 uint32_t ARMMCCodeEmitter::
526 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
527 SmallVectorImpl<MCFixup> &Fixups) const {
528 if (HasConditionalBranch(MI))
529 return ::getBranchTargetOpValue(MI, OpIdx,
530 ARM::fixup_arm_condbranch, Fixups);
531 return ::getBranchTargetOpValue(MI, OpIdx,
532 ARM::fixup_arm_uncondbranch, Fixups);
538 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
539 /// immediate branch target.
540 uint32_t ARMMCCodeEmitter::
541 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
542 SmallVectorImpl<MCFixup> &Fixups) const {
544 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
545 bool I = (Val & 0x800000);
546 bool J1 = (Val & 0x400000);
547 bool J2 = (Val & 0x200000);
561 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
563 uint32_t ARMMCCodeEmitter::
564 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
565 SmallVectorImpl<MCFixup> &Fixups) const {
566 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
567 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
571 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
573 uint32_t ARMMCCodeEmitter::
574 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
575 SmallVectorImpl<MCFixup> &Fixups) const {
576 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
577 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
581 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
583 uint32_t ARMMCCodeEmitter::
584 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
585 SmallVectorImpl<MCFixup> &Fixups) const {
586 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
587 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
591 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
593 uint32_t ARMMCCodeEmitter::
594 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
595 SmallVectorImpl<MCFixup> &) const {
599 const MCOperand &MO1 = MI.getOperand(OpIdx);
600 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
601 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
602 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
603 return (Rm << 3) | Rn;
606 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
607 uint32_t ARMMCCodeEmitter::
608 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
609 SmallVectorImpl<MCFixup> &Fixups) const {
611 // {12} = (U)nsigned (add == '1', sub == '0')
615 // If The first operand isn't a register, we have a label reference.
616 const MCOperand &MO = MI.getOperand(OpIdx);
618 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
620 isAdd = false ; // 'U' bit is set as part of the fixup.
622 assert(MO.isExpr() && "Unexpected machine operand type!");
623 const MCExpr *Expr = MO.getExpr();
627 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
629 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
630 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
632 ++MCNumCPRelocations;
634 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
636 uint32_t Binary = Imm12 & 0xfff;
637 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
640 Binary |= (Reg << 13);
644 /// getT2AddrModeImm8s4OpValue - Return encoding info for
645 /// 'reg +/- imm8<<2' operand.
646 uint32_t ARMMCCodeEmitter::
647 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
648 SmallVectorImpl<MCFixup> &Fixups) const {
650 // {8} = (U)nsigned (add == '1', sub == '0')
654 // If The first operand isn't a register, we have a label reference.
655 const MCOperand &MO = MI.getOperand(OpIdx);
657 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
659 isAdd = false ; // 'U' bit is set as part of the fixup.
661 assert(MO.isExpr() && "Unexpected machine operand type!");
662 const MCExpr *Expr = MO.getExpr();
663 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
664 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
666 ++MCNumCPRelocations;
668 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
670 uint32_t Binary = (Imm8 >> 2) & 0xff;
671 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
674 Binary |= (Reg << 9);
678 // FIXME: This routine assumes that a binary
679 // expression will always result in a PCRel expression
680 // In reality, its only true if one or more subexpressions
681 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
682 // but this is good enough for now.
683 static bool EvaluateAsPCRel(const MCExpr *Expr) {
684 switch (Expr->getKind()) {
685 default: assert(0 && "Unexpected expression type");
686 case MCExpr::SymbolRef: return false;
687 case MCExpr::Binary: return true;
692 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
693 SmallVectorImpl<MCFixup> &Fixups) const {
694 // {20-16} = imm{15-12}
695 // {11-0} = imm{11-0}
696 const MCOperand &MO = MI.getOperand(OpIdx);
698 // Hi / lo 16 bits already extracted during earlier passes.
699 return static_cast<unsigned>(MO.getImm());
701 // Handle :upper16: and :lower16: assembly prefixes.
702 const MCExpr *E = MO.getExpr();
703 if (E->getKind() == MCExpr::Target) {
704 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
705 E = ARM16Expr->getSubExpr();
708 switch (ARM16Expr->getKind()) {
709 default: assert(0 && "Unsupported ARMFixup");
710 case ARMMCExpr::VK_ARM_HI16:
711 if (!isTargetDarwin() && EvaluateAsPCRel(E))
712 Kind = MCFixupKind(isThumb2()
713 ? ARM::fixup_t2_movt_hi16_pcrel
714 : ARM::fixup_arm_movt_hi16_pcrel);
716 Kind = MCFixupKind(isThumb2()
717 ? ARM::fixup_t2_movt_hi16
718 : ARM::fixup_arm_movt_hi16);
720 case ARMMCExpr::VK_ARM_LO16:
721 if (!isTargetDarwin() && EvaluateAsPCRel(E))
722 Kind = MCFixupKind(isThumb2()
723 ? ARM::fixup_t2_movw_lo16_pcrel
724 : ARM::fixup_arm_movw_lo16_pcrel);
726 Kind = MCFixupKind(isThumb2()
727 ? ARM::fixup_t2_movw_lo16
728 : ARM::fixup_arm_movw_lo16);
731 Fixups.push_back(MCFixup::Create(0, E, Kind));
735 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
739 uint32_t ARMMCCodeEmitter::
740 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
741 SmallVectorImpl<MCFixup> &Fixups) const {
742 const MCOperand &MO = MI.getOperand(OpIdx);
743 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
744 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
745 unsigned Rn = getARMRegisterNumbering(MO.getReg());
746 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
747 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
748 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
749 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
750 unsigned SBits = getShiftOp(ShOp);
759 uint32_t Binary = Rm;
761 Binary |= SBits << 5;
762 Binary |= ShImm << 7;
768 uint32_t ARMMCCodeEmitter::
769 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
770 SmallVectorImpl<MCFixup> &Fixups) const {
772 // {13} 1 == imm12, 0 == Rm
775 const MCOperand &MO = MI.getOperand(OpIdx);
776 unsigned Rn = getARMRegisterNumbering(MO.getReg());
777 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
782 uint32_t ARMMCCodeEmitter::
783 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
784 SmallVectorImpl<MCFixup> &Fixups) const {
785 // {13} 1 == imm12, 0 == Rm
788 const MCOperand &MO = MI.getOperand(OpIdx);
789 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
790 unsigned Imm = MO1.getImm();
791 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
792 bool isReg = MO.getReg() != 0;
793 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
794 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
796 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
797 Binary <<= 7; // Shift amount is bits [11:7]
798 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
799 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
801 return Binary | (isAdd << 12) | (isReg << 13);
804 uint32_t ARMMCCodeEmitter::
805 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
806 SmallVectorImpl<MCFixup> &Fixups) const {
807 // {9} 1 == imm8, 0 == Rm
811 const MCOperand &MO = MI.getOperand(OpIdx);
812 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
813 unsigned Imm = MO1.getImm();
814 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
815 bool isImm = MO.getReg() == 0;
816 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
817 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
819 Imm8 = getARMRegisterNumbering(MO.getReg());
820 return Imm8 | (isAdd << 8) | (isImm << 9);
823 uint32_t ARMMCCodeEmitter::
824 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
825 SmallVectorImpl<MCFixup> &Fixups) const {
826 // {13} 1 == imm8, 0 == Rm
831 const MCOperand &MO = MI.getOperand(OpIdx);
832 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
833 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
834 unsigned Rn = getARMRegisterNumbering(MO.getReg());
835 unsigned Imm = MO2.getImm();
836 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
837 bool isImm = MO1.getReg() == 0;
838 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
839 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
841 Imm8 = getARMRegisterNumbering(MO1.getReg());
842 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
845 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
846 uint32_t ARMMCCodeEmitter::
847 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
848 SmallVectorImpl<MCFixup> &Fixups) const {
851 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
852 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
853 "Unexpected base register!");
855 // The immediate is already shifted for the implicit zeroes, so no change
857 return MO1.getImm() & 0xff;
860 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
861 uint32_t ARMMCCodeEmitter::
862 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
863 SmallVectorImpl<MCFixup> &Fixups) const {
867 const MCOperand &MO = MI.getOperand(OpIdx);
868 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
869 unsigned Rn = getARMRegisterNumbering(MO.getReg());
870 unsigned Imm5 = MO1.getImm();
871 return ((Imm5 & 0x1f) << 3) | Rn;
874 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
875 uint32_t ARMMCCodeEmitter::
876 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
877 SmallVectorImpl<MCFixup> &Fixups) const {
878 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
881 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
882 uint32_t ARMMCCodeEmitter::
883 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
884 SmallVectorImpl<MCFixup> &Fixups) const {
886 // {8} = (U)nsigned (add == '1', sub == '0')
890 // If The first operand isn't a register, we have a label reference.
891 const MCOperand &MO = MI.getOperand(OpIdx);
893 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
895 isAdd = false; // 'U' bit is handled as part of the fixup.
897 assert(MO.isExpr() && "Unexpected machine operand type!");
898 const MCExpr *Expr = MO.getExpr();
901 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
903 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
904 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
906 ++MCNumCPRelocations;
908 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
909 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
912 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
913 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
916 Binary |= (Reg << 9);
920 unsigned ARMMCCodeEmitter::
921 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
922 SmallVectorImpl<MCFixup> &Fixups) const {
923 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
924 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
925 // case the imm contains the amount to shift by.
928 // {4} = 1 if reg shift, 0 if imm shift
936 const MCOperand &MO = MI.getOperand(OpIdx);
937 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
938 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
939 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
942 unsigned Binary = getARMRegisterNumbering(MO.getReg());
944 // Encode the shift opcode.
946 unsigned Rs = MO1.getReg();
948 // Set shift operand (bit[7:4]).
954 default: llvm_unreachable("Unknown shift opc!");
955 case ARM_AM::lsl: SBits = 0x1; break;
956 case ARM_AM::lsr: SBits = 0x3; break;
957 case ARM_AM::asr: SBits = 0x5; break;
958 case ARM_AM::ror: SBits = 0x7; break;
962 Binary |= SBits << 4;
964 // Encode the shift operation Rs or shift_imm (except rrx).
965 // Encode Rs bit[11:8].
966 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
967 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
970 unsigned ARMMCCodeEmitter::
971 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
972 SmallVectorImpl<MCFixup> &Fixups) const {
973 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
974 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
975 // case the imm contains the amount to shift by.
978 // {4} = 1 if reg shift, 0 if imm shift
986 const MCOperand &MO = MI.getOperand(OpIdx);
987 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
988 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
991 unsigned Binary = getARMRegisterNumbering(MO.getReg());
993 // Encode the shift opcode.
996 // Set shift operand (bit[6:4]).
1001 // RRX - 110 and bit[11:8] clear.
1003 default: llvm_unreachable("Unknown shift opc!");
1004 case ARM_AM::lsl: SBits = 0x0; break;
1005 case ARM_AM::lsr: SBits = 0x2; break;
1006 case ARM_AM::asr: SBits = 0x4; break;
1007 case ARM_AM::ror: SBits = 0x6; break;
1013 // Encode shift_imm bit[11:7].
1014 Binary |= SBits << 4;
1015 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1019 unsigned ARMMCCodeEmitter::
1020 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1021 SmallVectorImpl<MCFixup> &Fixups) const {
1022 const MCOperand &MO1 = MI.getOperand(OpNum);
1023 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1024 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1026 // Encoded as [Rn, Rm, imm].
1027 // FIXME: Needs fixup support.
1028 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1030 Value |= getARMRegisterNumbering(MO2.getReg());
1032 Value |= MO3.getImm();
1037 unsigned ARMMCCodeEmitter::
1038 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1039 SmallVectorImpl<MCFixup> &Fixups) const {
1040 const MCOperand &MO1 = MI.getOperand(OpNum);
1041 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1043 // FIXME: Needs fixup support.
1044 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1046 // Even though the immediate is 8 bits long, we need 9 bits in order
1047 // to represent the (inverse of the) sign bit.
1049 int32_t tmp = (int32_t)MO2.getImm();
1053 Value |= 256; // Set the ADD bit
1058 unsigned ARMMCCodeEmitter::
1059 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1060 SmallVectorImpl<MCFixup> &Fixups) const {
1061 const MCOperand &MO1 = MI.getOperand(OpNum);
1063 // FIXME: Needs fixup support.
1065 int32_t tmp = (int32_t)MO1.getImm();
1069 Value |= 256; // Set the ADD bit
1074 unsigned ARMMCCodeEmitter::
1075 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1076 SmallVectorImpl<MCFixup> &Fixups) const {
1077 const MCOperand &MO1 = MI.getOperand(OpNum);
1079 // FIXME: Needs fixup support.
1081 int32_t tmp = (int32_t)MO1.getImm();
1085 Value |= 4096; // Set the ADD bit
1086 Value |= tmp & 4095;
1090 unsigned ARMMCCodeEmitter::
1091 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1092 SmallVectorImpl<MCFixup> &Fixups) const {
1093 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1094 // shifted. The second is the amount to shift by.
1101 const MCOperand &MO = MI.getOperand(OpIdx);
1102 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1103 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1106 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1108 // Encode the shift opcode.
1110 // Set shift operand (bit[6:4]).
1116 default: llvm_unreachable("Unknown shift opc!");
1117 case ARM_AM::lsl: SBits = 0x0; break;
1118 case ARM_AM::lsr: SBits = 0x2; break;
1119 case ARM_AM::asr: SBits = 0x4; break;
1120 case ARM_AM::ror: SBits = 0x6; break;
1123 Binary |= SBits << 4;
1124 if (SOpc == ARM_AM::rrx)
1127 // Encode shift_imm bit[11:7].
1128 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1131 unsigned ARMMCCodeEmitter::
1132 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1133 SmallVectorImpl<MCFixup> &Fixups) const {
1134 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1136 const MCOperand &MO = MI.getOperand(Op);
1137 uint32_t v = ~MO.getImm();
1138 uint32_t lsb = CountTrailingZeros_32(v);
1139 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1140 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1141 return lsb | (msb << 5);
1144 unsigned ARMMCCodeEmitter::
1145 getMsbOpValue(const MCInst &MI, unsigned Op,
1146 SmallVectorImpl<MCFixup> &Fixups) const {
1148 uint32_t lsb = MI.getOperand(Op-1).getImm();
1149 uint32_t width = MI.getOperand(Op).getImm();
1150 uint32_t msb = lsb+width-1;
1151 assert (width != 0 && msb < 32 && "Illegal bit width!");
1155 unsigned ARMMCCodeEmitter::
1156 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1157 SmallVectorImpl<MCFixup> &Fixups) const {
1160 // {7-0} = Number of registers
1163 // {15-0} = Bitfield of GPRs.
1164 unsigned Reg = MI.getOperand(Op).getReg();
1165 bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1166 bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1168 unsigned Binary = 0;
1170 if (SPRRegs || DPRRegs) {
1172 unsigned RegNo = getARMRegisterNumbering(Reg);
1173 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1174 Binary |= (RegNo & 0x1f) << 8;
1178 Binary |= NumRegs * 2;
1180 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1181 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1182 Binary |= 1 << RegNo;
1189 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1190 /// with the alignment operand.
1191 unsigned ARMMCCodeEmitter::
1192 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1193 SmallVectorImpl<MCFixup> &Fixups) const {
1194 const MCOperand &Reg = MI.getOperand(Op);
1195 const MCOperand &Imm = MI.getOperand(Op + 1);
1197 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1200 switch (Imm.getImm()) {
1204 case 8: Align = 0x01; break;
1205 case 16: Align = 0x02; break;
1206 case 32: Align = 0x03; break;
1209 return RegNo | (Align << 4);
1212 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1213 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1214 unsigned ARMMCCodeEmitter::
1215 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1216 SmallVectorImpl<MCFixup> &Fixups) const {
1217 const MCOperand &Reg = MI.getOperand(Op);
1218 const MCOperand &Imm = MI.getOperand(Op + 1);
1220 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1223 switch (Imm.getImm()) {
1228 case 16: Align = 0x00; break;
1229 case 32: Align = 0x03; break;
1232 return RegNo | (Align << 4);
1236 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1237 /// alignment operand for use in VLD-dup instructions. This is the same as
1238 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1239 /// different for VLD4-dup.
1240 unsigned ARMMCCodeEmitter::
1241 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1242 SmallVectorImpl<MCFixup> &Fixups) const {
1243 const MCOperand &Reg = MI.getOperand(Op);
1244 const MCOperand &Imm = MI.getOperand(Op + 1);
1246 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1249 switch (Imm.getImm()) {
1253 case 8: Align = 0x01; break;
1254 case 16: Align = 0x03; break;
1257 return RegNo | (Align << 4);
1260 unsigned ARMMCCodeEmitter::
1261 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1262 SmallVectorImpl<MCFixup> &Fixups) const {
1263 const MCOperand &MO = MI.getOperand(Op);
1264 if (MO.getReg() == 0) return 0x0D;
1268 unsigned ARMMCCodeEmitter::
1269 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1270 SmallVectorImpl<MCFixup> &Fixups) const {
1271 return 8 - MI.getOperand(Op).getImm();
1274 unsigned ARMMCCodeEmitter::
1275 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1276 SmallVectorImpl<MCFixup> &Fixups) const {
1277 return 16 - MI.getOperand(Op).getImm();
1280 unsigned ARMMCCodeEmitter::
1281 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1282 SmallVectorImpl<MCFixup> &Fixups) const {
1283 return 32 - MI.getOperand(Op).getImm();
1286 unsigned ARMMCCodeEmitter::
1287 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1288 SmallVectorImpl<MCFixup> &Fixups) const {
1289 return 64 - MI.getOperand(Op).getImm();
1292 void ARMMCCodeEmitter::
1293 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1294 SmallVectorImpl<MCFixup> &Fixups) const {
1295 // Pseudo instructions don't get encoded.
1296 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1297 uint64_t TSFlags = Desc.TSFlags;
1298 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1302 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1303 Size = Desc.getSize();
1305 llvm_unreachable("Unexpected instruction size!");
1307 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1308 // Thumb 32-bit wide instructions need to emit the high order halfword
1310 if (isThumb() && Size == 4) {
1311 EmitConstant(Binary >> 16, 2, OS);
1312 EmitConstant(Binary & 0xffff, 2, OS);
1314 EmitConstant(Binary, Size, OS);
1315 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1318 #include "ARMGenMCCodeEmitter.inc"