1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMFixupKinds.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCDirectives.h"
17 #include "llvm/MC/MCELFObjectWriter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCFixupKindInfo.h"
20 #include "llvm/MC/MCMachObjectWriter.h"
21 #include "llvm/MC/MCObjectWriter.h"
22 #include "llvm/MC/MCSectionELF.h"
23 #include "llvm/MC/MCSectionMachO.h"
24 #include "llvm/MC/MCAsmBackend.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCValue.h"
27 #include "llvm/Object/MachOFormat.h"
28 #include "llvm/Support/ELF.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
34 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
36 ARMELFObjectWriter(uint8_t OSABI)
37 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
38 /*HasRelocationAddend*/ false) {}
41 class ARMAsmBackend : public MCAsmBackend {
42 const MCSubtargetInfo* STI;
43 bool isThumbMode; // Currently emitting Thumb code.
45 ARMAsmBackend(const Target &T, const StringRef TT)
46 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
47 isThumbMode(TT.startswith("thumb")) {}
53 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
56 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
59 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
60 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
61 // This table *must* be in the order that the fixup_* kinds are defined in
64 // Name Offset (bits) Size (bits) Flags
65 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
66 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
67 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
68 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
69 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
70 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
71 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
72 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
73 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
74 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
75 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
76 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
77 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_bl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
84 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
85 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
86 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
87 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
88 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
89 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
90 { "fixup_arm_movt_hi16", 0, 20, 0 },
91 { "fixup_arm_movw_lo16", 0, 20, 0 },
92 { "fixup_t2_movt_hi16", 0, 20, 0 },
93 { "fixup_t2_movw_lo16", 0, 20, 0 },
94 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
95 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
96 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
97 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
100 if (Kind < FirstTargetFixupKind)
101 return MCAsmBackend::getFixupKindInfo(Kind);
103 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
105 return Infos[Kind - FirstTargetFixupKind];
108 /// processFixupValue - Target hook to process the literal value of a fixup
110 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
111 const MCFixup &Fixup, const MCFragment *DF,
112 MCValue &Target, uint64_t &Value,
114 const MCSymbolRefExpr *A = Target.getSymA();
115 // Some fixups to thumb function symbols need the low bit (thumb bit)
117 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
118 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
119 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
121 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
122 if (Asm.isThumbFunc(&Sym))
126 // We must always generate a relocation for BL/BLX instructions if we have
127 // a symbol to reference, as the linker relies on knowing the destination
128 // symbol's thumb-ness to get interworking right.
129 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
130 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||
131 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
132 (unsigned)Fixup.getKind() == ARM::fixup_arm_bl))
136 bool mayNeedRelaxation(const MCInst &Inst) const;
138 bool fixupNeedsRelaxation(const MCFixup &Fixup,
140 const MCInstFragment *DF,
141 const MCAsmLayout &Layout) const;
143 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
145 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
147 void handleAssemblerFlag(MCAssemblerFlag Flag) {
159 unsigned getPointerSize() const { return 4; }
160 bool isThumb() const { return isThumbMode; }
161 void setIsThumb(bool it) { isThumbMode = it; }
163 } // end anonymous namespace
165 static unsigned getRelaxedOpcode(unsigned Op) {
168 case ARM::tBcc: return ARM::t2Bcc;
169 case ARM::tLDRpciASM: return ARM::t2LDRpci;
170 case ARM::tADR: return ARM::t2ADR;
171 case ARM::tB: return ARM::t2B;
175 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
176 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
181 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
183 const MCInstFragment *DF,
184 const MCAsmLayout &Layout) const {
185 switch ((unsigned)Fixup.getKind()) {
186 case ARM::fixup_arm_thumb_br: {
187 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
188 // low bit being an implied zero. There's an implied +4 offset for the
189 // branch, so we adjust the other way here to determine what's
192 // Relax if the value is too big for a (signed) i8.
193 int64_t Offset = int64_t(Value) - 4;
194 return Offset > 2046 || Offset < -2048;
196 case ARM::fixup_arm_thumb_bcc: {
197 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
198 // low bit being an implied zero. There's an implied +4 offset for the
199 // branch, so we adjust the other way here to determine what's
202 // Relax if the value is too big for a (signed) i8.
203 int64_t Offset = int64_t(Value) - 4;
204 return Offset > 254 || Offset < -256;
206 case ARM::fixup_thumb_adr_pcrel_10:
207 case ARM::fixup_arm_thumb_cp: {
208 // If the immediate is negative, greater than 1020, or not a multiple
209 // of four, the wide version of the instruction must be used.
210 int64_t Offset = int64_t(Value) - 4;
211 return Offset > 1020 || Offset < 0 || Offset & 3;
214 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
217 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
218 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
220 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
221 if (RelaxedOp == Inst.getOpcode()) {
222 SmallString<256> Tmp;
223 raw_svector_ostream OS(Tmp);
224 Inst.dump_pretty(OS);
226 report_fatal_error("unexpected instruction to relax: " + OS.str());
229 // The instructions we're relaxing have (so far) the same operands.
230 // We just need to update to the proper opcode.
232 Res.setOpcode(RelaxedOp);
235 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
236 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
237 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
238 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
239 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
241 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
242 : Thumb1_16bitNopEncoding;
243 uint64_t NumNops = Count / 2;
244 for (uint64_t i = 0; i != NumNops; ++i)
245 OW->Write16(nopEncoding);
251 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
253 uint64_t NumNops = Count / 4;
254 for (uint64_t i = 0; i != NumNops; ++i)
255 OW->Write32(nopEncoding);
256 // FIXME: should this function return false when unable to write exactly
257 // 'Count' bytes with NOP encodings?
259 default: break; // No leftover bytes to write
260 case 1: OW->Write8(0); break;
261 case 2: OW->Write16(0); break;
262 case 3: OW->Write16(0); OW->Write8(0xa0); break;
268 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
271 llvm_unreachable("Unknown fixup kind!");
276 case ARM::fixup_arm_movt_hi16:
279 case ARM::fixup_arm_movw_lo16:
280 case ARM::fixup_arm_movt_hi16_pcrel:
281 case ARM::fixup_arm_movw_lo16_pcrel: {
282 unsigned Hi4 = (Value & 0xF000) >> 12;
283 unsigned Lo12 = Value & 0x0FFF;
284 // inst{19-16} = Hi4;
285 // inst{11-0} = Lo12;
286 Value = (Hi4 << 16) | (Lo12);
289 case ARM::fixup_t2_movt_hi16:
292 case ARM::fixup_t2_movw_lo16:
293 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
294 // the other hi16 fixup?
295 case ARM::fixup_t2_movw_lo16_pcrel: {
296 unsigned Hi4 = (Value & 0xF000) >> 12;
297 unsigned i = (Value & 0x800) >> 11;
298 unsigned Mid3 = (Value & 0x700) >> 8;
299 unsigned Lo8 = Value & 0x0FF;
300 // inst{19-16} = Hi4;
302 // inst{14-12} = Mid3;
304 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
305 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
306 swapped |= (Value & 0x0000FFFF) << 16;
309 case ARM::fixup_arm_ldst_pcrel_12:
310 // ARM PC-relative values are offset by 8.
313 case ARM::fixup_t2_ldst_pcrel_12: {
314 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
317 if ((int64_t)Value < 0) {
321 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
322 Value |= isAdd << 23;
324 // Same addressing mode as fixup_arm_pcrel_10,
325 // but with 16-bit halfwords swapped.
326 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
327 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
328 swapped |= (Value & 0x0000FFFF) << 16;
334 case ARM::fixup_thumb_adr_pcrel_10:
335 return ((Value - 4) >> 2) & 0xff;
336 case ARM::fixup_arm_adr_pcrel_12: {
337 // ARM PC-relative values are offset by 8.
339 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
340 if ((int64_t)Value < 0) {
344 assert(ARM_AM::getSOImmVal(Value) != -1 &&
345 "Out of range pc-relative fixup value!");
346 // Encode the immediate and shift the opcode into place.
347 return ARM_AM::getSOImmVal(Value) | (opc << 21);
350 case ARM::fixup_t2_adr_pcrel_12: {
353 if ((int64_t)Value < 0) {
358 uint32_t out = (opc << 21);
359 out |= (Value & 0x800) << 15;
360 out |= (Value & 0x700) << 4;
361 out |= (Value & 0x0FF);
363 uint64_t swapped = (out & 0xFFFF0000) >> 16;
364 swapped |= (out & 0x0000FFFF) << 16;
368 case ARM::fixup_arm_condbranch:
369 case ARM::fixup_arm_uncondbranch:
370 case ARM::fixup_arm_bl:
371 case ARM::fixup_arm_blx:
372 // These values don't encode the low two bits since they're always zero.
373 // Offset by 8 just as above.
374 return 0xffffff & ((Value - 8) >> 2);
375 case ARM::fixup_t2_uncondbranch: {
377 Value >>= 1; // Low bit is not encoded.
380 bool I = Value & 0x800000;
381 bool J1 = Value & 0x400000;
382 bool J2 = Value & 0x200000;
386 out |= I << 26; // S bit
387 out |= !J1 << 13; // J1 bit
388 out |= !J2 << 11; // J2 bit
389 out |= (Value & 0x1FF800) << 5; // imm6 field
390 out |= (Value & 0x0007FF); // imm11 field
392 uint64_t swapped = (out & 0xFFFF0000) >> 16;
393 swapped |= (out & 0x0000FFFF) << 16;
396 case ARM::fixup_t2_condbranch: {
398 Value >>= 1; // Low bit is not encoded.
401 out |= (Value & 0x80000) << 7; // S bit
402 out |= (Value & 0x40000) >> 7; // J2 bit
403 out |= (Value & 0x20000) >> 4; // J1 bit
404 out |= (Value & 0x1F800) << 5; // imm6 field
405 out |= (Value & 0x007FF); // imm11 field
407 uint32_t swapped = (out & 0xFFFF0000) >> 16;
408 swapped |= (out & 0x0000FFFF) << 16;
411 case ARM::fixup_arm_thumb_bl: {
412 // The value doesn't encode the low bit (always zero) and is offset by
413 // four. The value is encoded into disjoint bit positions in the destination
414 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
416 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
418 // Note that the halfwords are stored high first, low second; so we need
419 // to transpose the fixup value here to map properly.
420 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
422 Value = 0x3fffff & ((Value - 4) >> 1);
423 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
424 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
425 Binary |= isNeg << 10; // Sign bit.
428 case ARM::fixup_arm_thumb_blx: {
429 // The value doesn't encode the low two bits (always zero) and is offset by
430 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
431 // positions in the destination opcode. x = unchanged, I = immediate value
432 // bit, S = sign extension bit, 0 = zero.
434 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
436 // Note that the halfwords are stored high first, low second; so we need
437 // to transpose the fixup value here to map properly.
438 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
440 Value = 0xfffff & ((Value - 2) >> 2);
441 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
442 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
443 Binary |= isNeg << 10; // Sign bit.
446 case ARM::fixup_arm_thumb_cp:
447 // Offset by 4, and don't encode the low two bits. Two bytes of that
448 // 'off by 4' is implicitly handled by the half-word ordering of the
449 // Thumb encoding, so we only need to adjust by 2 here.
450 return ((Value - 2) >> 2) & 0xff;
451 case ARM::fixup_arm_thumb_cb: {
452 // Offset by 4 and don't encode the lower bit, which is always 0.
453 uint32_t Binary = (Value - 4) >> 1;
454 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
456 case ARM::fixup_arm_thumb_br:
457 // Offset by 4 and don't encode the lower bit, which is always 0.
458 return ((Value - 4) >> 1) & 0x7ff;
459 case ARM::fixup_arm_thumb_bcc:
460 // Offset by 4 and don't encode the lower bit, which is always 0.
461 return ((Value - 4) >> 1) & 0xff;
462 case ARM::fixup_arm_pcrel_10_unscaled: {
463 Value = Value - 8; // ARM fixups offset by an additional word and don't
464 // need to adjust for the half-word ordering.
466 if ((int64_t)Value < 0) {
470 assert ((Value < 256) && "Out of range pc-relative fixup value!");
471 return Value | (isAdd << 23);
473 case ARM::fixup_arm_pcrel_10:
474 Value = Value - 4; // ARM fixups offset by an additional word and don't
475 // need to adjust for the half-word ordering.
477 case ARM::fixup_t2_pcrel_10: {
478 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
481 if ((int64_t)Value < 0) {
485 // These values don't encode the low two bits since they're always zero.
487 assert ((Value < 256) && "Out of range pc-relative fixup value!");
488 Value |= isAdd << 23;
490 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
492 if (Kind == ARM::fixup_t2_pcrel_10) {
493 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
494 swapped |= (Value & 0x0000FFFF) << 16;
505 // FIXME: This should be in a separate file.
506 // ELF is an ELF of course...
507 class ELFARMAsmBackend : public ARMAsmBackend {
510 ELFARMAsmBackend(const Target &T, const StringRef TT,
512 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
514 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
515 uint64_t Value) const;
517 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
518 return createARMELFObjectWriter(OS, OSABI);
522 // FIXME: Raise this to share code between Darwin and ELF.
523 void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
524 unsigned DataSize, uint64_t Value) const {
525 unsigned NumBytes = 4; // FIXME: 2 for Thumb
526 Value = adjustFixupValue(Fixup.getKind(), Value);
527 if (!Value) return; // Doesn't change encoding.
529 unsigned Offset = Fixup.getOffset();
531 // For each byte of the fragment that the fixup touches, mask in the bits from
532 // the fixup value. The Value has been "split up" into the appropriate
534 for (unsigned i = 0; i != NumBytes; ++i)
535 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
538 // FIXME: This should be in a separate file.
539 class DarwinARMAsmBackend : public ARMAsmBackend {
541 const object::mach::CPUSubtypeARM Subtype;
542 DarwinARMAsmBackend(const Target &T, const StringRef TT,
543 object::mach::CPUSubtypeARM st)
544 : ARMAsmBackend(T, TT), Subtype(st) { }
546 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
547 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
548 object::mach::CTM_ARM,
552 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
553 uint64_t Value) const;
555 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
560 /// getFixupKindNumBytes - The number of bytes the fixup may change.
561 static unsigned getFixupKindNumBytes(unsigned Kind) {
564 llvm_unreachable("Unknown fixup kind!");
567 case ARM::fixup_arm_thumb_bcc:
568 case ARM::fixup_arm_thumb_cp:
569 case ARM::fixup_thumb_adr_pcrel_10:
573 case ARM::fixup_arm_thumb_br:
574 case ARM::fixup_arm_thumb_cb:
577 case ARM::fixup_arm_pcrel_10_unscaled:
578 case ARM::fixup_arm_ldst_pcrel_12:
579 case ARM::fixup_arm_pcrel_10:
580 case ARM::fixup_arm_adr_pcrel_12:
581 case ARM::fixup_arm_bl:
582 case ARM::fixup_arm_blx:
583 case ARM::fixup_arm_condbranch:
584 case ARM::fixup_arm_uncondbranch:
588 case ARM::fixup_t2_ldst_pcrel_12:
589 case ARM::fixup_t2_condbranch:
590 case ARM::fixup_t2_uncondbranch:
591 case ARM::fixup_t2_pcrel_10:
592 case ARM::fixup_t2_adr_pcrel_12:
593 case ARM::fixup_arm_thumb_bl:
594 case ARM::fixup_arm_thumb_blx:
595 case ARM::fixup_arm_movt_hi16:
596 case ARM::fixup_arm_movw_lo16:
597 case ARM::fixup_arm_movt_hi16_pcrel:
598 case ARM::fixup_arm_movw_lo16_pcrel:
599 case ARM::fixup_t2_movt_hi16:
600 case ARM::fixup_t2_movw_lo16:
601 case ARM::fixup_t2_movt_hi16_pcrel:
602 case ARM::fixup_t2_movw_lo16_pcrel:
607 void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
608 unsigned DataSize, uint64_t Value) const {
609 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
610 Value = adjustFixupValue(Fixup.getKind(), Value);
611 if (!Value) return; // Doesn't change encoding.
613 unsigned Offset = Fixup.getOffset();
614 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
616 // For each byte of the fragment that the fixup touches, mask in the
617 // bits from the fixup value.
618 for (unsigned i = 0; i != NumBytes; ++i)
619 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
622 } // end anonymous namespace
624 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
625 Triple TheTriple(TT);
627 if (TheTriple.isOSDarwin()) {
628 if (TheTriple.getArchName() == "armv4t" ||
629 TheTriple.getArchName() == "thumbv4t")
630 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
631 else if (TheTriple.getArchName() == "armv5e" ||
632 TheTriple.getArchName() == "thumbv5e")
633 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
634 else if (TheTriple.getArchName() == "armv6" ||
635 TheTriple.getArchName() == "thumbv6")
636 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
637 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
640 if (TheTriple.isOSWindows())
641 assert(0 && "Windows not supported on ARM");
643 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
644 return new ELFARMAsmBackend(T, TT, OSABI);