1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMFixupKinds.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCDirectives.h"
17 #include "llvm/MC/MCELFObjectWriter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCMachObjectWriter.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Object/MachOFormat.h"
26 #include "llvm/Support/ELF.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
32 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
34 ARMELFObjectWriter(Triple::OSType OSType)
35 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSType, ELF::EM_ARM,
36 /*HasRelocationAddend*/ false) {}
39 class ARMAsmBackend : public MCAsmBackend {
40 const MCSubtargetInfo* STI;
41 bool isThumbMode; // Currently emitting Thumb code.
43 ARMAsmBackend(const Target &T, const StringRef TT)
44 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
45 isThumbMode(TT.startswith("thumb")) {}
51 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
54 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
57 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
58 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
59 // This table *must* be in the order that the fixup_* kinds are defined in
62 // Name Offset (bits) Size (bits) Flags
63 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
64 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
65 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
66 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
67 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
69 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
71 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
72 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
73 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
74 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
75 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
76 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
77 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
84 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
85 { "fixup_arm_movt_hi16", 0, 20, 0 },
86 { "fixup_arm_movw_lo16", 0, 20, 0 },
87 { "fixup_t2_movt_hi16", 0, 20, 0 },
88 { "fixup_t2_movw_lo16", 0, 20, 0 },
89 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
90 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
91 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
92 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
95 if (Kind < FirstTargetFixupKind)
96 return MCAsmBackend::getFixupKindInfo(Kind);
98 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
100 return Infos[Kind - FirstTargetFixupKind];
103 bool MayNeedRelaxation(const MCInst &Inst) const;
105 bool fixupNeedsRelaxation(const MCFixup &Fixup,
107 const MCInstFragment *DF,
108 const MCAsmLayout &Layout) const;
110 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
112 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
114 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
126 unsigned getPointerSize() const { return 4; }
127 bool isThumb() const { return isThumbMode; }
128 void setIsThumb(bool it) { isThumbMode = it; }
130 } // end anonymous namespace
132 static unsigned getRelaxedOpcode(unsigned Op) {
135 case ARM::tBcc: return ARM::t2Bcc;
139 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
140 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
145 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
147 const MCInstFragment *DF,
148 const MCAsmLayout &Layout) const {
149 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
150 // low bit being an implied zero. There's an implied +4 offset for the
151 // branch, so we adjust the other way here to determine what's
154 // Relax if the value is too big for a (signed) i8.
155 return int64_t((Value - 4)>>1) != int64_t(int8_t((Value - 4)>>1));
158 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
159 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
161 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
162 if (RelaxedOp == Inst.getOpcode()) {
163 SmallString<256> Tmp;
164 raw_svector_ostream OS(Tmp);
165 Inst.dump_pretty(OS);
167 report_fatal_error("unexpected instruction to relax: " + OS.str());
170 // The instructions we're relaxing have (so far) the same operands.
171 // We just need to update to the proper opcode.
173 Res.setOpcode(RelaxedOp);
176 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
177 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
178 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
179 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
180 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
182 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
183 : Thumb1_16bitNopEncoding;
184 uint64_t NumNops = Count / 2;
185 for (uint64_t i = 0; i != NumNops; ++i)
186 OW->Write16(nopEncoding);
192 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
194 uint64_t NumNops = Count / 4;
195 for (uint64_t i = 0; i != NumNops; ++i)
196 OW->Write32(nopEncoding);
197 // FIXME: should this function return false when unable to write exactly
198 // 'Count' bytes with NOP encodings?
200 default: break; // No leftover bytes to write
201 case 1: OW->Write8(0); break;
202 case 2: OW->Write16(0); break;
203 case 3: OW->Write16(0); OW->Write8(0xa0); break;
209 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
212 llvm_unreachable("Unknown fixup kind!");
217 case ARM::fixup_arm_movt_hi16:
220 case ARM::fixup_arm_movw_lo16:
221 case ARM::fixup_arm_movt_hi16_pcrel:
222 case ARM::fixup_arm_movw_lo16_pcrel: {
223 unsigned Hi4 = (Value & 0xF000) >> 12;
224 unsigned Lo12 = Value & 0x0FFF;
225 // inst{19-16} = Hi4;
226 // inst{11-0} = Lo12;
227 Value = (Hi4 << 16) | (Lo12);
230 case ARM::fixup_t2_movt_hi16:
233 case ARM::fixup_t2_movw_lo16:
234 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
235 // the other hi16 fixup?
236 case ARM::fixup_t2_movw_lo16_pcrel: {
237 unsigned Hi4 = (Value & 0xF000) >> 12;
238 unsigned i = (Value & 0x800) >> 11;
239 unsigned Mid3 = (Value & 0x700) >> 8;
240 unsigned Lo8 = Value & 0x0FF;
241 // inst{19-16} = Hi4;
243 // inst{14-12} = Mid3;
245 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
246 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
247 swapped |= (Value & 0x0000FFFF) << 16;
250 case ARM::fixup_arm_ldst_pcrel_12:
251 // ARM PC-relative values are offset by 8.
254 case ARM::fixup_t2_ldst_pcrel_12: {
255 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
258 if ((int64_t)Value < 0) {
262 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
263 Value |= isAdd << 23;
265 // Same addressing mode as fixup_arm_pcrel_10,
266 // but with 16-bit halfwords swapped.
267 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
268 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
269 swapped |= (Value & 0x0000FFFF) << 16;
275 case ARM::fixup_thumb_adr_pcrel_10:
276 return ((Value - 4) >> 2) & 0xff;
277 case ARM::fixup_arm_adr_pcrel_12: {
278 // ARM PC-relative values are offset by 8.
280 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
281 if ((int64_t)Value < 0) {
285 assert(ARM_AM::getSOImmVal(Value) != -1 &&
286 "Out of range pc-relative fixup value!");
287 // Encode the immediate and shift the opcode into place.
288 return ARM_AM::getSOImmVal(Value) | (opc << 21);
291 case ARM::fixup_t2_adr_pcrel_12: {
294 if ((int64_t)Value < 0) {
299 uint32_t out = (opc << 21);
300 out |= (Value & 0x800) << 15;
301 out |= (Value & 0x700) << 4;
302 out |= (Value & 0x0FF);
304 uint64_t swapped = (out & 0xFFFF0000) >> 16;
305 swapped |= (out & 0x0000FFFF) << 16;
309 case ARM::fixup_arm_condbranch:
310 case ARM::fixup_arm_uncondbranch:
311 // These values don't encode the low two bits since they're always zero.
312 // Offset by 8 just as above.
313 return 0xffffff & ((Value - 8) >> 2);
314 case ARM::fixup_t2_uncondbranch: {
316 Value >>= 1; // Low bit is not encoded.
319 bool I = Value & 0x800000;
320 bool J1 = Value & 0x400000;
321 bool J2 = Value & 0x200000;
325 out |= I << 26; // S bit
326 out |= !J1 << 13; // J1 bit
327 out |= !J2 << 11; // J2 bit
328 out |= (Value & 0x1FF800) << 5; // imm6 field
329 out |= (Value & 0x0007FF); // imm11 field
331 uint64_t swapped = (out & 0xFFFF0000) >> 16;
332 swapped |= (out & 0x0000FFFF) << 16;
335 case ARM::fixup_t2_condbranch: {
337 Value >>= 1; // Low bit is not encoded.
340 out |= (Value & 0x80000) << 7; // S bit
341 out |= (Value & 0x40000) >> 7; // J2 bit
342 out |= (Value & 0x20000) >> 4; // J1 bit
343 out |= (Value & 0x1F800) << 5; // imm6 field
344 out |= (Value & 0x007FF); // imm11 field
346 uint32_t swapped = (out & 0xFFFF0000) >> 16;
347 swapped |= (out & 0x0000FFFF) << 16;
350 case ARM::fixup_arm_thumb_bl: {
351 // The value doesn't encode the low bit (always zero) and is offset by
352 // four. The value is encoded into disjoint bit positions in the destination
353 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
355 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
357 // Note that the halfwords are stored high first, low second; so we need
358 // to transpose the fixup value here to map properly.
359 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
361 Value = 0x3fffff & ((Value - 4) >> 1);
362 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
363 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
364 Binary |= isNeg << 10; // Sign bit.
367 case ARM::fixup_arm_thumb_blx: {
368 // The value doesn't encode the low two bits (always zero) and is offset by
369 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
370 // positions in the destination opcode. x = unchanged, I = immediate value
371 // bit, S = sign extension bit, 0 = zero.
373 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
375 // Note that the halfwords are stored high first, low second; so we need
376 // to transpose the fixup value here to map properly.
377 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
379 Value = 0xfffff & ((Value - 2) >> 2);
380 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
381 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
382 Binary |= isNeg << 10; // Sign bit.
385 case ARM::fixup_arm_thumb_cp:
386 // Offset by 4, and don't encode the low two bits. Two bytes of that
387 // 'off by 4' is implicitly handled by the half-word ordering of the
388 // Thumb encoding, so we only need to adjust by 2 here.
389 return ((Value - 2) >> 2) & 0xff;
390 case ARM::fixup_arm_thumb_cb: {
391 // Offset by 4 and don't encode the lower bit, which is always 0.
392 uint32_t Binary = (Value - 4) >> 1;
393 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
395 case ARM::fixup_arm_thumb_br:
396 // Offset by 4 and don't encode the lower bit, which is always 0.
397 return ((Value - 4) >> 1) & 0x7ff;
398 case ARM::fixup_arm_thumb_bcc:
399 // Offset by 4 and don't encode the lower bit, which is always 0.
400 return ((Value - 4) >> 1) & 0xff;
401 case ARM::fixup_arm_pcrel_10:
402 Value = Value - 4; // ARM fixups offset by an additional word and don't
403 // need to adjust for the half-word ordering.
405 case ARM::fixup_t2_pcrel_10: {
406 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
409 if ((int64_t)Value < 0) {
413 // These values don't encode the low two bits since they're always zero.
415 assert ((Value < 256) && "Out of range pc-relative fixup value!");
416 Value |= isAdd << 23;
418 // Same addressing mode as fixup_arm_pcrel_10,
419 // but with 16-bit halfwords swapped.
420 if (Kind == ARM::fixup_t2_pcrel_10) {
421 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
422 swapped |= (Value & 0x0000FFFF) << 16;
433 // FIXME: This should be in a separate file.
434 // ELF is an ELF of course...
435 class ELFARMAsmBackend : public ARMAsmBackend {
437 Triple::OSType OSType;
438 ELFARMAsmBackend(const Target &T, const StringRef TT,
439 Triple::OSType _OSType)
440 : ARMAsmBackend(T, TT), OSType(_OSType) { }
442 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
443 uint64_t Value) const;
445 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
446 return createELFObjectWriter(new ARMELFObjectWriter(OSType), OS,
447 /*IsLittleEndian*/ true);
451 // FIXME: Raise this to share code between Darwin and ELF.
452 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
453 unsigned DataSize, uint64_t Value) const {
454 unsigned NumBytes = 4; // FIXME: 2 for Thumb
455 Value = adjustFixupValue(Fixup.getKind(), Value);
456 if (!Value) return; // Doesn't change encoding.
458 unsigned Offset = Fixup.getOffset();
460 // For each byte of the fragment that the fixup touches, mask in the bits from
461 // the fixup value. The Value has been "split up" into the appropriate
463 for (unsigned i = 0; i != NumBytes; ++i)
464 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
467 // FIXME: This should be in a separate file.
468 class DarwinARMAsmBackend : public ARMAsmBackend {
470 const object::mach::CPUSubtypeARM Subtype;
471 DarwinARMAsmBackend(const Target &T, const StringRef TT,
472 object::mach::CPUSubtypeARM st)
473 : ARMAsmBackend(T, TT), Subtype(st) { }
475 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
476 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
477 object::mach::CTM_ARM,
481 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
482 uint64_t Value) const;
484 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
489 /// getFixupKindNumBytes - The number of bytes the fixup may change.
490 static unsigned getFixupKindNumBytes(unsigned Kind) {
493 llvm_unreachable("Unknown fixup kind!");
496 case ARM::fixup_arm_thumb_bcc:
497 case ARM::fixup_arm_thumb_cp:
498 case ARM::fixup_thumb_adr_pcrel_10:
502 case ARM::fixup_arm_thumb_br:
503 case ARM::fixup_arm_thumb_cb:
506 case ARM::fixup_arm_ldst_pcrel_12:
507 case ARM::fixup_arm_pcrel_10:
508 case ARM::fixup_arm_adr_pcrel_12:
509 case ARM::fixup_arm_condbranch:
510 case ARM::fixup_arm_uncondbranch:
514 case ARM::fixup_t2_ldst_pcrel_12:
515 case ARM::fixup_t2_condbranch:
516 case ARM::fixup_t2_uncondbranch:
517 case ARM::fixup_t2_pcrel_10:
518 case ARM::fixup_t2_adr_pcrel_12:
519 case ARM::fixup_arm_thumb_bl:
520 case ARM::fixup_arm_thumb_blx:
521 case ARM::fixup_arm_movt_hi16:
522 case ARM::fixup_arm_movw_lo16:
523 case ARM::fixup_arm_movt_hi16_pcrel:
524 case ARM::fixup_arm_movw_lo16_pcrel:
525 case ARM::fixup_t2_movt_hi16:
526 case ARM::fixup_t2_movw_lo16:
527 case ARM::fixup_t2_movt_hi16_pcrel:
528 case ARM::fixup_t2_movw_lo16_pcrel:
533 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
534 unsigned DataSize, uint64_t Value) const {
535 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
536 Value = adjustFixupValue(Fixup.getKind(), Value);
537 if (!Value) return; // Doesn't change encoding.
539 unsigned Offset = Fixup.getOffset();
540 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
542 // For each byte of the fragment that the fixup touches, mask in the
543 // bits from the fixup value.
544 for (unsigned i = 0; i != NumBytes; ++i)
545 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
548 } // end anonymous namespace
550 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
551 Triple TheTriple(TT);
553 if (TheTriple.isOSDarwin()) {
554 if (TheTriple.getArchName() == "armv4t" ||
555 TheTriple.getArchName() == "thumbv4t")
556 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
557 else if (TheTriple.getArchName() == "armv5e" ||
558 TheTriple.getArchName() == "thumbv5e")
559 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
560 else if (TheTriple.getArchName() == "armv6" ||
561 TheTriple.getArchName() == "thumbv6")
562 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
563 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
566 if (TheTriple.isOSWindows())
567 assert(0 && "Windows not supported on ARM");
569 return new ELFARMAsmBackend(T, TT, Triple(TT).getOS());