1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMFixupKinds.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCDirectives.h"
17 #include "llvm/MC/MCELFObjectWriter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCMachObjectWriter.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCValue.h"
26 #include "llvm/Object/MachOFormat.h"
27 #include "llvm/Support/ELF.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
33 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
35 ARMELFObjectWriter(uint8_t OSABI)
36 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
37 /*HasRelocationAddend*/ false) {}
40 class ARMAsmBackend : public MCAsmBackend {
41 const MCSubtargetInfo* STI;
42 bool isThumbMode; // Currently emitting Thumb code.
44 ARMAsmBackend(const Target &T, const StringRef TT)
45 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
46 isThumbMode(TT.startswith("thumb")) {}
52 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
55 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
58 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
59 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
60 // This table *must* be in the order that the fixup_* kinds are defined in
63 // Name Offset (bits) Size (bits) Flags
64 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
65 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
66 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
67 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
68 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
69 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
71 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
73 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
74 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
76 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
77 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
84 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
85 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
86 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
87 { "fixup_arm_movt_hi16", 0, 20, 0 },
88 { "fixup_arm_movw_lo16", 0, 20, 0 },
89 { "fixup_t2_movt_hi16", 0, 20, 0 },
90 { "fixup_t2_movw_lo16", 0, 20, 0 },
91 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
92 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
93 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
94 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
97 if (Kind < FirstTargetFixupKind)
98 return MCAsmBackend::getFixupKindInfo(Kind);
100 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
102 return Infos[Kind - FirstTargetFixupKind];
105 /// processFixupValue - Target hook to process the literal value of a fixup
107 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
108 const MCFixup &Fixup, const MCFragment *DF,
109 MCValue &Target, uint64_t &Value) {
110 // Some fixups to thumb function symbols need the low bit (thumb bit)
112 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
113 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
114 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
115 if (const MCSymbolRefExpr *A = Target.getSymA()) {
116 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
117 if (Asm.isThumbFunc(&Sym))
123 bool mayNeedRelaxation(const MCInst &Inst) const;
125 bool fixupNeedsRelaxation(const MCFixup &Fixup,
127 const MCInstFragment *DF,
128 const MCAsmLayout &Layout) const;
130 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
132 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
134 void handleAssemblerFlag(MCAssemblerFlag Flag) {
146 unsigned getPointerSize() const { return 4; }
147 bool isThumb() const { return isThumbMode; }
148 void setIsThumb(bool it) { isThumbMode = it; }
150 } // end anonymous namespace
152 static unsigned getRelaxedOpcode(unsigned Op) {
155 case ARM::tBcc: return ARM::t2Bcc;
156 case ARM::tLDRpciASM: return ARM::t2LDRpci;
160 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
161 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
166 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
168 const MCInstFragment *DF,
169 const MCAsmLayout &Layout) const {
170 switch (Fixup.getKind()) {
171 default: assert(0 && "Unexpected fixup kind in fixupNeedsRelaxation()!");
172 case ARM::fixup_arm_thumb_bcc: {
173 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
174 // low bit being an implied zero. There's an implied +4 offset for the
175 // branch, so we adjust the other way here to determine what's
178 // Relax if the value is too big for a (signed) i8.
179 int64_t Offset = int64_t(Value) - 4;
180 return Offset > 254 || Offset < -256;
182 case ARM::fixup_arm_thumb_cp: {
183 // If the immediate is negative, greater than 1020, or not a multiple
184 // of four, the wide version of the instruction must be used.
185 int64_t Offset = int64_t(Value) - 4;
186 return Offset > 1020 || Offset < 0 || Offset & 3;
189 llvm_unreachable("Invalid switch/cash!?");
192 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
193 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
195 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
196 if (RelaxedOp == Inst.getOpcode()) {
197 SmallString<256> Tmp;
198 raw_svector_ostream OS(Tmp);
199 Inst.dump_pretty(OS);
201 report_fatal_error("unexpected instruction to relax: " + OS.str());
204 // The instructions we're relaxing have (so far) the same operands.
205 // We just need to update to the proper opcode.
207 Res.setOpcode(RelaxedOp);
210 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
211 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
212 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
213 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
214 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
216 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
217 : Thumb1_16bitNopEncoding;
218 uint64_t NumNops = Count / 2;
219 for (uint64_t i = 0; i != NumNops; ++i)
220 OW->Write16(nopEncoding);
226 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
228 uint64_t NumNops = Count / 4;
229 for (uint64_t i = 0; i != NumNops; ++i)
230 OW->Write32(nopEncoding);
231 // FIXME: should this function return false when unable to write exactly
232 // 'Count' bytes with NOP encodings?
234 default: break; // No leftover bytes to write
235 case 1: OW->Write8(0); break;
236 case 2: OW->Write16(0); break;
237 case 3: OW->Write16(0); OW->Write8(0xa0); break;
243 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
246 llvm_unreachable("Unknown fixup kind!");
251 case ARM::fixup_arm_movt_hi16:
254 case ARM::fixup_arm_movw_lo16:
255 case ARM::fixup_arm_movt_hi16_pcrel:
256 case ARM::fixup_arm_movw_lo16_pcrel: {
257 unsigned Hi4 = (Value & 0xF000) >> 12;
258 unsigned Lo12 = Value & 0x0FFF;
259 // inst{19-16} = Hi4;
260 // inst{11-0} = Lo12;
261 Value = (Hi4 << 16) | (Lo12);
264 case ARM::fixup_t2_movt_hi16:
267 case ARM::fixup_t2_movw_lo16:
268 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
269 // the other hi16 fixup?
270 case ARM::fixup_t2_movw_lo16_pcrel: {
271 unsigned Hi4 = (Value & 0xF000) >> 12;
272 unsigned i = (Value & 0x800) >> 11;
273 unsigned Mid3 = (Value & 0x700) >> 8;
274 unsigned Lo8 = Value & 0x0FF;
275 // inst{19-16} = Hi4;
277 // inst{14-12} = Mid3;
279 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
280 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
281 swapped |= (Value & 0x0000FFFF) << 16;
284 case ARM::fixup_arm_ldst_pcrel_12:
285 // ARM PC-relative values are offset by 8.
288 case ARM::fixup_t2_ldst_pcrel_12: {
289 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
292 if ((int64_t)Value < 0) {
296 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
297 Value |= isAdd << 23;
299 // Same addressing mode as fixup_arm_pcrel_10,
300 // but with 16-bit halfwords swapped.
301 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
302 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
303 swapped |= (Value & 0x0000FFFF) << 16;
309 case ARM::fixup_thumb_adr_pcrel_10:
310 return ((Value - 4) >> 2) & 0xff;
311 case ARM::fixup_arm_adr_pcrel_12: {
312 // ARM PC-relative values are offset by 8.
314 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
315 if ((int64_t)Value < 0) {
319 assert(ARM_AM::getSOImmVal(Value) != -1 &&
320 "Out of range pc-relative fixup value!");
321 // Encode the immediate and shift the opcode into place.
322 return ARM_AM::getSOImmVal(Value) | (opc << 21);
325 case ARM::fixup_t2_adr_pcrel_12: {
328 if ((int64_t)Value < 0) {
333 uint32_t out = (opc << 21);
334 out |= (Value & 0x800) << 15;
335 out |= (Value & 0x700) << 4;
336 out |= (Value & 0x0FF);
338 uint64_t swapped = (out & 0xFFFF0000) >> 16;
339 swapped |= (out & 0x0000FFFF) << 16;
343 case ARM::fixup_arm_condbranch:
344 case ARM::fixup_arm_uncondbranch:
345 // These values don't encode the low two bits since they're always zero.
346 // Offset by 8 just as above.
347 return 0xffffff & ((Value - 8) >> 2);
348 case ARM::fixup_t2_uncondbranch: {
350 Value >>= 1; // Low bit is not encoded.
353 bool I = Value & 0x800000;
354 bool J1 = Value & 0x400000;
355 bool J2 = Value & 0x200000;
359 out |= I << 26; // S bit
360 out |= !J1 << 13; // J1 bit
361 out |= !J2 << 11; // J2 bit
362 out |= (Value & 0x1FF800) << 5; // imm6 field
363 out |= (Value & 0x0007FF); // imm11 field
365 uint64_t swapped = (out & 0xFFFF0000) >> 16;
366 swapped |= (out & 0x0000FFFF) << 16;
369 case ARM::fixup_t2_condbranch: {
371 Value >>= 1; // Low bit is not encoded.
374 out |= (Value & 0x80000) << 7; // S bit
375 out |= (Value & 0x40000) >> 7; // J2 bit
376 out |= (Value & 0x20000) >> 4; // J1 bit
377 out |= (Value & 0x1F800) << 5; // imm6 field
378 out |= (Value & 0x007FF); // imm11 field
380 uint32_t swapped = (out & 0xFFFF0000) >> 16;
381 swapped |= (out & 0x0000FFFF) << 16;
384 case ARM::fixup_arm_thumb_bl: {
385 // The value doesn't encode the low bit (always zero) and is offset by
386 // four. The value is encoded into disjoint bit positions in the destination
387 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
389 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
391 // Note that the halfwords are stored high first, low second; so we need
392 // to transpose the fixup value here to map properly.
393 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
395 Value = 0x3fffff & ((Value - 4) >> 1);
396 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
397 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
398 Binary |= isNeg << 10; // Sign bit.
401 case ARM::fixup_arm_thumb_blx: {
402 // The value doesn't encode the low two bits (always zero) and is offset by
403 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
404 // positions in the destination opcode. x = unchanged, I = immediate value
405 // bit, S = sign extension bit, 0 = zero.
407 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
409 // Note that the halfwords are stored high first, low second; so we need
410 // to transpose the fixup value here to map properly.
411 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
413 Value = 0xfffff & ((Value - 2) >> 2);
414 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
415 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
416 Binary |= isNeg << 10; // Sign bit.
419 case ARM::fixup_arm_thumb_cp:
420 // Offset by 4, and don't encode the low two bits. Two bytes of that
421 // 'off by 4' is implicitly handled by the half-word ordering of the
422 // Thumb encoding, so we only need to adjust by 2 here.
423 return ((Value - 2) >> 2) & 0xff;
424 case ARM::fixup_arm_thumb_cb: {
425 // Offset by 4 and don't encode the lower bit, which is always 0.
426 uint32_t Binary = (Value - 4) >> 1;
427 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
429 case ARM::fixup_arm_thumb_br:
430 // Offset by 4 and don't encode the lower bit, which is always 0.
431 return ((Value - 4) >> 1) & 0x7ff;
432 case ARM::fixup_arm_thumb_bcc:
433 // Offset by 4 and don't encode the lower bit, which is always 0.
434 return ((Value - 4) >> 1) & 0xff;
435 case ARM::fixup_arm_pcrel_10_unscaled: {
436 Value = Value - 8; // ARM fixups offset by an additional word and don't
437 // need to adjust for the half-word ordering.
439 if ((int64_t)Value < 0) {
443 assert ((Value < 256) && "Out of range pc-relative fixup value!");
444 return Value | (isAdd << 23);
446 case ARM::fixup_arm_pcrel_10:
447 Value = Value - 4; // ARM fixups offset by an additional word and don't
448 // need to adjust for the half-word ordering.
450 case ARM::fixup_t2_pcrel_10: {
451 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
454 if ((int64_t)Value < 0) {
458 // These values don't encode the low two bits since they're always zero.
460 assert ((Value < 256) && "Out of range pc-relative fixup value!");
461 Value |= isAdd << 23;
463 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
465 if (Kind == ARM::fixup_t2_pcrel_10) {
466 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
467 swapped |= (Value & 0x0000FFFF) << 16;
478 // FIXME: This should be in a separate file.
479 // ELF is an ELF of course...
480 class ELFARMAsmBackend : public ARMAsmBackend {
483 ELFARMAsmBackend(const Target &T, const StringRef TT,
485 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
487 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
488 uint64_t Value) const;
490 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
491 return createARMELFObjectWriter(OS, OSABI);
495 // FIXME: Raise this to share code between Darwin and ELF.
496 void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
497 unsigned DataSize, uint64_t Value) const {
498 unsigned NumBytes = 4; // FIXME: 2 for Thumb
499 Value = adjustFixupValue(Fixup.getKind(), Value);
500 if (!Value) return; // Doesn't change encoding.
502 unsigned Offset = Fixup.getOffset();
504 // For each byte of the fragment that the fixup touches, mask in the bits from
505 // the fixup value. The Value has been "split up" into the appropriate
507 for (unsigned i = 0; i != NumBytes; ++i)
508 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
511 // FIXME: This should be in a separate file.
512 class DarwinARMAsmBackend : public ARMAsmBackend {
514 const object::mach::CPUSubtypeARM Subtype;
515 DarwinARMAsmBackend(const Target &T, const StringRef TT,
516 object::mach::CPUSubtypeARM st)
517 : ARMAsmBackend(T, TT), Subtype(st) { }
519 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
520 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
521 object::mach::CTM_ARM,
525 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
526 uint64_t Value) const;
528 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
533 /// getFixupKindNumBytes - The number of bytes the fixup may change.
534 static unsigned getFixupKindNumBytes(unsigned Kind) {
537 llvm_unreachable("Unknown fixup kind!");
540 case ARM::fixup_arm_thumb_bcc:
541 case ARM::fixup_arm_thumb_cp:
542 case ARM::fixup_thumb_adr_pcrel_10:
546 case ARM::fixup_arm_thumb_br:
547 case ARM::fixup_arm_thumb_cb:
550 case ARM::fixup_arm_pcrel_10_unscaled:
551 case ARM::fixup_arm_ldst_pcrel_12:
552 case ARM::fixup_arm_pcrel_10:
553 case ARM::fixup_arm_adr_pcrel_12:
554 case ARM::fixup_arm_condbranch:
555 case ARM::fixup_arm_uncondbranch:
559 case ARM::fixup_t2_ldst_pcrel_12:
560 case ARM::fixup_t2_condbranch:
561 case ARM::fixup_t2_uncondbranch:
562 case ARM::fixup_t2_pcrel_10:
563 case ARM::fixup_t2_adr_pcrel_12:
564 case ARM::fixup_arm_thumb_bl:
565 case ARM::fixup_arm_thumb_blx:
566 case ARM::fixup_arm_movt_hi16:
567 case ARM::fixup_arm_movw_lo16:
568 case ARM::fixup_arm_movt_hi16_pcrel:
569 case ARM::fixup_arm_movw_lo16_pcrel:
570 case ARM::fixup_t2_movt_hi16:
571 case ARM::fixup_t2_movw_lo16:
572 case ARM::fixup_t2_movt_hi16_pcrel:
573 case ARM::fixup_t2_movw_lo16_pcrel:
578 void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
579 unsigned DataSize, uint64_t Value) const {
580 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
581 Value = adjustFixupValue(Fixup.getKind(), Value);
582 if (!Value) return; // Doesn't change encoding.
584 unsigned Offset = Fixup.getOffset();
585 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
587 // For each byte of the fragment that the fixup touches, mask in the
588 // bits from the fixup value.
589 for (unsigned i = 0; i != NumBytes; ++i)
590 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
593 } // end anonymous namespace
595 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
596 Triple TheTriple(TT);
598 if (TheTriple.isOSDarwin()) {
599 if (TheTriple.getArchName() == "armv4t" ||
600 TheTriple.getArchName() == "thumbv4t")
601 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
602 else if (TheTriple.getArchName() == "armv5e" ||
603 TheTriple.getArchName() == "thumbv5e")
604 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
605 else if (TheTriple.getArchName() == "armv6" ||
606 TheTriple.getArchName() == "thumbv6")
607 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
608 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
611 if (TheTriple.isOSWindows())
612 assert(0 && "Windows not supported on ARM");
614 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
615 return new ELFARMAsmBackend(T, TT, OSABI);