1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMFixupKinds.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCELFObjectWriter.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCFixupKindInfo.h"
19 #include "llvm/MC/MCMachObjectWriter.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCValue.h"
26 #include "llvm/Object/MachOFormat.h"
27 #include "llvm/Support/ELF.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
33 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
35 ARMELFObjectWriter(uint8_t OSABI)
36 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
37 /*HasRelocationAddend*/ false) {}
40 class ARMAsmBackend : public MCAsmBackend {
41 const MCSubtargetInfo* STI;
42 bool isThumbMode; // Currently emitting Thumb code.
44 ARMAsmBackend(const Target &T, const StringRef TT)
45 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
46 isThumbMode(TT.startswith("thumb")) {}
52 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
55 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
58 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
59 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
60 // This table *must* be in the order that the fixup_* kinds are defined in
63 // Name Offset (bits) Size (bits) Flags
64 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
65 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
66 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
67 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
68 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
69 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
71 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
73 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
74 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
76 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
77 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
84 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
85 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
86 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
87 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel |
88 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
89 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
90 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
91 { "fixup_arm_movt_hi16", 0, 20, 0 },
92 { "fixup_arm_movw_lo16", 0, 20, 0 },
93 { "fixup_t2_movt_hi16", 0, 20, 0 },
94 { "fixup_t2_movw_lo16", 0, 20, 0 },
95 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
96 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
97 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
98 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
101 if (Kind < FirstTargetFixupKind)
102 return MCAsmBackend::getFixupKindInfo(Kind);
104 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
106 return Infos[Kind - FirstTargetFixupKind];
109 /// processFixupValue - Target hook to process the literal value of a fixup
111 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
112 const MCFixup &Fixup, const MCFragment *DF,
113 MCValue &Target, uint64_t &Value,
115 const MCSymbolRefExpr *A = Target.getSymA();
116 // Some fixups to thumb function symbols need the low bit (thumb bit)
118 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
119 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
120 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
121 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
122 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
123 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
125 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
126 if (Asm.isThumbFunc(&Sym))
130 // We must always generate a relocation for BL/BLX instructions if we have
131 // a symbol to reference, as the linker relies on knowing the destination
132 // symbol's thumb-ness to get interworking right.
133 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
134 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||
135 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
136 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
137 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
141 bool mayNeedRelaxation(const MCInst &Inst) const;
143 bool fixupNeedsRelaxation(const MCFixup &Fixup,
145 const MCInstFragment *DF,
146 const MCAsmLayout &Layout) const;
148 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
150 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
152 void handleAssemblerFlag(MCAssemblerFlag Flag) {
164 unsigned getPointerSize() const { return 4; }
165 bool isThumb() const { return isThumbMode; }
166 void setIsThumb(bool it) { isThumbMode = it; }
168 } // end anonymous namespace
170 static unsigned getRelaxedOpcode(unsigned Op) {
173 case ARM::tBcc: return ARM::t2Bcc;
174 case ARM::tLDRpciASM: return ARM::t2LDRpci;
175 case ARM::tADR: return ARM::t2ADR;
176 case ARM::tB: return ARM::t2B;
180 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
181 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
186 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
188 const MCInstFragment *DF,
189 const MCAsmLayout &Layout) const {
190 switch ((unsigned)Fixup.getKind()) {
191 case ARM::fixup_arm_thumb_br: {
192 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
193 // low bit being an implied zero. There's an implied +4 offset for the
194 // branch, so we adjust the other way here to determine what's
197 // Relax if the value is too big for a (signed) i8.
198 int64_t Offset = int64_t(Value) - 4;
199 return Offset > 2046 || Offset < -2048;
201 case ARM::fixup_arm_thumb_bcc: {
202 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
203 // low bit being an implied zero. There's an implied +4 offset for the
204 // branch, so we adjust the other way here to determine what's
207 // Relax if the value is too big for a (signed) i8.
208 int64_t Offset = int64_t(Value) - 4;
209 return Offset > 254 || Offset < -256;
211 case ARM::fixup_thumb_adr_pcrel_10:
212 case ARM::fixup_arm_thumb_cp: {
213 // If the immediate is negative, greater than 1020, or not a multiple
214 // of four, the wide version of the instruction must be used.
215 int64_t Offset = int64_t(Value) - 4;
216 return Offset > 1020 || Offset < 0 || Offset & 3;
219 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
222 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
223 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
225 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
226 if (RelaxedOp == Inst.getOpcode()) {
227 SmallString<256> Tmp;
228 raw_svector_ostream OS(Tmp);
229 Inst.dump_pretty(OS);
231 report_fatal_error("unexpected instruction to relax: " + OS.str());
234 // The instructions we're relaxing have (so far) the same operands.
235 // We just need to update to the proper opcode.
237 Res.setOpcode(RelaxedOp);
240 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
241 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
242 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
243 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
244 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
246 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
247 : Thumb1_16bitNopEncoding;
248 uint64_t NumNops = Count / 2;
249 for (uint64_t i = 0; i != NumNops; ++i)
250 OW->Write16(nopEncoding);
256 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
258 uint64_t NumNops = Count / 4;
259 for (uint64_t i = 0; i != NumNops; ++i)
260 OW->Write32(nopEncoding);
261 // FIXME: should this function return false when unable to write exactly
262 // 'Count' bytes with NOP encodings?
264 default: break; // No leftover bytes to write
265 case 1: OW->Write8(0); break;
266 case 2: OW->Write16(0); break;
267 case 3: OW->Write16(0); OW->Write8(0xa0); break;
273 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
276 llvm_unreachable("Unknown fixup kind!");
281 case ARM::fixup_arm_movt_hi16:
284 case ARM::fixup_arm_movw_lo16:
285 case ARM::fixup_arm_movt_hi16_pcrel:
286 case ARM::fixup_arm_movw_lo16_pcrel: {
287 unsigned Hi4 = (Value & 0xF000) >> 12;
288 unsigned Lo12 = Value & 0x0FFF;
289 // inst{19-16} = Hi4;
290 // inst{11-0} = Lo12;
291 Value = (Hi4 << 16) | (Lo12);
294 case ARM::fixup_t2_movt_hi16:
297 case ARM::fixup_t2_movw_lo16:
298 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
299 // the other hi16 fixup?
300 case ARM::fixup_t2_movw_lo16_pcrel: {
301 unsigned Hi4 = (Value & 0xF000) >> 12;
302 unsigned i = (Value & 0x800) >> 11;
303 unsigned Mid3 = (Value & 0x700) >> 8;
304 unsigned Lo8 = Value & 0x0FF;
305 // inst{19-16} = Hi4;
307 // inst{14-12} = Mid3;
309 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
310 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
311 swapped |= (Value & 0x0000FFFF) << 16;
314 case ARM::fixup_arm_ldst_pcrel_12:
315 // ARM PC-relative values are offset by 8.
318 case ARM::fixup_t2_ldst_pcrel_12: {
319 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
322 if ((int64_t)Value < 0) {
326 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
327 Value |= isAdd << 23;
329 // Same addressing mode as fixup_arm_pcrel_10,
330 // but with 16-bit halfwords swapped.
331 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
332 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
333 swapped |= (Value & 0x0000FFFF) << 16;
339 case ARM::fixup_thumb_adr_pcrel_10:
340 return ((Value - 4) >> 2) & 0xff;
341 case ARM::fixup_arm_adr_pcrel_12: {
342 // ARM PC-relative values are offset by 8.
344 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
345 if ((int64_t)Value < 0) {
349 assert(ARM_AM::getSOImmVal(Value) != -1 &&
350 "Out of range pc-relative fixup value!");
351 // Encode the immediate and shift the opcode into place.
352 return ARM_AM::getSOImmVal(Value) | (opc << 21);
355 case ARM::fixup_t2_adr_pcrel_12: {
358 if ((int64_t)Value < 0) {
363 uint32_t out = (opc << 21);
364 out |= (Value & 0x800) << 15;
365 out |= (Value & 0x700) << 4;
366 out |= (Value & 0x0FF);
368 uint64_t swapped = (out & 0xFFFF0000) >> 16;
369 swapped |= (out & 0x0000FFFF) << 16;
373 case ARM::fixup_arm_condbranch:
374 case ARM::fixup_arm_uncondbranch:
375 case ARM::fixup_arm_uncondbl:
376 case ARM::fixup_arm_condbl:
377 case ARM::fixup_arm_blx:
378 // These values don't encode the low two bits since they're always zero.
379 // Offset by 8 just as above.
380 return 0xffffff & ((Value - 8) >> 2);
381 case ARM::fixup_t2_uncondbranch: {
383 Value >>= 1; // Low bit is not encoded.
386 bool I = Value & 0x800000;
387 bool J1 = Value & 0x400000;
388 bool J2 = Value & 0x200000;
392 out |= I << 26; // S bit
393 out |= !J1 << 13; // J1 bit
394 out |= !J2 << 11; // J2 bit
395 out |= (Value & 0x1FF800) << 5; // imm6 field
396 out |= (Value & 0x0007FF); // imm11 field
398 uint64_t swapped = (out & 0xFFFF0000) >> 16;
399 swapped |= (out & 0x0000FFFF) << 16;
402 case ARM::fixup_t2_condbranch: {
404 Value >>= 1; // Low bit is not encoded.
407 out |= (Value & 0x80000) << 7; // S bit
408 out |= (Value & 0x40000) >> 7; // J2 bit
409 out |= (Value & 0x20000) >> 4; // J1 bit
410 out |= (Value & 0x1F800) << 5; // imm6 field
411 out |= (Value & 0x007FF); // imm11 field
413 uint32_t swapped = (out & 0xFFFF0000) >> 16;
414 swapped |= (out & 0x0000FFFF) << 16;
417 case ARM::fixup_arm_thumb_bl: {
418 // The value doesn't encode the low bit (always zero) and is offset by
419 // four. The value is encoded into disjoint bit positions in the destination
420 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
422 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
424 // Note that the halfwords are stored high first, low second; so we need
425 // to transpose the fixup value here to map properly.
426 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
428 Value = 0x3fffff & ((Value - 4) >> 1);
429 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
430 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
431 Binary |= isNeg << 10; // Sign bit.
434 case ARM::fixup_arm_thumb_blx: {
435 // The value doesn't encode the low two bits (always zero) and is offset by
436 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
437 // positions in the destination opcode. x = unchanged, I = immediate value
438 // bit, S = sign extension bit, 0 = zero.
440 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
442 // Note that the halfwords are stored high first, low second; so we need
443 // to transpose the fixup value here to map properly.
444 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
446 Value = 0xfffff & ((Value - 2) >> 2);
447 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
448 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
449 Binary |= isNeg << 10; // Sign bit.
452 case ARM::fixup_arm_thumb_cp:
453 // Offset by 4, and don't encode the low two bits. Two bytes of that
454 // 'off by 4' is implicitly handled by the half-word ordering of the
455 // Thumb encoding, so we only need to adjust by 2 here.
456 return ((Value - 2) >> 2) & 0xff;
457 case ARM::fixup_arm_thumb_cb: {
458 // Offset by 4 and don't encode the lower bit, which is always 0.
459 uint32_t Binary = (Value - 4) >> 1;
460 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
462 case ARM::fixup_arm_thumb_br:
463 // Offset by 4 and don't encode the lower bit, which is always 0.
464 return ((Value - 4) >> 1) & 0x7ff;
465 case ARM::fixup_arm_thumb_bcc:
466 // Offset by 4 and don't encode the lower bit, which is always 0.
467 return ((Value - 4) >> 1) & 0xff;
468 case ARM::fixup_arm_pcrel_10_unscaled: {
469 Value = Value - 8; // ARM fixups offset by an additional word and don't
470 // need to adjust for the half-word ordering.
472 if ((int64_t)Value < 0) {
476 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
477 assert ((Value < 256) && "Out of range pc-relative fixup value!");
478 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
479 return Value | (isAdd << 23);
481 case ARM::fixup_arm_pcrel_10:
482 Value = Value - 4; // ARM fixups offset by an additional word and don't
483 // need to adjust for the half-word ordering.
485 case ARM::fixup_t2_pcrel_10: {
486 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
489 if ((int64_t)Value < 0) {
493 // These values don't encode the low two bits since they're always zero.
495 assert ((Value < 256) && "Out of range pc-relative fixup value!");
496 Value |= isAdd << 23;
498 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
500 if (Kind == ARM::fixup_t2_pcrel_10) {
501 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
502 swapped |= (Value & 0x0000FFFF) << 16;
513 // FIXME: This should be in a separate file.
514 // ELF is an ELF of course...
515 class ELFARMAsmBackend : public ARMAsmBackend {
518 ELFARMAsmBackend(const Target &T, const StringRef TT,
520 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
522 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
523 uint64_t Value) const;
525 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
526 return createARMELFObjectWriter(OS, OSABI);
530 // FIXME: Raise this to share code between Darwin and ELF.
531 void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
532 unsigned DataSize, uint64_t Value) const {
533 unsigned NumBytes = 4; // FIXME: 2 for Thumb
534 Value = adjustFixupValue(Fixup.getKind(), Value);
535 if (!Value) return; // Doesn't change encoding.
537 unsigned Offset = Fixup.getOffset();
539 // For each byte of the fragment that the fixup touches, mask in the bits from
540 // the fixup value. The Value has been "split up" into the appropriate
542 for (unsigned i = 0; i != NumBytes; ++i)
543 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
546 // FIXME: This should be in a separate file.
547 class DarwinARMAsmBackend : public ARMAsmBackend {
549 const object::mach::CPUSubtypeARM Subtype;
550 DarwinARMAsmBackend(const Target &T, const StringRef TT,
551 object::mach::CPUSubtypeARM st)
552 : ARMAsmBackend(T, TT), Subtype(st) { }
554 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
555 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
556 object::mach::CTM_ARM,
560 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
561 uint64_t Value) const;
563 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
568 /// getFixupKindNumBytes - The number of bytes the fixup may change.
569 static unsigned getFixupKindNumBytes(unsigned Kind) {
572 llvm_unreachable("Unknown fixup kind!");
575 case ARM::fixup_arm_thumb_bcc:
576 case ARM::fixup_arm_thumb_cp:
577 case ARM::fixup_thumb_adr_pcrel_10:
581 case ARM::fixup_arm_thumb_br:
582 case ARM::fixup_arm_thumb_cb:
585 case ARM::fixup_arm_pcrel_10_unscaled:
586 case ARM::fixup_arm_ldst_pcrel_12:
587 case ARM::fixup_arm_pcrel_10:
588 case ARM::fixup_arm_adr_pcrel_12:
589 case ARM::fixup_arm_uncondbl:
590 case ARM::fixup_arm_condbl:
591 case ARM::fixup_arm_blx:
592 case ARM::fixup_arm_condbranch:
593 case ARM::fixup_arm_uncondbranch:
597 case ARM::fixup_t2_ldst_pcrel_12:
598 case ARM::fixup_t2_condbranch:
599 case ARM::fixup_t2_uncondbranch:
600 case ARM::fixup_t2_pcrel_10:
601 case ARM::fixup_t2_adr_pcrel_12:
602 case ARM::fixup_arm_thumb_bl:
603 case ARM::fixup_arm_thumb_blx:
604 case ARM::fixup_arm_movt_hi16:
605 case ARM::fixup_arm_movw_lo16:
606 case ARM::fixup_arm_movt_hi16_pcrel:
607 case ARM::fixup_arm_movw_lo16_pcrel:
608 case ARM::fixup_t2_movt_hi16:
609 case ARM::fixup_t2_movw_lo16:
610 case ARM::fixup_t2_movt_hi16_pcrel:
611 case ARM::fixup_t2_movw_lo16_pcrel:
616 void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
617 unsigned DataSize, uint64_t Value) const {
618 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
619 Value = adjustFixupValue(Fixup.getKind(), Value);
620 if (!Value) return; // Doesn't change encoding.
622 unsigned Offset = Fixup.getOffset();
623 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
625 // For each byte of the fragment that the fixup touches, mask in the
626 // bits from the fixup value.
627 for (unsigned i = 0; i != NumBytes; ++i)
628 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
631 } // end anonymous namespace
633 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
634 Triple TheTriple(TT);
636 if (TheTriple.isOSDarwin()) {
637 if (TheTriple.getArchName() == "armv4t" ||
638 TheTriple.getArchName() == "thumbv4t")
639 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
640 else if (TheTriple.getArchName() == "armv5e" ||
641 TheTriple.getArchName() == "thumbv5e")
642 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
643 else if (TheTriple.getArchName() == "armv6" ||
644 TheTriple.getArchName() == "thumbv6")
645 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
646 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
649 if (TheTriple.isOSWindows())
650 assert(0 && "Windows not supported on ARM");
652 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
653 return new ELFARMAsmBackend(T, TT, OSABI);