1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMFixupKinds.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCDirectives.h"
17 #include "llvm/MC/MCELFObjectWriter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCMachObjectWriter.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCValue.h"
26 #include "llvm/Object/MachOFormat.h"
27 #include "llvm/Support/ELF.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
33 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
35 ARMELFObjectWriter(uint8_t OSABI)
36 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
37 /*HasRelocationAddend*/ false) {}
40 class ARMAsmBackend : public MCAsmBackend {
41 const MCSubtargetInfo* STI;
42 bool isThumbMode; // Currently emitting Thumb code.
44 ARMAsmBackend(const Target &T, const StringRef TT)
45 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
46 isThumbMode(TT.startswith("thumb")) {}
52 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
55 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
58 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
59 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
60 // This table *must* be in the order that the fixup_* kinds are defined in
63 // Name Offset (bits) Size (bits) Flags
64 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
65 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
66 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
67 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
68 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
69 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
71 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
73 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
74 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
76 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
77 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_arm_bl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
84 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
85 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
86 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
87 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
88 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
89 { "fixup_arm_movt_hi16", 0, 20, 0 },
90 { "fixup_arm_movw_lo16", 0, 20, 0 },
91 { "fixup_t2_movt_hi16", 0, 20, 0 },
92 { "fixup_t2_movw_lo16", 0, 20, 0 },
93 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
94 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
95 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
96 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
99 if (Kind < FirstTargetFixupKind)
100 return MCAsmBackend::getFixupKindInfo(Kind);
102 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
104 return Infos[Kind - FirstTargetFixupKind];
107 /// processFixupValue - Target hook to process the literal value of a fixup
109 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
110 const MCFixup &Fixup, const MCFragment *DF,
111 MCValue &Target, uint64_t &Value,
113 const MCSymbolRefExpr *A = Target.getSymA();
114 // Some fixups to thumb function symbols need the low bit (thumb bit)
116 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
117 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
118 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
120 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
121 if (Asm.isThumbFunc(&Sym))
125 // We must always generate a relocation for BL/BLX instructions if we have
126 // a symbol to reference, as the linker relies on knowing the destination
127 // symbol's thumb-ness to get interworking right.
128 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
129 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||
130 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
131 (unsigned)Fixup.getKind() == ARM::fixup_arm_bl))
135 bool mayNeedRelaxation(const MCInst &Inst) const;
137 bool fixupNeedsRelaxation(const MCFixup &Fixup,
139 const MCInstFragment *DF,
140 const MCAsmLayout &Layout) const;
142 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
144 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
146 void handleAssemblerFlag(MCAssemblerFlag Flag) {
158 unsigned getPointerSize() const { return 4; }
159 bool isThumb() const { return isThumbMode; }
160 void setIsThumb(bool it) { isThumbMode = it; }
162 } // end anonymous namespace
164 static unsigned getRelaxedOpcode(unsigned Op) {
167 case ARM::tBcc: return ARM::t2Bcc;
168 case ARM::tLDRpciASM: return ARM::t2LDRpci;
169 case ARM::tADR: return ARM::t2ADR;
173 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
174 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
179 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
181 const MCInstFragment *DF,
182 const MCAsmLayout &Layout) const {
183 switch ((unsigned)Fixup.getKind()) {
184 case ARM::fixup_arm_thumb_bcc: {
185 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
186 // low bit being an implied zero. There's an implied +4 offset for the
187 // branch, so we adjust the other way here to determine what's
190 // Relax if the value is too big for a (signed) i8.
191 int64_t Offset = int64_t(Value) - 4;
192 return Offset > 254 || Offset < -256;
194 case ARM::fixup_thumb_adr_pcrel_10:
195 case ARM::fixup_arm_thumb_cp: {
196 // If the immediate is negative, greater than 1020, or not a multiple
197 // of four, the wide version of the instruction must be used.
198 int64_t Offset = int64_t(Value) - 4;
199 return Offset > 1020 || Offset < 0 || Offset & 3;
202 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
205 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
206 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
208 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
209 if (RelaxedOp == Inst.getOpcode()) {
210 SmallString<256> Tmp;
211 raw_svector_ostream OS(Tmp);
212 Inst.dump_pretty(OS);
214 report_fatal_error("unexpected instruction to relax: " + OS.str());
217 // The instructions we're relaxing have (so far) the same operands.
218 // We just need to update to the proper opcode.
220 Res.setOpcode(RelaxedOp);
223 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
224 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
225 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
226 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
227 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
229 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
230 : Thumb1_16bitNopEncoding;
231 uint64_t NumNops = Count / 2;
232 for (uint64_t i = 0; i != NumNops; ++i)
233 OW->Write16(nopEncoding);
239 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
241 uint64_t NumNops = Count / 4;
242 for (uint64_t i = 0; i != NumNops; ++i)
243 OW->Write32(nopEncoding);
244 // FIXME: should this function return false when unable to write exactly
245 // 'Count' bytes with NOP encodings?
247 default: break; // No leftover bytes to write
248 case 1: OW->Write8(0); break;
249 case 2: OW->Write16(0); break;
250 case 3: OW->Write16(0); OW->Write8(0xa0); break;
256 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
259 llvm_unreachable("Unknown fixup kind!");
264 case ARM::fixup_arm_movt_hi16:
267 case ARM::fixup_arm_movw_lo16:
268 case ARM::fixup_arm_movt_hi16_pcrel:
269 case ARM::fixup_arm_movw_lo16_pcrel: {
270 unsigned Hi4 = (Value & 0xF000) >> 12;
271 unsigned Lo12 = Value & 0x0FFF;
272 // inst{19-16} = Hi4;
273 // inst{11-0} = Lo12;
274 Value = (Hi4 << 16) | (Lo12);
277 case ARM::fixup_t2_movt_hi16:
280 case ARM::fixup_t2_movw_lo16:
281 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
282 // the other hi16 fixup?
283 case ARM::fixup_t2_movw_lo16_pcrel: {
284 unsigned Hi4 = (Value & 0xF000) >> 12;
285 unsigned i = (Value & 0x800) >> 11;
286 unsigned Mid3 = (Value & 0x700) >> 8;
287 unsigned Lo8 = Value & 0x0FF;
288 // inst{19-16} = Hi4;
290 // inst{14-12} = Mid3;
292 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
293 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
294 swapped |= (Value & 0x0000FFFF) << 16;
297 case ARM::fixup_arm_ldst_pcrel_12:
298 // ARM PC-relative values are offset by 8.
301 case ARM::fixup_t2_ldst_pcrel_12: {
302 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
305 if ((int64_t)Value < 0) {
309 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
310 Value |= isAdd << 23;
312 // Same addressing mode as fixup_arm_pcrel_10,
313 // but with 16-bit halfwords swapped.
314 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
315 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
316 swapped |= (Value & 0x0000FFFF) << 16;
322 case ARM::fixup_thumb_adr_pcrel_10:
323 return ((Value - 4) >> 2) & 0xff;
324 case ARM::fixup_arm_adr_pcrel_12: {
325 // ARM PC-relative values are offset by 8.
327 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
328 if ((int64_t)Value < 0) {
332 assert(ARM_AM::getSOImmVal(Value) != -1 &&
333 "Out of range pc-relative fixup value!");
334 // Encode the immediate and shift the opcode into place.
335 return ARM_AM::getSOImmVal(Value) | (opc << 21);
338 case ARM::fixup_t2_adr_pcrel_12: {
341 if ((int64_t)Value < 0) {
346 uint32_t out = (opc << 21);
347 out |= (Value & 0x800) << 15;
348 out |= (Value & 0x700) << 4;
349 out |= (Value & 0x0FF);
351 uint64_t swapped = (out & 0xFFFF0000) >> 16;
352 swapped |= (out & 0x0000FFFF) << 16;
356 case ARM::fixup_arm_condbranch:
357 case ARM::fixup_arm_uncondbranch:
358 case ARM::fixup_arm_bl:
359 case ARM::fixup_arm_blx:
360 // These values don't encode the low two bits since they're always zero.
361 // Offset by 8 just as above.
362 return 0xffffff & ((Value - 8) >> 2);
363 case ARM::fixup_t2_uncondbranch: {
365 Value >>= 1; // Low bit is not encoded.
368 bool I = Value & 0x800000;
369 bool J1 = Value & 0x400000;
370 bool J2 = Value & 0x200000;
374 out |= I << 26; // S bit
375 out |= !J1 << 13; // J1 bit
376 out |= !J2 << 11; // J2 bit
377 out |= (Value & 0x1FF800) << 5; // imm6 field
378 out |= (Value & 0x0007FF); // imm11 field
380 uint64_t swapped = (out & 0xFFFF0000) >> 16;
381 swapped |= (out & 0x0000FFFF) << 16;
384 case ARM::fixup_t2_condbranch: {
386 Value >>= 1; // Low bit is not encoded.
389 out |= (Value & 0x80000) << 7; // S bit
390 out |= (Value & 0x40000) >> 7; // J2 bit
391 out |= (Value & 0x20000) >> 4; // J1 bit
392 out |= (Value & 0x1F800) << 5; // imm6 field
393 out |= (Value & 0x007FF); // imm11 field
395 uint32_t swapped = (out & 0xFFFF0000) >> 16;
396 swapped |= (out & 0x0000FFFF) << 16;
399 case ARM::fixup_arm_thumb_bl: {
400 // The value doesn't encode the low bit (always zero) and is offset by
401 // four. The value is encoded into disjoint bit positions in the destination
402 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
404 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
406 // Note that the halfwords are stored high first, low second; so we need
407 // to transpose the fixup value here to map properly.
408 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
410 Value = 0x3fffff & ((Value - 4) >> 1);
411 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
412 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
413 Binary |= isNeg << 10; // Sign bit.
416 case ARM::fixup_arm_thumb_blx: {
417 // The value doesn't encode the low two bits (always zero) and is offset by
418 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
419 // positions in the destination opcode. x = unchanged, I = immediate value
420 // bit, S = sign extension bit, 0 = zero.
422 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
424 // Note that the halfwords are stored high first, low second; so we need
425 // to transpose the fixup value here to map properly.
426 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
428 Value = 0xfffff & ((Value - 2) >> 2);
429 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
430 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
431 Binary |= isNeg << 10; // Sign bit.
434 case ARM::fixup_arm_thumb_cp:
435 // Offset by 4, and don't encode the low two bits. Two bytes of that
436 // 'off by 4' is implicitly handled by the half-word ordering of the
437 // Thumb encoding, so we only need to adjust by 2 here.
438 return ((Value - 2) >> 2) & 0xff;
439 case ARM::fixup_arm_thumb_cb: {
440 // Offset by 4 and don't encode the lower bit, which is always 0.
441 uint32_t Binary = (Value - 4) >> 1;
442 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
444 case ARM::fixup_arm_thumb_br:
445 // Offset by 4 and don't encode the lower bit, which is always 0.
446 return ((Value - 4) >> 1) & 0x7ff;
447 case ARM::fixup_arm_thumb_bcc:
448 // Offset by 4 and don't encode the lower bit, which is always 0.
449 return ((Value - 4) >> 1) & 0xff;
450 case ARM::fixup_arm_pcrel_10_unscaled: {
451 Value = Value - 8; // ARM fixups offset by an additional word and don't
452 // need to adjust for the half-word ordering.
454 if ((int64_t)Value < 0) {
458 assert ((Value < 256) && "Out of range pc-relative fixup value!");
459 return Value | (isAdd << 23);
461 case ARM::fixup_arm_pcrel_10:
462 Value = Value - 4; // ARM fixups offset by an additional word and don't
463 // need to adjust for the half-word ordering.
465 case ARM::fixup_t2_pcrel_10: {
466 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
469 if ((int64_t)Value < 0) {
473 // These values don't encode the low two bits since they're always zero.
475 assert ((Value < 256) && "Out of range pc-relative fixup value!");
476 Value |= isAdd << 23;
478 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
480 if (Kind == ARM::fixup_t2_pcrel_10) {
481 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
482 swapped |= (Value & 0x0000FFFF) << 16;
493 // FIXME: This should be in a separate file.
494 // ELF is an ELF of course...
495 class ELFARMAsmBackend : public ARMAsmBackend {
498 ELFARMAsmBackend(const Target &T, const StringRef TT,
500 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
502 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
503 uint64_t Value) const;
505 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
506 return createARMELFObjectWriter(OS, OSABI);
510 // FIXME: Raise this to share code between Darwin and ELF.
511 void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
512 unsigned DataSize, uint64_t Value) const {
513 unsigned NumBytes = 4; // FIXME: 2 for Thumb
514 Value = adjustFixupValue(Fixup.getKind(), Value);
515 if (!Value) return; // Doesn't change encoding.
517 unsigned Offset = Fixup.getOffset();
519 // For each byte of the fragment that the fixup touches, mask in the bits from
520 // the fixup value. The Value has been "split up" into the appropriate
522 for (unsigned i = 0; i != NumBytes; ++i)
523 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
526 // FIXME: This should be in a separate file.
527 class DarwinARMAsmBackend : public ARMAsmBackend {
529 const object::mach::CPUSubtypeARM Subtype;
530 DarwinARMAsmBackend(const Target &T, const StringRef TT,
531 object::mach::CPUSubtypeARM st)
532 : ARMAsmBackend(T, TT), Subtype(st) { }
534 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
535 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
536 object::mach::CTM_ARM,
540 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
541 uint64_t Value) const;
543 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
548 /// getFixupKindNumBytes - The number of bytes the fixup may change.
549 static unsigned getFixupKindNumBytes(unsigned Kind) {
552 llvm_unreachable("Unknown fixup kind!");
555 case ARM::fixup_arm_thumb_bcc:
556 case ARM::fixup_arm_thumb_cp:
557 case ARM::fixup_thumb_adr_pcrel_10:
561 case ARM::fixup_arm_thumb_br:
562 case ARM::fixup_arm_thumb_cb:
565 case ARM::fixup_arm_pcrel_10_unscaled:
566 case ARM::fixup_arm_ldst_pcrel_12:
567 case ARM::fixup_arm_pcrel_10:
568 case ARM::fixup_arm_adr_pcrel_12:
569 case ARM::fixup_arm_bl:
570 case ARM::fixup_arm_blx:
571 case ARM::fixup_arm_condbranch:
572 case ARM::fixup_arm_uncondbranch:
576 case ARM::fixup_t2_ldst_pcrel_12:
577 case ARM::fixup_t2_condbranch:
578 case ARM::fixup_t2_uncondbranch:
579 case ARM::fixup_t2_pcrel_10:
580 case ARM::fixup_t2_adr_pcrel_12:
581 case ARM::fixup_arm_thumb_bl:
582 case ARM::fixup_arm_thumb_blx:
583 case ARM::fixup_arm_movt_hi16:
584 case ARM::fixup_arm_movw_lo16:
585 case ARM::fixup_arm_movt_hi16_pcrel:
586 case ARM::fixup_arm_movw_lo16_pcrel:
587 case ARM::fixup_t2_movt_hi16:
588 case ARM::fixup_t2_movw_lo16:
589 case ARM::fixup_t2_movt_hi16_pcrel:
590 case ARM::fixup_t2_movw_lo16_pcrel:
595 void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
596 unsigned DataSize, uint64_t Value) const {
597 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
598 Value = adjustFixupValue(Fixup.getKind(), Value);
599 if (!Value) return; // Doesn't change encoding.
601 unsigned Offset = Fixup.getOffset();
602 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
604 // For each byte of the fragment that the fixup touches, mask in the
605 // bits from the fixup value.
606 for (unsigned i = 0; i != NumBytes; ++i)
607 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
610 } // end anonymous namespace
612 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
613 Triple TheTriple(TT);
615 if (TheTriple.isOSDarwin()) {
616 if (TheTriple.getArchName() == "armv4t" ||
617 TheTriple.getArchName() == "thumbv4t")
618 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
619 else if (TheTriple.getArchName() == "armv5e" ||
620 TheTriple.getArchName() == "thumbv5e")
621 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
622 else if (TheTriple.getArchName() == "armv6" ||
623 TheTriple.getArchName() == "thumbv6")
624 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
625 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
628 if (TheTriple.isOSWindows())
629 assert(0 && "Windows not supported on ARM");
631 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
632 return new ELFARMAsmBackend(T, TT, OSABI);