1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMFixupKinds.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCDirectives.h"
17 #include "llvm/MC/MCELFObjectWriter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCMachObjectWriter.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCValue.h"
26 #include "llvm/Object/MachOFormat.h"
27 #include "llvm/Support/ELF.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
33 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
35 ARMELFObjectWriter(uint8_t OSABI)
36 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
37 /*HasRelocationAddend*/ false) {}
40 class ARMAsmBackend : public MCAsmBackend {
41 const MCSubtargetInfo* STI;
42 bool isThumbMode; // Currently emitting Thumb code.
44 ARMAsmBackend(const Target &T, const StringRef TT)
45 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
46 isThumbMode(TT.startswith("thumb")) {}
52 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
55 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
58 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
59 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
60 // This table *must* be in the order that the fixup_* kinds are defined in
63 // Name Offset (bits) Size (bits) Flags
64 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
65 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
66 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
67 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
68 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
69 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
71 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
73 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
74 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
76 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
77 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
84 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
85 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
86 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
87 { "fixup_arm_movt_hi16", 0, 20, 0 },
88 { "fixup_arm_movw_lo16", 0, 20, 0 },
89 { "fixup_t2_movt_hi16", 0, 20, 0 },
90 { "fixup_t2_movw_lo16", 0, 20, 0 },
91 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
92 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
93 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
94 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
97 if (Kind < FirstTargetFixupKind)
98 return MCAsmBackend::getFixupKindInfo(Kind);
100 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
102 return Infos[Kind - FirstTargetFixupKind];
105 /// processFixupValue - Target hook to process the literal value of a fixup
107 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
108 const MCFixup &Fixup, const MCFragment *DF,
109 MCValue &Target, uint64_t &Value) {
110 // Some fixups to thumb function symbols need the low bit (thumb bit)
112 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
113 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
114 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
115 if (const MCSymbolRefExpr *A = Target.getSymA()) {
116 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
117 if (Asm.isThumbFunc(&Sym))
123 bool MayNeedRelaxation(const MCInst &Inst) const;
125 bool fixupNeedsRelaxation(const MCFixup &Fixup,
127 const MCInstFragment *DF,
128 const MCAsmLayout &Layout) const;
130 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
132 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
134 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
146 unsigned getPointerSize() const { return 4; }
147 bool isThumb() const { return isThumbMode; }
148 void setIsThumb(bool it) { isThumbMode = it; }
150 } // end anonymous namespace
152 static unsigned getRelaxedOpcode(unsigned Op) {
155 case ARM::tBcc: return ARM::t2Bcc;
159 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
160 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
165 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
167 const MCInstFragment *DF,
168 const MCAsmLayout &Layout) const {
169 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
170 // low bit being an implied zero. There's an implied +4 offset for the
171 // branch, so we adjust the other way here to determine what's
174 // Relax if the value is too big for a (signed) i8.
175 int64_t Offset = int64_t(Value) - 4;
176 return Offset > 254 || Offset < -256;
179 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
180 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
182 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
183 if (RelaxedOp == Inst.getOpcode()) {
184 SmallString<256> Tmp;
185 raw_svector_ostream OS(Tmp);
186 Inst.dump_pretty(OS);
188 report_fatal_error("unexpected instruction to relax: " + OS.str());
191 // The instructions we're relaxing have (so far) the same operands.
192 // We just need to update to the proper opcode.
194 Res.setOpcode(RelaxedOp);
197 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
198 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
199 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
200 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
201 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
203 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
204 : Thumb1_16bitNopEncoding;
205 uint64_t NumNops = Count / 2;
206 for (uint64_t i = 0; i != NumNops; ++i)
207 OW->Write16(nopEncoding);
213 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
215 uint64_t NumNops = Count / 4;
216 for (uint64_t i = 0; i != NumNops; ++i)
217 OW->Write32(nopEncoding);
218 // FIXME: should this function return false when unable to write exactly
219 // 'Count' bytes with NOP encodings?
221 default: break; // No leftover bytes to write
222 case 1: OW->Write8(0); break;
223 case 2: OW->Write16(0); break;
224 case 3: OW->Write16(0); OW->Write8(0xa0); break;
230 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
233 llvm_unreachable("Unknown fixup kind!");
238 case ARM::fixup_arm_movt_hi16:
241 case ARM::fixup_arm_movw_lo16:
242 case ARM::fixup_arm_movt_hi16_pcrel:
243 case ARM::fixup_arm_movw_lo16_pcrel: {
244 unsigned Hi4 = (Value & 0xF000) >> 12;
245 unsigned Lo12 = Value & 0x0FFF;
246 // inst{19-16} = Hi4;
247 // inst{11-0} = Lo12;
248 Value = (Hi4 << 16) | (Lo12);
251 case ARM::fixup_t2_movt_hi16:
254 case ARM::fixup_t2_movw_lo16:
255 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
256 // the other hi16 fixup?
257 case ARM::fixup_t2_movw_lo16_pcrel: {
258 unsigned Hi4 = (Value & 0xF000) >> 12;
259 unsigned i = (Value & 0x800) >> 11;
260 unsigned Mid3 = (Value & 0x700) >> 8;
261 unsigned Lo8 = Value & 0x0FF;
262 // inst{19-16} = Hi4;
264 // inst{14-12} = Mid3;
266 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
267 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
268 swapped |= (Value & 0x0000FFFF) << 16;
271 case ARM::fixup_arm_ldst_pcrel_12:
272 // ARM PC-relative values are offset by 8.
275 case ARM::fixup_t2_ldst_pcrel_12: {
276 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
279 if ((int64_t)Value < 0) {
283 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
284 Value |= isAdd << 23;
286 // Same addressing mode as fixup_arm_pcrel_10,
287 // but with 16-bit halfwords swapped.
288 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
289 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
290 swapped |= (Value & 0x0000FFFF) << 16;
296 case ARM::fixup_thumb_adr_pcrel_10:
297 return ((Value - 4) >> 2) & 0xff;
298 case ARM::fixup_arm_adr_pcrel_12: {
299 // ARM PC-relative values are offset by 8.
301 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
302 if ((int64_t)Value < 0) {
306 assert(ARM_AM::getSOImmVal(Value) != -1 &&
307 "Out of range pc-relative fixup value!");
308 // Encode the immediate and shift the opcode into place.
309 return ARM_AM::getSOImmVal(Value) | (opc << 21);
312 case ARM::fixup_t2_adr_pcrel_12: {
315 if ((int64_t)Value < 0) {
320 uint32_t out = (opc << 21);
321 out |= (Value & 0x800) << 15;
322 out |= (Value & 0x700) << 4;
323 out |= (Value & 0x0FF);
325 uint64_t swapped = (out & 0xFFFF0000) >> 16;
326 swapped |= (out & 0x0000FFFF) << 16;
330 case ARM::fixup_arm_condbranch:
331 case ARM::fixup_arm_uncondbranch:
332 // These values don't encode the low two bits since they're always zero.
333 // Offset by 8 just as above.
334 return 0xffffff & ((Value - 8) >> 2);
335 case ARM::fixup_t2_uncondbranch: {
337 Value >>= 1; // Low bit is not encoded.
340 bool I = Value & 0x800000;
341 bool J1 = Value & 0x400000;
342 bool J2 = Value & 0x200000;
346 out |= I << 26; // S bit
347 out |= !J1 << 13; // J1 bit
348 out |= !J2 << 11; // J2 bit
349 out |= (Value & 0x1FF800) << 5; // imm6 field
350 out |= (Value & 0x0007FF); // imm11 field
352 uint64_t swapped = (out & 0xFFFF0000) >> 16;
353 swapped |= (out & 0x0000FFFF) << 16;
356 case ARM::fixup_t2_condbranch: {
358 Value >>= 1; // Low bit is not encoded.
361 out |= (Value & 0x80000) << 7; // S bit
362 out |= (Value & 0x40000) >> 7; // J2 bit
363 out |= (Value & 0x20000) >> 4; // J1 bit
364 out |= (Value & 0x1F800) << 5; // imm6 field
365 out |= (Value & 0x007FF); // imm11 field
367 uint32_t swapped = (out & 0xFFFF0000) >> 16;
368 swapped |= (out & 0x0000FFFF) << 16;
371 case ARM::fixup_arm_thumb_bl: {
372 // The value doesn't encode the low bit (always zero) and is offset by
373 // four. The value is encoded into disjoint bit positions in the destination
374 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
376 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
378 // Note that the halfwords are stored high first, low second; so we need
379 // to transpose the fixup value here to map properly.
380 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
382 Value = 0x3fffff & ((Value - 4) >> 1);
383 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
384 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
385 Binary |= isNeg << 10; // Sign bit.
388 case ARM::fixup_arm_thumb_blx: {
389 // The value doesn't encode the low two bits (always zero) and is offset by
390 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
391 // positions in the destination opcode. x = unchanged, I = immediate value
392 // bit, S = sign extension bit, 0 = zero.
394 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
396 // Note that the halfwords are stored high first, low second; so we need
397 // to transpose the fixup value here to map properly.
398 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
400 Value = 0xfffff & ((Value - 2) >> 2);
401 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
402 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
403 Binary |= isNeg << 10; // Sign bit.
406 case ARM::fixup_arm_thumb_cp:
407 // Offset by 4, and don't encode the low two bits. Two bytes of that
408 // 'off by 4' is implicitly handled by the half-word ordering of the
409 // Thumb encoding, so we only need to adjust by 2 here.
410 return ((Value - 2) >> 2) & 0xff;
411 case ARM::fixup_arm_thumb_cb: {
412 // Offset by 4 and don't encode the lower bit, which is always 0.
413 uint32_t Binary = (Value - 4) >> 1;
414 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
416 case ARM::fixup_arm_thumb_br:
417 // Offset by 4 and don't encode the lower bit, which is always 0.
418 return ((Value - 4) >> 1) & 0x7ff;
419 case ARM::fixup_arm_thumb_bcc:
420 // Offset by 4 and don't encode the lower bit, which is always 0.
421 return ((Value - 4) >> 1) & 0xff;
422 case ARM::fixup_arm_pcrel_10_unscaled: {
423 Value = Value - 8; // ARM fixups offset by an additional word and don't
424 // need to adjust for the half-word ordering.
426 if ((int64_t)Value < 0) {
430 assert ((Value < 256) && "Out of range pc-relative fixup value!");
431 return Value | (isAdd << 23);
433 case ARM::fixup_arm_pcrel_10:
434 Value = Value - 4; // ARM fixups offset by an additional word and don't
435 // need to adjust for the half-word ordering.
437 case ARM::fixup_t2_pcrel_10: {
438 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
441 if ((int64_t)Value < 0) {
445 // These values don't encode the low two bits since they're always zero.
447 assert ((Value < 256) && "Out of range pc-relative fixup value!");
448 Value |= isAdd << 23;
450 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
452 if (Kind == ARM::fixup_t2_pcrel_10) {
453 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
454 swapped |= (Value & 0x0000FFFF) << 16;
465 // FIXME: This should be in a separate file.
466 // ELF is an ELF of course...
467 class ELFARMAsmBackend : public ARMAsmBackend {
470 ELFARMAsmBackend(const Target &T, const StringRef TT,
472 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
474 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
475 uint64_t Value) const;
477 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
478 return createARMELFObjectWriter(OS, OSABI);
482 // FIXME: Raise this to share code between Darwin and ELF.
483 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
484 unsigned DataSize, uint64_t Value) const {
485 unsigned NumBytes = 4; // FIXME: 2 for Thumb
486 Value = adjustFixupValue(Fixup.getKind(), Value);
487 if (!Value) return; // Doesn't change encoding.
489 unsigned Offset = Fixup.getOffset();
491 // For each byte of the fragment that the fixup touches, mask in the bits from
492 // the fixup value. The Value has been "split up" into the appropriate
494 for (unsigned i = 0; i != NumBytes; ++i)
495 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
498 // FIXME: This should be in a separate file.
499 class DarwinARMAsmBackend : public ARMAsmBackend {
501 const object::mach::CPUSubtypeARM Subtype;
502 DarwinARMAsmBackend(const Target &T, const StringRef TT,
503 object::mach::CPUSubtypeARM st)
504 : ARMAsmBackend(T, TT), Subtype(st) { }
506 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
507 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
508 object::mach::CTM_ARM,
512 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
513 uint64_t Value) const;
515 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
520 /// getFixupKindNumBytes - The number of bytes the fixup may change.
521 static unsigned getFixupKindNumBytes(unsigned Kind) {
524 llvm_unreachable("Unknown fixup kind!");
527 case ARM::fixup_arm_thumb_bcc:
528 case ARM::fixup_arm_thumb_cp:
529 case ARM::fixup_thumb_adr_pcrel_10:
533 case ARM::fixup_arm_thumb_br:
534 case ARM::fixup_arm_thumb_cb:
537 case ARM::fixup_arm_pcrel_10_unscaled:
538 case ARM::fixup_arm_ldst_pcrel_12:
539 case ARM::fixup_arm_pcrel_10:
540 case ARM::fixup_arm_adr_pcrel_12:
541 case ARM::fixup_arm_condbranch:
542 case ARM::fixup_arm_uncondbranch:
546 case ARM::fixup_t2_ldst_pcrel_12:
547 case ARM::fixup_t2_condbranch:
548 case ARM::fixup_t2_uncondbranch:
549 case ARM::fixup_t2_pcrel_10:
550 case ARM::fixup_t2_adr_pcrel_12:
551 case ARM::fixup_arm_thumb_bl:
552 case ARM::fixup_arm_thumb_blx:
553 case ARM::fixup_arm_movt_hi16:
554 case ARM::fixup_arm_movw_lo16:
555 case ARM::fixup_arm_movt_hi16_pcrel:
556 case ARM::fixup_arm_movw_lo16_pcrel:
557 case ARM::fixup_t2_movt_hi16:
558 case ARM::fixup_t2_movw_lo16:
559 case ARM::fixup_t2_movt_hi16_pcrel:
560 case ARM::fixup_t2_movw_lo16_pcrel:
565 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
566 unsigned DataSize, uint64_t Value) const {
567 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
568 Value = adjustFixupValue(Fixup.getKind(), Value);
569 if (!Value) return; // Doesn't change encoding.
571 unsigned Offset = Fixup.getOffset();
572 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
574 // For each byte of the fragment that the fixup touches, mask in the
575 // bits from the fixup value.
576 for (unsigned i = 0; i != NumBytes; ++i)
577 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
580 } // end anonymous namespace
582 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
583 Triple TheTriple(TT);
585 if (TheTriple.isOSDarwin()) {
586 if (TheTriple.getArchName() == "armv4t" ||
587 TheTriple.getArchName() == "thumbv4t")
588 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
589 else if (TheTriple.getArchName() == "armv5e" ||
590 TheTriple.getArchName() == "thumbv5e")
591 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
592 else if (TheTriple.getArchName() == "armv6" ||
593 TheTriple.getArchName() == "thumbv6")
594 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
595 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
598 if (TheTriple.isOSWindows())
599 assert(0 && "Windows not supported on ARM");
601 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
602 return new ELFARMAsmBackend(T, TT, OSABI);