1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMFixupKinds.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCELFObjectWriter.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCFixupKindInfo.h"
19 #include "llvm/MC/MCMachObjectWriter.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCValue.h"
26 #include "llvm/Object/MachOFormat.h"
27 #include "llvm/Support/ELF.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
33 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
35 ARMELFObjectWriter(uint8_t OSABI)
36 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
37 /*HasRelocationAddend*/ false) {}
40 class ARMAsmBackend : public MCAsmBackend {
41 const MCSubtargetInfo* STI;
42 bool isThumbMode; // Currently emitting Thumb code.
44 ARMAsmBackend(const Target &T, const StringRef TT)
45 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
46 isThumbMode(TT.startswith("thumb")) {}
52 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
55 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
58 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
59 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
60 // This table *must* be in the order that the fixup_* kinds are defined in
63 // Name Offset (bits) Size (bits) Flags
64 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
65 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
66 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
67 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
68 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
69 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
71 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
73 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
74 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
76 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
77 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_arm_bl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
84 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
85 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
86 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
87 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
88 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
89 { "fixup_arm_movt_hi16", 0, 20, 0 },
90 { "fixup_arm_movw_lo16", 0, 20, 0 },
91 { "fixup_t2_movt_hi16", 0, 20, 0 },
92 { "fixup_t2_movw_lo16", 0, 20, 0 },
93 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
94 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
95 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
96 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
99 if (Kind < FirstTargetFixupKind)
100 return MCAsmBackend::getFixupKindInfo(Kind);
102 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
104 return Infos[Kind - FirstTargetFixupKind];
107 /// processFixupValue - Target hook to process the literal value of a fixup
109 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
110 const MCFixup &Fixup, const MCFragment *DF,
111 MCValue &Target, uint64_t &Value,
113 const MCSymbolRefExpr *A = Target.getSymA();
114 // Some fixups to thumb function symbols need the low bit (thumb bit)
116 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
117 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
118 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
120 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
121 if (Asm.isThumbFunc(&Sym))
125 // We must always generate a relocation for BL/BLX instructions if we have
126 // a symbol to reference, as the linker relies on knowing the destination
127 // symbol's thumb-ness to get interworking right.
128 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
129 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||
130 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
131 (unsigned)Fixup.getKind() == ARM::fixup_arm_bl))
135 bool mayNeedRelaxation(const MCInst &Inst) const;
137 bool fixupNeedsRelaxation(const MCFixup &Fixup,
139 const MCInstFragment *DF,
140 const MCAsmLayout &Layout) const;
142 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
144 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
146 void handleAssemblerFlag(MCAssemblerFlag Flag) {
158 unsigned getPointerSize() const { return 4; }
159 bool isThumb() const { return isThumbMode; }
160 void setIsThumb(bool it) { isThumbMode = it; }
162 } // end anonymous namespace
164 static unsigned getRelaxedOpcode(unsigned Op) {
167 case ARM::tBcc: return ARM::t2Bcc;
168 case ARM::tLDRpciASM: return ARM::t2LDRpci;
169 case ARM::tADR: return ARM::t2ADR;
170 case ARM::tB: return ARM::t2B;
174 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
175 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
180 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
182 const MCInstFragment *DF,
183 const MCAsmLayout &Layout) const {
184 switch ((unsigned)Fixup.getKind()) {
185 case ARM::fixup_arm_thumb_br: {
186 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
187 // low bit being an implied zero. There's an implied +4 offset for the
188 // branch, so we adjust the other way here to determine what's
191 // Relax if the value is too big for a (signed) i8.
192 int64_t Offset = int64_t(Value) - 4;
193 return Offset > 2046 || Offset < -2048;
195 case ARM::fixup_arm_thumb_bcc: {
196 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
197 // low bit being an implied zero. There's an implied +4 offset for the
198 // branch, so we adjust the other way here to determine what's
201 // Relax if the value is too big for a (signed) i8.
202 int64_t Offset = int64_t(Value) - 4;
203 return Offset > 254 || Offset < -256;
205 case ARM::fixup_thumb_adr_pcrel_10:
206 case ARM::fixup_arm_thumb_cp: {
207 // If the immediate is negative, greater than 1020, or not a multiple
208 // of four, the wide version of the instruction must be used.
209 int64_t Offset = int64_t(Value) - 4;
210 return Offset > 1020 || Offset < 0 || Offset & 3;
213 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
216 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
217 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
219 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
220 if (RelaxedOp == Inst.getOpcode()) {
221 SmallString<256> Tmp;
222 raw_svector_ostream OS(Tmp);
223 Inst.dump_pretty(OS);
225 report_fatal_error("unexpected instruction to relax: " + OS.str());
228 // The instructions we're relaxing have (so far) the same operands.
229 // We just need to update to the proper opcode.
231 Res.setOpcode(RelaxedOp);
234 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
235 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
236 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
237 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
238 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
240 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
241 : Thumb1_16bitNopEncoding;
242 uint64_t NumNops = Count / 2;
243 for (uint64_t i = 0; i != NumNops; ++i)
244 OW->Write16(nopEncoding);
250 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
252 uint64_t NumNops = Count / 4;
253 for (uint64_t i = 0; i != NumNops; ++i)
254 OW->Write32(nopEncoding);
255 // FIXME: should this function return false when unable to write exactly
256 // 'Count' bytes with NOP encodings?
258 default: break; // No leftover bytes to write
259 case 1: OW->Write8(0); break;
260 case 2: OW->Write16(0); break;
261 case 3: OW->Write16(0); OW->Write8(0xa0); break;
267 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
270 llvm_unreachable("Unknown fixup kind!");
275 case ARM::fixup_arm_movt_hi16:
278 case ARM::fixup_arm_movw_lo16:
279 case ARM::fixup_arm_movt_hi16_pcrel:
280 case ARM::fixup_arm_movw_lo16_pcrel: {
281 unsigned Hi4 = (Value & 0xF000) >> 12;
282 unsigned Lo12 = Value & 0x0FFF;
283 // inst{19-16} = Hi4;
284 // inst{11-0} = Lo12;
285 Value = (Hi4 << 16) | (Lo12);
288 case ARM::fixup_t2_movt_hi16:
291 case ARM::fixup_t2_movw_lo16:
292 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
293 // the other hi16 fixup?
294 case ARM::fixup_t2_movw_lo16_pcrel: {
295 unsigned Hi4 = (Value & 0xF000) >> 12;
296 unsigned i = (Value & 0x800) >> 11;
297 unsigned Mid3 = (Value & 0x700) >> 8;
298 unsigned Lo8 = Value & 0x0FF;
299 // inst{19-16} = Hi4;
301 // inst{14-12} = Mid3;
303 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
304 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
305 swapped |= (Value & 0x0000FFFF) << 16;
308 case ARM::fixup_arm_ldst_pcrel_12:
309 // ARM PC-relative values are offset by 8.
312 case ARM::fixup_t2_ldst_pcrel_12: {
313 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
316 if ((int64_t)Value < 0) {
320 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
321 Value |= isAdd << 23;
323 // Same addressing mode as fixup_arm_pcrel_10,
324 // but with 16-bit halfwords swapped.
325 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
326 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
327 swapped |= (Value & 0x0000FFFF) << 16;
333 case ARM::fixup_thumb_adr_pcrel_10:
334 return ((Value - 4) >> 2) & 0xff;
335 case ARM::fixup_arm_adr_pcrel_12: {
336 // ARM PC-relative values are offset by 8.
338 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
339 if ((int64_t)Value < 0) {
343 assert(ARM_AM::getSOImmVal(Value) != -1 &&
344 "Out of range pc-relative fixup value!");
345 // Encode the immediate and shift the opcode into place.
346 return ARM_AM::getSOImmVal(Value) | (opc << 21);
349 case ARM::fixup_t2_adr_pcrel_12: {
352 if ((int64_t)Value < 0) {
357 uint32_t out = (opc << 21);
358 out |= (Value & 0x800) << 15;
359 out |= (Value & 0x700) << 4;
360 out |= (Value & 0x0FF);
362 uint64_t swapped = (out & 0xFFFF0000) >> 16;
363 swapped |= (out & 0x0000FFFF) << 16;
367 case ARM::fixup_arm_condbranch:
368 case ARM::fixup_arm_uncondbranch:
369 case ARM::fixup_arm_bl:
370 case ARM::fixup_arm_blx:
371 // These values don't encode the low two bits since they're always zero.
372 // Offset by 8 just as above.
373 return 0xffffff & ((Value - 8) >> 2);
374 case ARM::fixup_t2_uncondbranch: {
376 Value >>= 1; // Low bit is not encoded.
379 bool I = Value & 0x800000;
380 bool J1 = Value & 0x400000;
381 bool J2 = Value & 0x200000;
385 out |= I << 26; // S bit
386 out |= !J1 << 13; // J1 bit
387 out |= !J2 << 11; // J2 bit
388 out |= (Value & 0x1FF800) << 5; // imm6 field
389 out |= (Value & 0x0007FF); // imm11 field
391 uint64_t swapped = (out & 0xFFFF0000) >> 16;
392 swapped |= (out & 0x0000FFFF) << 16;
395 case ARM::fixup_t2_condbranch: {
397 Value >>= 1; // Low bit is not encoded.
400 out |= (Value & 0x80000) << 7; // S bit
401 out |= (Value & 0x40000) >> 7; // J2 bit
402 out |= (Value & 0x20000) >> 4; // J1 bit
403 out |= (Value & 0x1F800) << 5; // imm6 field
404 out |= (Value & 0x007FF); // imm11 field
406 uint32_t swapped = (out & 0xFFFF0000) >> 16;
407 swapped |= (out & 0x0000FFFF) << 16;
410 case ARM::fixup_arm_thumb_bl: {
411 // The value doesn't encode the low bit (always zero) and is offset by
412 // four. The value is encoded into disjoint bit positions in the destination
413 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
415 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
417 // Note that the halfwords are stored high first, low second; so we need
418 // to transpose the fixup value here to map properly.
419 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
421 Value = 0x3fffff & ((Value - 4) >> 1);
422 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
423 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
424 Binary |= isNeg << 10; // Sign bit.
427 case ARM::fixup_arm_thumb_blx: {
428 // The value doesn't encode the low two bits (always zero) and is offset by
429 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
430 // positions in the destination opcode. x = unchanged, I = immediate value
431 // bit, S = sign extension bit, 0 = zero.
433 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
435 // Note that the halfwords are stored high first, low second; so we need
436 // to transpose the fixup value here to map properly.
437 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
439 Value = 0xfffff & ((Value - 2) >> 2);
440 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
441 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
442 Binary |= isNeg << 10; // Sign bit.
445 case ARM::fixup_arm_thumb_cp:
446 // Offset by 4, and don't encode the low two bits. Two bytes of that
447 // 'off by 4' is implicitly handled by the half-word ordering of the
448 // Thumb encoding, so we only need to adjust by 2 here.
449 return ((Value - 2) >> 2) & 0xff;
450 case ARM::fixup_arm_thumb_cb: {
451 // Offset by 4 and don't encode the lower bit, which is always 0.
452 uint32_t Binary = (Value - 4) >> 1;
453 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
455 case ARM::fixup_arm_thumb_br:
456 // Offset by 4 and don't encode the lower bit, which is always 0.
457 return ((Value - 4) >> 1) & 0x7ff;
458 case ARM::fixup_arm_thumb_bcc:
459 // Offset by 4 and don't encode the lower bit, which is always 0.
460 return ((Value - 4) >> 1) & 0xff;
461 case ARM::fixup_arm_pcrel_10_unscaled: {
462 Value = Value - 8; // ARM fixups offset by an additional word and don't
463 // need to adjust for the half-word ordering.
465 if ((int64_t)Value < 0) {
469 assert ((Value < 256) && "Out of range pc-relative fixup value!");
470 return Value | (isAdd << 23);
472 case ARM::fixup_arm_pcrel_10:
473 Value = Value - 4; // ARM fixups offset by an additional word and don't
474 // need to adjust for the half-word ordering.
476 case ARM::fixup_t2_pcrel_10: {
477 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
480 if ((int64_t)Value < 0) {
484 // These values don't encode the low two bits since they're always zero.
486 assert ((Value < 256) && "Out of range pc-relative fixup value!");
487 Value |= isAdd << 23;
489 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
491 if (Kind == ARM::fixup_t2_pcrel_10) {
492 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
493 swapped |= (Value & 0x0000FFFF) << 16;
504 // FIXME: This should be in a separate file.
505 // ELF is an ELF of course...
506 class ELFARMAsmBackend : public ARMAsmBackend {
509 ELFARMAsmBackend(const Target &T, const StringRef TT,
511 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
513 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
514 uint64_t Value) const;
516 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
517 return createARMELFObjectWriter(OS, OSABI);
521 // FIXME: Raise this to share code between Darwin and ELF.
522 void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
523 unsigned DataSize, uint64_t Value) const {
524 unsigned NumBytes = 4; // FIXME: 2 for Thumb
525 Value = adjustFixupValue(Fixup.getKind(), Value);
526 if (!Value) return; // Doesn't change encoding.
528 unsigned Offset = Fixup.getOffset();
530 // For each byte of the fragment that the fixup touches, mask in the bits from
531 // the fixup value. The Value has been "split up" into the appropriate
533 for (unsigned i = 0; i != NumBytes; ++i)
534 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
537 // FIXME: This should be in a separate file.
538 class DarwinARMAsmBackend : public ARMAsmBackend {
540 const object::mach::CPUSubtypeARM Subtype;
541 DarwinARMAsmBackend(const Target &T, const StringRef TT,
542 object::mach::CPUSubtypeARM st)
543 : ARMAsmBackend(T, TT), Subtype(st) { }
545 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
546 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
547 object::mach::CTM_ARM,
551 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
552 uint64_t Value) const;
554 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
559 /// getFixupKindNumBytes - The number of bytes the fixup may change.
560 static unsigned getFixupKindNumBytes(unsigned Kind) {
563 llvm_unreachable("Unknown fixup kind!");
566 case ARM::fixup_arm_thumb_bcc:
567 case ARM::fixup_arm_thumb_cp:
568 case ARM::fixup_thumb_adr_pcrel_10:
572 case ARM::fixup_arm_thumb_br:
573 case ARM::fixup_arm_thumb_cb:
576 case ARM::fixup_arm_pcrel_10_unscaled:
577 case ARM::fixup_arm_ldst_pcrel_12:
578 case ARM::fixup_arm_pcrel_10:
579 case ARM::fixup_arm_adr_pcrel_12:
580 case ARM::fixup_arm_bl:
581 case ARM::fixup_arm_blx:
582 case ARM::fixup_arm_condbranch:
583 case ARM::fixup_arm_uncondbranch:
587 case ARM::fixup_t2_ldst_pcrel_12:
588 case ARM::fixup_t2_condbranch:
589 case ARM::fixup_t2_uncondbranch:
590 case ARM::fixup_t2_pcrel_10:
591 case ARM::fixup_t2_adr_pcrel_12:
592 case ARM::fixup_arm_thumb_bl:
593 case ARM::fixup_arm_thumb_blx:
594 case ARM::fixup_arm_movt_hi16:
595 case ARM::fixup_arm_movw_lo16:
596 case ARM::fixup_arm_movt_hi16_pcrel:
597 case ARM::fixup_arm_movw_lo16_pcrel:
598 case ARM::fixup_t2_movt_hi16:
599 case ARM::fixup_t2_movw_lo16:
600 case ARM::fixup_t2_movt_hi16_pcrel:
601 case ARM::fixup_t2_movw_lo16_pcrel:
606 void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
607 unsigned DataSize, uint64_t Value) const {
608 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
609 Value = adjustFixupValue(Fixup.getKind(), Value);
610 if (!Value) return; // Doesn't change encoding.
612 unsigned Offset = Fixup.getOffset();
613 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
615 // For each byte of the fragment that the fixup touches, mask in the
616 // bits from the fixup value.
617 for (unsigned i = 0; i != NumBytes; ++i)
618 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
621 } // end anonymous namespace
623 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
624 Triple TheTriple(TT);
626 if (TheTriple.isOSDarwin()) {
627 if (TheTriple.getArchName() == "armv4t" ||
628 TheTriple.getArchName() == "thumbv4t")
629 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
630 else if (TheTriple.getArchName() == "armv5e" ||
631 TheTriple.getArchName() == "thumbv5e")
632 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
633 else if (TheTriple.getArchName() == "armv6" ||
634 TheTriple.getArchName() == "thumbv6")
635 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
636 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
639 if (TheTriple.isOSWindows())
640 assert(0 && "Windows not supported on ARM");
642 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
643 return new ELFARMAsmBackend(T, TT, OSABI);