1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/raw_ostream.h"
30 #define DEBUG_TYPE "arm-disassembler"
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
35 // Handles the condition code status of instructions in IT blocks
39 // Returns the condition code for instruction in IT block
41 unsigned CC = ARMCC::AL;
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 ITStates.push_back(CCBits);
77 ITStates.push_back(CCBits ^ 1);
79 ITStates.push_back(CCBits);
83 std::vector<unsigned char> ITStates;
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
91 /// Constructor - Initializes the disassembler.
93 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
94 MCDisassembler(STI, Ctx) {
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
102 const MemoryObject ®ion, uint64_t address,
103 raw_ostream &vStream,
104 raw_ostream &cStream) const override;
107 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
108 class ThumbDisassembler : public MCDisassembler {
110 /// Constructor - Initializes the disassembler.
112 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
113 MCDisassembler(STI, Ctx) {
116 ~ThumbDisassembler() {
119 /// getInstruction - See MCDisassembler.
120 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
121 const MemoryObject ®ion, uint64_t address,
122 raw_ostream &vStream,
123 raw_ostream &cStream) const override;
126 mutable ITStatus ITBlock;
127 DecodeStatus AddThumbPredicate(MCInst&) const;
128 void UpdateThumbVFPPredicate(MCInst&) const;
132 static bool Check(DecodeStatus &Out, DecodeStatus In) {
134 case MCDisassembler::Success:
135 // Out stays the same.
137 case MCDisassembler::SoftFail:
140 case MCDisassembler::Fail:
144 llvm_unreachable("Invalid DecodeStatus!");
148 // Forward declare these because the autogenerated code will reference them.
149 // Definitions are further down.
150 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
153 unsigned RegNo, uint64_t Address,
154 const void *Decoder);
155 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
156 unsigned RegNo, uint64_t Address,
157 const void *Decoder);
158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
175 const void *Decoder);
176 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
181 unsigned RegNo, uint64_t Address,
182 const void *Decoder);
184 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
204 const void *Decoder);
205 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
217 const void *Decoder);
218 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
323 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
347 uint64_t Address, const void* Decoder);
348 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
349 uint64_t Address, const void* Decoder);
350 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
353 uint64_t Address, const void* Decoder);
354 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
395 uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
397 uint64_t Address, const void *Decoder);
399 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
400 uint64_t Address, const void *Decoder);
401 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
402 uint64_t Address, const void *Decoder);
403 #include "ARMGenDisassemblerTables.inc"
405 static MCDisassembler *createARMDisassembler(const Target &T,
406 const MCSubtargetInfo &STI,
408 return new ARMDisassembler(STI, Ctx);
411 static MCDisassembler *createThumbDisassembler(const Target &T,
412 const MCSubtargetInfo &STI,
414 return new ThumbDisassembler(STI, Ctx);
417 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
418 const MemoryObject &Region,
421 raw_ostream &cs) const {
426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
429 // We want to read exactly 4 bytes of data.
430 if (Region.readBytes(Address, 4, bytes) == -1) {
432 return MCDisassembler::Fail;
435 // Encoded as a small-endian 32-bit word in the stream.
436 uint32_t insn = (bytes[3] << 24) |
441 // Calling the auto-generated decoder function.
442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
444 if (result != MCDisassembler::Fail) {
449 // VFP and NEON instructions, similarly, are shared between ARM
452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
453 if (result != MCDisassembler::Fail) {
459 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
460 if (result != MCDisassembler::Fail) {
466 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
468 if (result != MCDisassembler::Fail) {
470 // Add a fake predicate operand, because we share these instruction
471 // definitions with Thumb2 where these instructions are predicable.
472 if (!DecodePredicateOperand(MI, 0xE, Address, this))
473 return MCDisassembler::Fail;
478 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
480 if (result != MCDisassembler::Fail) {
482 // Add a fake predicate operand, because we share these instruction
483 // definitions with Thumb2 where these instructions are predicable.
484 if (!DecodePredicateOperand(MI, 0xE, Address, this))
485 return MCDisassembler::Fail;
490 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
492 if (result != MCDisassembler::Fail) {
494 // Add a fake predicate operand, because we share these instruction
495 // definitions with Thumb2 where these instructions are predicable.
496 if (!DecodePredicateOperand(MI, 0xE, Address, this))
497 return MCDisassembler::Fail;
502 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address,
504 if (result != MCDisassembler::Fail) {
510 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address,
512 if (result != MCDisassembler::Fail) {
519 return MCDisassembler::Fail;
523 extern const MCInstrDesc ARMInsts[];
526 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
527 /// immediate Value in the MCInst. The immediate Value has had any PC
528 /// adjustment made by the caller. If the instruction is a branch instruction
529 /// then isBranch is true, else false. If the getOpInfo() function was set as
530 /// part of the setupForSymbolicDisassembly() call then that function is called
531 /// to get any symbolic information at the Address for this instruction. If
532 /// that returns non-zero then the symbolic information it returns is used to
533 /// create an MCExpr and that is added as an operand to the MCInst. If
534 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
535 /// Value is done and if a symbol is found an MCExpr is created with that, else
536 /// an MCExpr with Value is created. This function returns true if it adds an
537 /// operand to the MCInst and false otherwise.
538 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
539 bool isBranch, uint64_t InstSize,
540 MCInst &MI, const void *Decoder) {
541 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
542 // FIXME: Does it make sense for value to be negative?
543 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
544 /* Offset */ 0, InstSize);
547 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
548 /// referenced by a load instruction with the base register that is the Pc.
549 /// These can often be values in a literal pool near the Address of the
550 /// instruction. The Address of the instruction and its immediate Value are
551 /// used as a possible literal pool entry. The SymbolLookUp call back will
552 /// return the name of a symbol referenced by the literal pool's entry if
553 /// the referenced address is that of a symbol. Or it will return a pointer to
554 /// a literal 'C' string if the referenced address of the literal pool's entry
555 /// is an address into a section with 'C' string literals.
556 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
557 const void *Decoder) {
558 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
559 Dis->tryAddingPcLoadReferenceComment(Value, Address);
562 // Thumb1 instructions don't have explicit S bits. Rather, they
563 // implicitly set CPSR. Since it's not represented in the encoding, the
564 // auto-generated decoder won't inject the CPSR operand. We need to fix
565 // that as a post-pass.
566 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
567 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
568 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
569 MCInst::iterator I = MI.begin();
570 for (unsigned i = 0; i < NumOps; ++i, ++I) {
571 if (I == MI.end()) break;
572 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
573 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
574 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
579 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
582 // Most Thumb instructions don't have explicit predicates in the
583 // encoding, but rather get their predicates from IT context. We need
584 // to fix up the predicate operands using this context information as a
586 MCDisassembler::DecodeStatus
587 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
588 MCDisassembler::DecodeStatus S = Success;
590 // A few instructions actually have predicates encoded in them. Don't
591 // try to overwrite it if we're seeing one of those.
592 switch (MI.getOpcode()) {
603 // Some instructions (mostly conditional branches) are not
604 // allowed in IT blocks.
605 if (ITBlock.instrInITBlock())
614 // Some instructions (mostly unconditional branches) can
615 // only appears at the end of, or outside of, an IT.
616 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
623 // If we're in an IT block, base the predicate on that. Otherwise,
624 // assume a predicate of AL.
626 CC = ITBlock.getITCC();
629 if (ITBlock.instrInITBlock())
630 ITBlock.advanceITState();
632 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
633 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
634 MCInst::iterator I = MI.begin();
635 for (unsigned i = 0; i < NumOps; ++i, ++I) {
636 if (I == MI.end()) break;
637 if (OpInfo[i].isPredicate()) {
638 I = MI.insert(I, MCOperand::CreateImm(CC));
641 MI.insert(I, MCOperand::CreateReg(0));
643 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
648 I = MI.insert(I, MCOperand::CreateImm(CC));
651 MI.insert(I, MCOperand::CreateReg(0));
653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
658 // Thumb VFP instructions are a special case. Because we share their
659 // encodings between ARM and Thumb modes, and they are predicable in ARM
660 // mode, the auto-generated decoder will give them an (incorrect)
661 // predicate operand. We need to rewrite these operands based on the IT
662 // context as a post-pass.
663 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
665 CC = ITBlock.getITCC();
666 if (ITBlock.instrInITBlock())
667 ITBlock.advanceITState();
669 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
670 MCInst::iterator I = MI.begin();
671 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
672 for (unsigned i = 0; i < NumOps; ++i, ++I) {
673 if (OpInfo[i].isPredicate() ) {
679 I->setReg(ARM::CPSR);
685 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
686 const MemoryObject &Region,
689 raw_ostream &cs) const {
694 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
695 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
697 // We want to read exactly 2 bytes of data.
698 if (Region.readBytes(Address, 2, bytes) == -1) {
700 return MCDisassembler::Fail;
703 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
704 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
706 if (result != MCDisassembler::Fail) {
708 Check(result, AddThumbPredicate(MI));
713 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
717 bool InITBlock = ITBlock.instrInITBlock();
718 Check(result, AddThumbPredicate(MI));
719 AddThumb1SBit(MI, InITBlock);
724 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
726 if (result != MCDisassembler::Fail) {
729 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
730 // the Thumb predicate.
731 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
732 result = MCDisassembler::SoftFail;
734 Check(result, AddThumbPredicate(MI));
736 // If we find an IT instruction, we need to parse its condition
737 // code and mask operands so that we can apply them correctly
738 // to the subsequent instructions.
739 if (MI.getOpcode() == ARM::t2IT) {
741 unsigned Firstcond = MI.getOperand(0).getImm();
742 unsigned Mask = MI.getOperand(1).getImm();
743 ITBlock.setITState(Firstcond, Mask);
749 // We want to read exactly 4 bytes of data.
750 if (Region.readBytes(Address, 4, bytes) == -1) {
752 return MCDisassembler::Fail;
755 uint32_t insn32 = (bytes[3] << 8) |
760 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
762 if (result != MCDisassembler::Fail) {
764 bool InITBlock = ITBlock.instrInITBlock();
765 Check(result, AddThumbPredicate(MI));
766 AddThumb1SBit(MI, InITBlock);
771 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
773 if (result != MCDisassembler::Fail) {
775 Check(result, AddThumbPredicate(MI));
779 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
781 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
782 if (result != MCDisassembler::Fail) {
784 UpdateThumbVFPPredicate(MI);
790 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
791 if (result != MCDisassembler::Fail) {
796 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
798 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
800 if (result != MCDisassembler::Fail) {
802 Check(result, AddThumbPredicate(MI));
807 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
809 uint32_t NEONLdStInsn = insn32;
810 NEONLdStInsn &= 0xF0FFFFFF;
811 NEONLdStInsn |= 0x04000000;
812 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
814 if (result != MCDisassembler::Fail) {
816 Check(result, AddThumbPredicate(MI));
821 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
823 uint32_t NEONDataInsn = insn32;
824 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
825 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
826 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
827 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
829 if (result != MCDisassembler::Fail) {
831 Check(result, AddThumbPredicate(MI));
836 uint32_t NEONCryptoInsn = insn32;
837 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
838 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
839 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
840 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
842 if (result != MCDisassembler::Fail) {
848 uint32_t NEONv8Insn = insn32;
849 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
850 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
852 if (result != MCDisassembler::Fail) {
860 return MCDisassembler::Fail;
864 extern "C" void LLVMInitializeARMDisassembler() {
865 TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
866 createARMDisassembler);
867 TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
868 createARMDisassembler);
869 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
870 createThumbDisassembler);
871 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
872 createThumbDisassembler);
875 static const uint16_t GPRDecoderTable[] = {
876 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
877 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
878 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
879 ARM::R12, ARM::SP, ARM::LR, ARM::PC
882 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
883 uint64_t Address, const void *Decoder) {
885 return MCDisassembler::Fail;
887 unsigned Register = GPRDecoderTable[RegNo];
888 Inst.addOperand(MCOperand::CreateReg(Register));
889 return MCDisassembler::Success;
893 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
894 uint64_t Address, const void *Decoder) {
895 DecodeStatus S = MCDisassembler::Success;
898 S = MCDisassembler::SoftFail;
900 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
906 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
907 uint64_t Address, const void *Decoder) {
908 DecodeStatus S = MCDisassembler::Success;
912 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
913 return MCDisassembler::Success;
916 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
920 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
921 uint64_t Address, const void *Decoder) {
923 return MCDisassembler::Fail;
924 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
927 static const uint16_t GPRPairDecoderTable[] = {
928 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
929 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
932 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
933 uint64_t Address, const void *Decoder) {
934 DecodeStatus S = MCDisassembler::Success;
937 return MCDisassembler::Fail;
939 if ((RegNo & 1) || RegNo == 0xe)
940 S = MCDisassembler::SoftFail;
942 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
943 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
947 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
948 uint64_t Address, const void *Decoder) {
949 unsigned Register = 0;
970 return MCDisassembler::Fail;
973 Inst.addOperand(MCOperand::CreateReg(Register));
974 return MCDisassembler::Success;
977 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
978 uint64_t Address, const void *Decoder) {
979 DecodeStatus S = MCDisassembler::Success;
980 if (RegNo == 13 || RegNo == 15)
981 S = MCDisassembler::SoftFail;
982 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
986 static const uint16_t SPRDecoderTable[] = {
987 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
988 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
989 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
990 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
991 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
992 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
993 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
994 ARM::S28, ARM::S29, ARM::S30, ARM::S31
997 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
998 uint64_t Address, const void *Decoder) {
1000 return MCDisassembler::Fail;
1002 unsigned Register = SPRDecoderTable[RegNo];
1003 Inst.addOperand(MCOperand::CreateReg(Register));
1004 return MCDisassembler::Success;
1007 static const uint16_t DPRDecoderTable[] = {
1008 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1009 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1010 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1011 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1012 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1013 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1014 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1015 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1018 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1019 uint64_t Address, const void *Decoder) {
1020 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1022 bool hasD16 = featureBits & ARM::FeatureD16;
1024 if (RegNo > 31 || (hasD16 && RegNo > 15))
1025 return MCDisassembler::Fail;
1027 unsigned Register = DPRDecoderTable[RegNo];
1028 Inst.addOperand(MCOperand::CreateReg(Register));
1029 return MCDisassembler::Success;
1032 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1033 uint64_t Address, const void *Decoder) {
1035 return MCDisassembler::Fail;
1036 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1040 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1041 uint64_t Address, const void *Decoder) {
1043 return MCDisassembler::Fail;
1044 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1047 static const uint16_t QPRDecoderTable[] = {
1048 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1049 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1050 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1051 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1055 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1056 uint64_t Address, const void *Decoder) {
1057 if (RegNo > 31 || (RegNo & 1) != 0)
1058 return MCDisassembler::Fail;
1061 unsigned Register = QPRDecoderTable[RegNo];
1062 Inst.addOperand(MCOperand::CreateReg(Register));
1063 return MCDisassembler::Success;
1066 static const uint16_t DPairDecoderTable[] = {
1067 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1068 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1069 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1070 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1071 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1075 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1076 uint64_t Address, const void *Decoder) {
1078 return MCDisassembler::Fail;
1080 unsigned Register = DPairDecoderTable[RegNo];
1081 Inst.addOperand(MCOperand::CreateReg(Register));
1082 return MCDisassembler::Success;
1085 static const uint16_t DPairSpacedDecoderTable[] = {
1086 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1087 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1088 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1089 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1090 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1091 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1092 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1093 ARM::D28_D30, ARM::D29_D31
1096 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1099 const void *Decoder) {
1101 return MCDisassembler::Fail;
1103 unsigned Register = DPairSpacedDecoderTable[RegNo];
1104 Inst.addOperand(MCOperand::CreateReg(Register));
1105 return MCDisassembler::Success;
1108 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1109 uint64_t Address, const void *Decoder) {
1110 if (Val == 0xF) return MCDisassembler::Fail;
1111 // AL predicate is not allowed on Thumb1 branches.
1112 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1113 return MCDisassembler::Fail;
1114 Inst.addOperand(MCOperand::CreateImm(Val));
1115 if (Val == ARMCC::AL) {
1116 Inst.addOperand(MCOperand::CreateReg(0));
1118 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1119 return MCDisassembler::Success;
1122 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1123 uint64_t Address, const void *Decoder) {
1125 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1127 Inst.addOperand(MCOperand::CreateReg(0));
1128 return MCDisassembler::Success;
1131 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1132 uint64_t Address, const void *Decoder) {
1133 uint32_t imm = Val & 0xFF;
1134 uint32_t rot = (Val & 0xF00) >> 7;
1135 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1136 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1137 return MCDisassembler::Success;
1140 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1141 uint64_t Address, const void *Decoder) {
1142 DecodeStatus S = MCDisassembler::Success;
1144 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1145 unsigned type = fieldFromInstruction(Val, 5, 2);
1146 unsigned imm = fieldFromInstruction(Val, 7, 5);
1148 // Register-immediate
1149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1150 return MCDisassembler::Fail;
1152 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1155 Shift = ARM_AM::lsl;
1158 Shift = ARM_AM::lsr;
1161 Shift = ARM_AM::asr;
1164 Shift = ARM_AM::ror;
1168 if (Shift == ARM_AM::ror && imm == 0)
1169 Shift = ARM_AM::rrx;
1171 unsigned Op = Shift | (imm << 3);
1172 Inst.addOperand(MCOperand::CreateImm(Op));
1177 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1178 uint64_t Address, const void *Decoder) {
1179 DecodeStatus S = MCDisassembler::Success;
1181 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1182 unsigned type = fieldFromInstruction(Val, 5, 2);
1183 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1185 // Register-register
1186 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1187 return MCDisassembler::Fail;
1188 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1189 return MCDisassembler::Fail;
1191 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1194 Shift = ARM_AM::lsl;
1197 Shift = ARM_AM::lsr;
1200 Shift = ARM_AM::asr;
1203 Shift = ARM_AM::ror;
1207 Inst.addOperand(MCOperand::CreateImm(Shift));
1212 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1213 uint64_t Address, const void *Decoder) {
1214 DecodeStatus S = MCDisassembler::Success;
1216 bool NeedDisjointWriteback = false;
1217 unsigned WritebackReg = 0;
1218 switch (Inst.getOpcode()) {
1221 case ARM::LDMIA_UPD:
1222 case ARM::LDMDB_UPD:
1223 case ARM::LDMIB_UPD:
1224 case ARM::LDMDA_UPD:
1225 case ARM::t2LDMIA_UPD:
1226 case ARM::t2LDMDB_UPD:
1227 case ARM::t2STMIA_UPD:
1228 case ARM::t2STMDB_UPD:
1229 NeedDisjointWriteback = true;
1230 WritebackReg = Inst.getOperand(0).getReg();
1234 // Empty register lists are not allowed.
1235 if (Val == 0) return MCDisassembler::Fail;
1236 for (unsigned i = 0; i < 16; ++i) {
1237 if (Val & (1 << i)) {
1238 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1239 return MCDisassembler::Fail;
1240 // Writeback not allowed if Rn is in the target list.
1241 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1242 Check(S, MCDisassembler::SoftFail);
1249 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1250 uint64_t Address, const void *Decoder) {
1251 DecodeStatus S = MCDisassembler::Success;
1253 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1254 unsigned regs = fieldFromInstruction(Val, 0, 8);
1256 // In case of unpredictable encoding, tweak the operands.
1257 if (regs == 0 || (Vd + regs) > 32) {
1258 regs = Vd + regs > 32 ? 32 - Vd : regs;
1259 regs = std::max( 1u, regs);
1260 S = MCDisassembler::SoftFail;
1263 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1264 return MCDisassembler::Fail;
1265 for (unsigned i = 0; i < (regs - 1); ++i) {
1266 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1267 return MCDisassembler::Fail;
1273 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1274 uint64_t Address, const void *Decoder) {
1275 DecodeStatus S = MCDisassembler::Success;
1277 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1278 unsigned regs = fieldFromInstruction(Val, 1, 7);
1280 // In case of unpredictable encoding, tweak the operands.
1281 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1282 regs = Vd + regs > 32 ? 32 - Vd : regs;
1283 regs = std::max( 1u, regs);
1284 regs = std::min(16u, regs);
1285 S = MCDisassembler::SoftFail;
1288 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1289 return MCDisassembler::Fail;
1290 for (unsigned i = 0; i < (regs - 1); ++i) {
1291 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1292 return MCDisassembler::Fail;
1298 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1299 uint64_t Address, const void *Decoder) {
1300 // This operand encodes a mask of contiguous zeros between a specified MSB
1301 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1302 // the mask of all bits LSB-and-lower, and then xor them to create
1303 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1304 // create the final mask.
1305 unsigned msb = fieldFromInstruction(Val, 5, 5);
1306 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1308 DecodeStatus S = MCDisassembler::Success;
1310 Check(S, MCDisassembler::SoftFail);
1311 // The check above will cause the warning for the "potentially undefined
1312 // instruction encoding" but we can't build a bad MCOperand value here
1313 // with a lsb > msb or else printing the MCInst will cause a crash.
1317 uint32_t msb_mask = 0xFFFFFFFF;
1318 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1319 uint32_t lsb_mask = (1U << lsb) - 1;
1321 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1325 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1326 uint64_t Address, const void *Decoder) {
1327 DecodeStatus S = MCDisassembler::Success;
1329 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1330 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1331 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1332 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1333 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1334 unsigned U = fieldFromInstruction(Insn, 23, 1);
1336 switch (Inst.getOpcode()) {
1337 case ARM::LDC_OFFSET:
1340 case ARM::LDC_OPTION:
1341 case ARM::LDCL_OFFSET:
1343 case ARM::LDCL_POST:
1344 case ARM::LDCL_OPTION:
1345 case ARM::STC_OFFSET:
1348 case ARM::STC_OPTION:
1349 case ARM::STCL_OFFSET:
1351 case ARM::STCL_POST:
1352 case ARM::STCL_OPTION:
1353 case ARM::t2LDC_OFFSET:
1354 case ARM::t2LDC_PRE:
1355 case ARM::t2LDC_POST:
1356 case ARM::t2LDC_OPTION:
1357 case ARM::t2LDCL_OFFSET:
1358 case ARM::t2LDCL_PRE:
1359 case ARM::t2LDCL_POST:
1360 case ARM::t2LDCL_OPTION:
1361 case ARM::t2STC_OFFSET:
1362 case ARM::t2STC_PRE:
1363 case ARM::t2STC_POST:
1364 case ARM::t2STC_OPTION:
1365 case ARM::t2STCL_OFFSET:
1366 case ARM::t2STCL_PRE:
1367 case ARM::t2STCL_POST:
1368 case ARM::t2STCL_OPTION:
1369 if (coproc == 0xA || coproc == 0xB)
1370 return MCDisassembler::Fail;
1376 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1378 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1379 return MCDisassembler::Fail;
1381 Inst.addOperand(MCOperand::CreateImm(coproc));
1382 Inst.addOperand(MCOperand::CreateImm(CRd));
1383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1384 return MCDisassembler::Fail;
1386 switch (Inst.getOpcode()) {
1387 case ARM::t2LDC2_OFFSET:
1388 case ARM::t2LDC2L_OFFSET:
1389 case ARM::t2LDC2_PRE:
1390 case ARM::t2LDC2L_PRE:
1391 case ARM::t2STC2_OFFSET:
1392 case ARM::t2STC2L_OFFSET:
1393 case ARM::t2STC2_PRE:
1394 case ARM::t2STC2L_PRE:
1395 case ARM::LDC2_OFFSET:
1396 case ARM::LDC2L_OFFSET:
1398 case ARM::LDC2L_PRE:
1399 case ARM::STC2_OFFSET:
1400 case ARM::STC2L_OFFSET:
1402 case ARM::STC2L_PRE:
1403 case ARM::t2LDC_OFFSET:
1404 case ARM::t2LDCL_OFFSET:
1405 case ARM::t2LDC_PRE:
1406 case ARM::t2LDCL_PRE:
1407 case ARM::t2STC_OFFSET:
1408 case ARM::t2STCL_OFFSET:
1409 case ARM::t2STC_PRE:
1410 case ARM::t2STCL_PRE:
1411 case ARM::LDC_OFFSET:
1412 case ARM::LDCL_OFFSET:
1415 case ARM::STC_OFFSET:
1416 case ARM::STCL_OFFSET:
1419 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1420 Inst.addOperand(MCOperand::CreateImm(imm));
1422 case ARM::t2LDC2_POST:
1423 case ARM::t2LDC2L_POST:
1424 case ARM::t2STC2_POST:
1425 case ARM::t2STC2L_POST:
1426 case ARM::LDC2_POST:
1427 case ARM::LDC2L_POST:
1428 case ARM::STC2_POST:
1429 case ARM::STC2L_POST:
1430 case ARM::t2LDC_POST:
1431 case ARM::t2LDCL_POST:
1432 case ARM::t2STC_POST:
1433 case ARM::t2STCL_POST:
1435 case ARM::LDCL_POST:
1437 case ARM::STCL_POST:
1441 // The 'option' variant doesn't encode 'U' in the immediate since
1442 // the immediate is unsigned [0,255].
1443 Inst.addOperand(MCOperand::CreateImm(imm));
1447 switch (Inst.getOpcode()) {
1448 case ARM::LDC_OFFSET:
1451 case ARM::LDC_OPTION:
1452 case ARM::LDCL_OFFSET:
1454 case ARM::LDCL_POST:
1455 case ARM::LDCL_OPTION:
1456 case ARM::STC_OFFSET:
1459 case ARM::STC_OPTION:
1460 case ARM::STCL_OFFSET:
1462 case ARM::STCL_POST:
1463 case ARM::STCL_OPTION:
1464 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1465 return MCDisassembler::Fail;
1475 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1476 uint64_t Address, const void *Decoder) {
1477 DecodeStatus S = MCDisassembler::Success;
1479 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1480 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1481 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1482 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1483 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1484 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1485 unsigned P = fieldFromInstruction(Insn, 24, 1);
1486 unsigned W = fieldFromInstruction(Insn, 21, 1);
1488 // On stores, the writeback operand precedes Rt.
1489 switch (Inst.getOpcode()) {
1490 case ARM::STR_POST_IMM:
1491 case ARM::STR_POST_REG:
1492 case ARM::STRB_POST_IMM:
1493 case ARM::STRB_POST_REG:
1494 case ARM::STRT_POST_REG:
1495 case ARM::STRT_POST_IMM:
1496 case ARM::STRBT_POST_REG:
1497 case ARM::STRBT_POST_IMM:
1498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1499 return MCDisassembler::Fail;
1505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1506 return MCDisassembler::Fail;
1508 // On loads, the writeback operand comes after Rt.
1509 switch (Inst.getOpcode()) {
1510 case ARM::LDR_POST_IMM:
1511 case ARM::LDR_POST_REG:
1512 case ARM::LDRB_POST_IMM:
1513 case ARM::LDRB_POST_REG:
1514 case ARM::LDRBT_POST_REG:
1515 case ARM::LDRBT_POST_IMM:
1516 case ARM::LDRT_POST_REG:
1517 case ARM::LDRT_POST_IMM:
1518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1519 return MCDisassembler::Fail;
1525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1526 return MCDisassembler::Fail;
1528 ARM_AM::AddrOpc Op = ARM_AM::add;
1529 if (!fieldFromInstruction(Insn, 23, 1))
1532 bool writeback = (P == 0) || (W == 1);
1533 unsigned idx_mode = 0;
1535 idx_mode = ARMII::IndexModePre;
1536 else if (!P && writeback)
1537 idx_mode = ARMII::IndexModePost;
1539 if (writeback && (Rn == 15 || Rn == Rt))
1540 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1543 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1544 return MCDisassembler::Fail;
1545 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1546 switch( fieldFromInstruction(Insn, 5, 2)) {
1560 return MCDisassembler::Fail;
1562 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1563 if (Opc == ARM_AM::ror && amt == 0)
1565 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1567 Inst.addOperand(MCOperand::CreateImm(imm));
1569 Inst.addOperand(MCOperand::CreateReg(0));
1570 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1571 Inst.addOperand(MCOperand::CreateImm(tmp));
1574 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1575 return MCDisassembler::Fail;
1580 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1581 uint64_t Address, const void *Decoder) {
1582 DecodeStatus S = MCDisassembler::Success;
1584 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1585 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1586 unsigned type = fieldFromInstruction(Val, 5, 2);
1587 unsigned imm = fieldFromInstruction(Val, 7, 5);
1588 unsigned U = fieldFromInstruction(Val, 12, 1);
1590 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1606 if (ShOp == ARM_AM::ror && imm == 0)
1609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1610 return MCDisassembler::Fail;
1611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1612 return MCDisassembler::Fail;
1615 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1617 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1618 Inst.addOperand(MCOperand::CreateImm(shift));
1624 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1625 uint64_t Address, const void *Decoder) {
1626 DecodeStatus S = MCDisassembler::Success;
1628 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1629 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1630 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1631 unsigned type = fieldFromInstruction(Insn, 22, 1);
1632 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1633 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1634 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1635 unsigned W = fieldFromInstruction(Insn, 21, 1);
1636 unsigned P = fieldFromInstruction(Insn, 24, 1);
1637 unsigned Rt2 = Rt + 1;
1639 bool writeback = (W == 1) | (P == 0);
1641 // For {LD,ST}RD, Rt must be even, else undefined.
1642 switch (Inst.getOpcode()) {
1645 case ARM::STRD_POST:
1648 case ARM::LDRD_POST:
1649 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1654 switch (Inst.getOpcode()) {
1657 case ARM::STRD_POST:
1658 if (P == 0 && W == 1)
1659 S = MCDisassembler::SoftFail;
1661 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1662 S = MCDisassembler::SoftFail;
1663 if (type && Rm == 15)
1664 S = MCDisassembler::SoftFail;
1666 S = MCDisassembler::SoftFail;
1667 if (!type && fieldFromInstruction(Insn, 8, 4))
1668 S = MCDisassembler::SoftFail;
1672 case ARM::STRH_POST:
1674 S = MCDisassembler::SoftFail;
1675 if (writeback && (Rn == 15 || Rn == Rt))
1676 S = MCDisassembler::SoftFail;
1677 if (!type && Rm == 15)
1678 S = MCDisassembler::SoftFail;
1682 case ARM::LDRD_POST:
1683 if (type && Rn == 15){
1685 S = MCDisassembler::SoftFail;
1688 if (P == 0 && W == 1)
1689 S = MCDisassembler::SoftFail;
1690 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1691 S = MCDisassembler::SoftFail;
1692 if (!type && writeback && Rn == 15)
1693 S = MCDisassembler::SoftFail;
1694 if (writeback && (Rn == Rt || Rn == Rt2))
1695 S = MCDisassembler::SoftFail;
1699 case ARM::LDRH_POST:
1700 if (type && Rn == 15){
1702 S = MCDisassembler::SoftFail;
1706 S = MCDisassembler::SoftFail;
1707 if (!type && Rm == 15)
1708 S = MCDisassembler::SoftFail;
1709 if (!type && writeback && (Rn == 15 || Rn == Rt))
1710 S = MCDisassembler::SoftFail;
1713 case ARM::LDRSH_PRE:
1714 case ARM::LDRSH_POST:
1716 case ARM::LDRSB_PRE:
1717 case ARM::LDRSB_POST:
1718 if (type && Rn == 15){
1720 S = MCDisassembler::SoftFail;
1723 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1724 S = MCDisassembler::SoftFail;
1725 if (!type && (Rt == 15 || Rm == 15))
1726 S = MCDisassembler::SoftFail;
1727 if (!type && writeback && (Rn == 15 || Rn == Rt))
1728 S = MCDisassembler::SoftFail;
1734 if (writeback) { // Writeback
1736 U |= ARMII::IndexModePre << 9;
1738 U |= ARMII::IndexModePost << 9;
1740 // On stores, the writeback operand precedes Rt.
1741 switch (Inst.getOpcode()) {
1744 case ARM::STRD_POST:
1747 case ARM::STRH_POST:
1748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1749 return MCDisassembler::Fail;
1756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1757 return MCDisassembler::Fail;
1758 switch (Inst.getOpcode()) {
1761 case ARM::STRD_POST:
1764 case ARM::LDRD_POST:
1765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1766 return MCDisassembler::Fail;
1773 // On loads, the writeback operand comes after Rt.
1774 switch (Inst.getOpcode()) {
1777 case ARM::LDRD_POST:
1780 case ARM::LDRH_POST:
1782 case ARM::LDRSH_PRE:
1783 case ARM::LDRSH_POST:
1785 case ARM::LDRSB_PRE:
1786 case ARM::LDRSB_POST:
1789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1790 return MCDisassembler::Fail;
1797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1798 return MCDisassembler::Fail;
1801 Inst.addOperand(MCOperand::CreateReg(0));
1802 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1805 return MCDisassembler::Fail;
1806 Inst.addOperand(MCOperand::CreateImm(U));
1809 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1810 return MCDisassembler::Fail;
1815 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1816 uint64_t Address, const void *Decoder) {
1817 DecodeStatus S = MCDisassembler::Success;
1819 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1820 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1837 Inst.addOperand(MCOperand::CreateImm(mode));
1838 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1839 return MCDisassembler::Fail;
1844 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1845 uint64_t Address, const void *Decoder) {
1846 DecodeStatus S = MCDisassembler::Success;
1848 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1849 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1850 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1851 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1854 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1857 return MCDisassembler::Fail;
1858 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1859 return MCDisassembler::Fail;
1860 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1861 return MCDisassembler::Fail;
1862 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1863 return MCDisassembler::Fail;
1867 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1869 uint64_t Address, const void *Decoder) {
1870 DecodeStatus S = MCDisassembler::Success;
1872 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1873 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1874 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1877 // Ambiguous with RFE and SRS
1878 switch (Inst.getOpcode()) {
1880 Inst.setOpcode(ARM::RFEDA);
1882 case ARM::LDMDA_UPD:
1883 Inst.setOpcode(ARM::RFEDA_UPD);
1886 Inst.setOpcode(ARM::RFEDB);
1888 case ARM::LDMDB_UPD:
1889 Inst.setOpcode(ARM::RFEDB_UPD);
1892 Inst.setOpcode(ARM::RFEIA);
1894 case ARM::LDMIA_UPD:
1895 Inst.setOpcode(ARM::RFEIA_UPD);
1898 Inst.setOpcode(ARM::RFEIB);
1900 case ARM::LDMIB_UPD:
1901 Inst.setOpcode(ARM::RFEIB_UPD);
1904 Inst.setOpcode(ARM::SRSDA);
1906 case ARM::STMDA_UPD:
1907 Inst.setOpcode(ARM::SRSDA_UPD);
1910 Inst.setOpcode(ARM::SRSDB);
1912 case ARM::STMDB_UPD:
1913 Inst.setOpcode(ARM::SRSDB_UPD);
1916 Inst.setOpcode(ARM::SRSIA);
1918 case ARM::STMIA_UPD:
1919 Inst.setOpcode(ARM::SRSIA_UPD);
1922 Inst.setOpcode(ARM::SRSIB);
1924 case ARM::STMIB_UPD:
1925 Inst.setOpcode(ARM::SRSIB_UPD);
1928 return MCDisassembler::Fail;
1931 // For stores (which become SRS's, the only operand is the mode.
1932 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1933 // Check SRS encoding constraints
1934 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1935 fieldFromInstruction(Insn, 20, 1) == 0))
1936 return MCDisassembler::Fail;
1939 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1943 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1947 return MCDisassembler::Fail;
1948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1949 return MCDisassembler::Fail; // Tied
1950 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1951 return MCDisassembler::Fail;
1952 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1953 return MCDisassembler::Fail;
1958 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1959 uint64_t Address, const void *Decoder) {
1960 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1961 unsigned M = fieldFromInstruction(Insn, 17, 1);
1962 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1963 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1965 DecodeStatus S = MCDisassembler::Success;
1967 // This decoder is called from multiple location that do not check
1968 // the full encoding is valid before they do.
1969 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1970 fieldFromInstruction(Insn, 16, 1) != 0 ||
1971 fieldFromInstruction(Insn, 20, 8) != 0x10)
1972 return MCDisassembler::Fail;
1974 // imod == '01' --> UNPREDICTABLE
1975 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1976 // return failure here. The '01' imod value is unprintable, so there's
1977 // nothing useful we could do even if we returned UNPREDICTABLE.
1979 if (imod == 1) return MCDisassembler::Fail;
1982 Inst.setOpcode(ARM::CPS3p);
1983 Inst.addOperand(MCOperand::CreateImm(imod));
1984 Inst.addOperand(MCOperand::CreateImm(iflags));
1985 Inst.addOperand(MCOperand::CreateImm(mode));
1986 } else if (imod && !M) {
1987 Inst.setOpcode(ARM::CPS2p);
1988 Inst.addOperand(MCOperand::CreateImm(imod));
1989 Inst.addOperand(MCOperand::CreateImm(iflags));
1990 if (mode) S = MCDisassembler::SoftFail;
1991 } else if (!imod && M) {
1992 Inst.setOpcode(ARM::CPS1p);
1993 Inst.addOperand(MCOperand::CreateImm(mode));
1994 if (iflags) S = MCDisassembler::SoftFail;
1996 // imod == '00' && M == '0' --> UNPREDICTABLE
1997 Inst.setOpcode(ARM::CPS1p);
1998 Inst.addOperand(MCOperand::CreateImm(mode));
1999 S = MCDisassembler::SoftFail;
2005 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2006 uint64_t Address, const void *Decoder) {
2007 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2008 unsigned M = fieldFromInstruction(Insn, 8, 1);
2009 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2010 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2012 DecodeStatus S = MCDisassembler::Success;
2014 // imod == '01' --> UNPREDICTABLE
2015 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2016 // return failure here. The '01' imod value is unprintable, so there's
2017 // nothing useful we could do even if we returned UNPREDICTABLE.
2019 if (imod == 1) return MCDisassembler::Fail;
2022 Inst.setOpcode(ARM::t2CPS3p);
2023 Inst.addOperand(MCOperand::CreateImm(imod));
2024 Inst.addOperand(MCOperand::CreateImm(iflags));
2025 Inst.addOperand(MCOperand::CreateImm(mode));
2026 } else if (imod && !M) {
2027 Inst.setOpcode(ARM::t2CPS2p);
2028 Inst.addOperand(MCOperand::CreateImm(imod));
2029 Inst.addOperand(MCOperand::CreateImm(iflags));
2030 if (mode) S = MCDisassembler::SoftFail;
2031 } else if (!imod && M) {
2032 Inst.setOpcode(ARM::t2CPS1p);
2033 Inst.addOperand(MCOperand::CreateImm(mode));
2034 if (iflags) S = MCDisassembler::SoftFail;
2036 // imod == '00' && M == '0' --> this is a HINT instruction
2037 int imm = fieldFromInstruction(Insn, 0, 8);
2038 // HINT are defined only for immediate in [0..4]
2039 if(imm > 4) return MCDisassembler::Fail;
2040 Inst.setOpcode(ARM::t2HINT);
2041 Inst.addOperand(MCOperand::CreateImm(imm));
2047 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2048 uint64_t Address, const void *Decoder) {
2049 DecodeStatus S = MCDisassembler::Success;
2051 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2054 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2055 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2056 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2057 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2059 if (Inst.getOpcode() == ARM::t2MOVTi16)
2060 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2061 return MCDisassembler::Fail;
2062 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2063 return MCDisassembler::Fail;
2065 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2066 Inst.addOperand(MCOperand::CreateImm(imm));
2071 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2072 uint64_t Address, const void *Decoder) {
2073 DecodeStatus S = MCDisassembler::Success;
2075 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2076 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2079 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2080 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2082 if (Inst.getOpcode() == ARM::MOVTi16)
2083 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2084 return MCDisassembler::Fail;
2086 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2087 return MCDisassembler::Fail;
2089 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2090 Inst.addOperand(MCOperand::CreateImm(imm));
2092 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2093 return MCDisassembler::Fail;
2098 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2099 uint64_t Address, const void *Decoder) {
2100 DecodeStatus S = MCDisassembler::Success;
2102 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2103 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2104 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2105 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2106 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2109 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2112 return MCDisassembler::Fail;
2113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2114 return MCDisassembler::Fail;
2115 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2116 return MCDisassembler::Fail;
2117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2118 return MCDisassembler::Fail;
2120 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2121 return MCDisassembler::Fail;
2126 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2127 uint64_t Address, const void *Decoder) {
2128 DecodeStatus S = MCDisassembler::Success;
2130 unsigned add = fieldFromInstruction(Val, 12, 1);
2131 unsigned imm = fieldFromInstruction(Val, 0, 12);
2132 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2135 return MCDisassembler::Fail;
2137 if (!add) imm *= -1;
2138 if (imm == 0 && !add) imm = INT32_MIN;
2139 Inst.addOperand(MCOperand::CreateImm(imm));
2141 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2146 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2147 uint64_t Address, const void *Decoder) {
2148 DecodeStatus S = MCDisassembler::Success;
2150 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2151 unsigned U = fieldFromInstruction(Val, 8, 1);
2152 unsigned imm = fieldFromInstruction(Val, 0, 8);
2154 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2155 return MCDisassembler::Fail;
2158 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2160 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2165 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2166 uint64_t Address, const void *Decoder) {
2167 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2171 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2172 uint64_t Address, const void *Decoder) {
2173 DecodeStatus Status = MCDisassembler::Success;
2175 // Note the J1 and J2 values are from the encoded instruction. So here
2176 // change them to I1 and I2 values via as documented:
2177 // I1 = NOT(J1 EOR S);
2178 // I2 = NOT(J2 EOR S);
2179 // and build the imm32 with one trailing zero as documented:
2180 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2181 unsigned S = fieldFromInstruction(Insn, 26, 1);
2182 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2183 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2184 unsigned I1 = !(J1 ^ S);
2185 unsigned I2 = !(J2 ^ S);
2186 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2187 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2188 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2189 int imm32 = SignExtend32<25>(tmp << 1);
2190 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2191 true, 4, Inst, Decoder))
2192 Inst.addOperand(MCOperand::CreateImm(imm32));
2198 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2199 uint64_t Address, const void *Decoder) {
2200 DecodeStatus S = MCDisassembler::Success;
2202 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2203 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2206 Inst.setOpcode(ARM::BLXi);
2207 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2208 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2209 true, 4, Inst, Decoder))
2210 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2214 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2215 true, 4, Inst, Decoder))
2216 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2217 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2218 return MCDisassembler::Fail;
2224 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2225 uint64_t Address, const void *Decoder) {
2226 DecodeStatus S = MCDisassembler::Success;
2228 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2229 unsigned align = fieldFromInstruction(Val, 4, 2);
2231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2232 return MCDisassembler::Fail;
2234 Inst.addOperand(MCOperand::CreateImm(0));
2236 Inst.addOperand(MCOperand::CreateImm(4 << align));
2241 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2242 uint64_t Address, const void *Decoder) {
2243 DecodeStatus S = MCDisassembler::Success;
2245 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2246 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2247 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2248 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2249 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2250 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2252 // First output register
2253 switch (Inst.getOpcode()) {
2254 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2255 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2256 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2257 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2258 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2259 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2260 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2261 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2262 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2263 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2264 return MCDisassembler::Fail;
2269 case ARM::VLD2b16wb_fixed:
2270 case ARM::VLD2b16wb_register:
2271 case ARM::VLD2b32wb_fixed:
2272 case ARM::VLD2b32wb_register:
2273 case ARM::VLD2b8wb_fixed:
2274 case ARM::VLD2b8wb_register:
2275 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2276 return MCDisassembler::Fail;
2279 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2280 return MCDisassembler::Fail;
2283 // Second output register
2284 switch (Inst.getOpcode()) {
2288 case ARM::VLD3d8_UPD:
2289 case ARM::VLD3d16_UPD:
2290 case ARM::VLD3d32_UPD:
2294 case ARM::VLD4d8_UPD:
2295 case ARM::VLD4d16_UPD:
2296 case ARM::VLD4d32_UPD:
2297 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2298 return MCDisassembler::Fail;
2303 case ARM::VLD3q8_UPD:
2304 case ARM::VLD3q16_UPD:
2305 case ARM::VLD3q32_UPD:
2309 case ARM::VLD4q8_UPD:
2310 case ARM::VLD4q16_UPD:
2311 case ARM::VLD4q32_UPD:
2312 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2313 return MCDisassembler::Fail;
2318 // Third output register
2319 switch(Inst.getOpcode()) {
2323 case ARM::VLD3d8_UPD:
2324 case ARM::VLD3d16_UPD:
2325 case ARM::VLD3d32_UPD:
2329 case ARM::VLD4d8_UPD:
2330 case ARM::VLD4d16_UPD:
2331 case ARM::VLD4d32_UPD:
2332 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2333 return MCDisassembler::Fail;
2338 case ARM::VLD3q8_UPD:
2339 case ARM::VLD3q16_UPD:
2340 case ARM::VLD3q32_UPD:
2344 case ARM::VLD4q8_UPD:
2345 case ARM::VLD4q16_UPD:
2346 case ARM::VLD4q32_UPD:
2347 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2348 return MCDisassembler::Fail;
2354 // Fourth output register
2355 switch (Inst.getOpcode()) {
2359 case ARM::VLD4d8_UPD:
2360 case ARM::VLD4d16_UPD:
2361 case ARM::VLD4d32_UPD:
2362 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2363 return MCDisassembler::Fail;
2368 case ARM::VLD4q8_UPD:
2369 case ARM::VLD4q16_UPD:
2370 case ARM::VLD4q32_UPD:
2371 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2372 return MCDisassembler::Fail;
2378 // Writeback operand
2379 switch (Inst.getOpcode()) {
2380 case ARM::VLD1d8wb_fixed:
2381 case ARM::VLD1d16wb_fixed:
2382 case ARM::VLD1d32wb_fixed:
2383 case ARM::VLD1d64wb_fixed:
2384 case ARM::VLD1d8wb_register:
2385 case ARM::VLD1d16wb_register:
2386 case ARM::VLD1d32wb_register:
2387 case ARM::VLD1d64wb_register:
2388 case ARM::VLD1q8wb_fixed:
2389 case ARM::VLD1q16wb_fixed:
2390 case ARM::VLD1q32wb_fixed:
2391 case ARM::VLD1q64wb_fixed:
2392 case ARM::VLD1q8wb_register:
2393 case ARM::VLD1q16wb_register:
2394 case ARM::VLD1q32wb_register:
2395 case ARM::VLD1q64wb_register:
2396 case ARM::VLD1d8Twb_fixed:
2397 case ARM::VLD1d8Twb_register:
2398 case ARM::VLD1d16Twb_fixed:
2399 case ARM::VLD1d16Twb_register:
2400 case ARM::VLD1d32Twb_fixed:
2401 case ARM::VLD1d32Twb_register:
2402 case ARM::VLD1d64Twb_fixed:
2403 case ARM::VLD1d64Twb_register:
2404 case ARM::VLD1d8Qwb_fixed:
2405 case ARM::VLD1d8Qwb_register:
2406 case ARM::VLD1d16Qwb_fixed:
2407 case ARM::VLD1d16Qwb_register:
2408 case ARM::VLD1d32Qwb_fixed:
2409 case ARM::VLD1d32Qwb_register:
2410 case ARM::VLD1d64Qwb_fixed:
2411 case ARM::VLD1d64Qwb_register:
2412 case ARM::VLD2d8wb_fixed:
2413 case ARM::VLD2d16wb_fixed:
2414 case ARM::VLD2d32wb_fixed:
2415 case ARM::VLD2q8wb_fixed:
2416 case ARM::VLD2q16wb_fixed:
2417 case ARM::VLD2q32wb_fixed:
2418 case ARM::VLD2d8wb_register:
2419 case ARM::VLD2d16wb_register:
2420 case ARM::VLD2d32wb_register:
2421 case ARM::VLD2q8wb_register:
2422 case ARM::VLD2q16wb_register:
2423 case ARM::VLD2q32wb_register:
2424 case ARM::VLD2b8wb_fixed:
2425 case ARM::VLD2b16wb_fixed:
2426 case ARM::VLD2b32wb_fixed:
2427 case ARM::VLD2b8wb_register:
2428 case ARM::VLD2b16wb_register:
2429 case ARM::VLD2b32wb_register:
2430 Inst.addOperand(MCOperand::CreateImm(0));
2432 case ARM::VLD3d8_UPD:
2433 case ARM::VLD3d16_UPD:
2434 case ARM::VLD3d32_UPD:
2435 case ARM::VLD3q8_UPD:
2436 case ARM::VLD3q16_UPD:
2437 case ARM::VLD3q32_UPD:
2438 case ARM::VLD4d8_UPD:
2439 case ARM::VLD4d16_UPD:
2440 case ARM::VLD4d32_UPD:
2441 case ARM::VLD4q8_UPD:
2442 case ARM::VLD4q16_UPD:
2443 case ARM::VLD4q32_UPD:
2444 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2445 return MCDisassembler::Fail;
2451 // AddrMode6 Base (register+alignment)
2452 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2453 return MCDisassembler::Fail;
2455 // AddrMode6 Offset (register)
2456 switch (Inst.getOpcode()) {
2458 // The below have been updated to have explicit am6offset split
2459 // between fixed and register offset. For those instructions not
2460 // yet updated, we need to add an additional reg0 operand for the
2463 // The fixed offset encodes as Rm == 0xd, so we check for that.
2465 Inst.addOperand(MCOperand::CreateReg(0));
2468 // Fall through to handle the register offset variant.
2469 case ARM::VLD1d8wb_fixed:
2470 case ARM::VLD1d16wb_fixed:
2471 case ARM::VLD1d32wb_fixed:
2472 case ARM::VLD1d64wb_fixed:
2473 case ARM::VLD1d8Twb_fixed:
2474 case ARM::VLD1d16Twb_fixed:
2475 case ARM::VLD1d32Twb_fixed:
2476 case ARM::VLD1d64Twb_fixed:
2477 case ARM::VLD1d8Qwb_fixed:
2478 case ARM::VLD1d16Qwb_fixed:
2479 case ARM::VLD1d32Qwb_fixed:
2480 case ARM::VLD1d64Qwb_fixed:
2481 case ARM::VLD1d8wb_register:
2482 case ARM::VLD1d16wb_register:
2483 case ARM::VLD1d32wb_register:
2484 case ARM::VLD1d64wb_register:
2485 case ARM::VLD1q8wb_fixed:
2486 case ARM::VLD1q16wb_fixed:
2487 case ARM::VLD1q32wb_fixed:
2488 case ARM::VLD1q64wb_fixed:
2489 case ARM::VLD1q8wb_register:
2490 case ARM::VLD1q16wb_register:
2491 case ARM::VLD1q32wb_register:
2492 case ARM::VLD1q64wb_register:
2493 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2494 // variant encodes Rm == 0xf. Anything else is a register offset post-
2495 // increment and we need to add the register operand to the instruction.
2496 if (Rm != 0xD && Rm != 0xF &&
2497 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2498 return MCDisassembler::Fail;
2500 case ARM::VLD2d8wb_fixed:
2501 case ARM::VLD2d16wb_fixed:
2502 case ARM::VLD2d32wb_fixed:
2503 case ARM::VLD2b8wb_fixed:
2504 case ARM::VLD2b16wb_fixed:
2505 case ARM::VLD2b32wb_fixed:
2506 case ARM::VLD2q8wb_fixed:
2507 case ARM::VLD2q16wb_fixed:
2508 case ARM::VLD2q32wb_fixed:
2515 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2516 uint64_t Address, const void *Decoder) {
2517 unsigned type = fieldFromInstruction(Insn, 8, 4);
2518 unsigned align = fieldFromInstruction(Insn, 4, 2);
2519 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2520 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2521 if (type == 10 && align == 3) return MCDisassembler::Fail;
2523 unsigned load = fieldFromInstruction(Insn, 21, 1);
2524 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2525 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2528 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2529 uint64_t Address, const void *Decoder) {
2530 unsigned size = fieldFromInstruction(Insn, 6, 2);
2531 if (size == 3) return MCDisassembler::Fail;
2533 unsigned type = fieldFromInstruction(Insn, 8, 4);
2534 unsigned align = fieldFromInstruction(Insn, 4, 2);
2535 if (type == 8 && align == 3) return MCDisassembler::Fail;
2536 if (type == 9 && align == 3) return MCDisassembler::Fail;
2538 unsigned load = fieldFromInstruction(Insn, 21, 1);
2539 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2540 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2543 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2544 uint64_t Address, const void *Decoder) {
2545 unsigned size = fieldFromInstruction(Insn, 6, 2);
2546 if (size == 3) return MCDisassembler::Fail;
2548 unsigned align = fieldFromInstruction(Insn, 4, 2);
2549 if (align & 2) return MCDisassembler::Fail;
2551 unsigned load = fieldFromInstruction(Insn, 21, 1);
2552 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2553 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2556 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2557 uint64_t Address, const void *Decoder) {
2558 unsigned size = fieldFromInstruction(Insn, 6, 2);
2559 if (size == 3) return MCDisassembler::Fail;
2561 unsigned load = fieldFromInstruction(Insn, 21, 1);
2562 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2563 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2566 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2567 uint64_t Address, const void *Decoder) {
2568 DecodeStatus S = MCDisassembler::Success;
2570 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2571 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2572 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2573 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2574 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2575 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2577 // Writeback Operand
2578 switch (Inst.getOpcode()) {
2579 case ARM::VST1d8wb_fixed:
2580 case ARM::VST1d16wb_fixed:
2581 case ARM::VST1d32wb_fixed:
2582 case ARM::VST1d64wb_fixed:
2583 case ARM::VST1d8wb_register:
2584 case ARM::VST1d16wb_register:
2585 case ARM::VST1d32wb_register:
2586 case ARM::VST1d64wb_register:
2587 case ARM::VST1q8wb_fixed:
2588 case ARM::VST1q16wb_fixed:
2589 case ARM::VST1q32wb_fixed:
2590 case ARM::VST1q64wb_fixed:
2591 case ARM::VST1q8wb_register:
2592 case ARM::VST1q16wb_register:
2593 case ARM::VST1q32wb_register:
2594 case ARM::VST1q64wb_register:
2595 case ARM::VST1d8Twb_fixed:
2596 case ARM::VST1d16Twb_fixed:
2597 case ARM::VST1d32Twb_fixed:
2598 case ARM::VST1d64Twb_fixed:
2599 case ARM::VST1d8Twb_register:
2600 case ARM::VST1d16Twb_register:
2601 case ARM::VST1d32Twb_register:
2602 case ARM::VST1d64Twb_register:
2603 case ARM::VST1d8Qwb_fixed:
2604 case ARM::VST1d16Qwb_fixed:
2605 case ARM::VST1d32Qwb_fixed:
2606 case ARM::VST1d64Qwb_fixed:
2607 case ARM::VST1d8Qwb_register:
2608 case ARM::VST1d16Qwb_register:
2609 case ARM::VST1d32Qwb_register:
2610 case ARM::VST1d64Qwb_register:
2611 case ARM::VST2d8wb_fixed:
2612 case ARM::VST2d16wb_fixed:
2613 case ARM::VST2d32wb_fixed:
2614 case ARM::VST2d8wb_register:
2615 case ARM::VST2d16wb_register:
2616 case ARM::VST2d32wb_register:
2617 case ARM::VST2q8wb_fixed:
2618 case ARM::VST2q16wb_fixed:
2619 case ARM::VST2q32wb_fixed:
2620 case ARM::VST2q8wb_register:
2621 case ARM::VST2q16wb_register:
2622 case ARM::VST2q32wb_register:
2623 case ARM::VST2b8wb_fixed:
2624 case ARM::VST2b16wb_fixed:
2625 case ARM::VST2b32wb_fixed:
2626 case ARM::VST2b8wb_register:
2627 case ARM::VST2b16wb_register:
2628 case ARM::VST2b32wb_register:
2630 return MCDisassembler::Fail;
2631 Inst.addOperand(MCOperand::CreateImm(0));
2633 case ARM::VST3d8_UPD:
2634 case ARM::VST3d16_UPD:
2635 case ARM::VST3d32_UPD:
2636 case ARM::VST3q8_UPD:
2637 case ARM::VST3q16_UPD:
2638 case ARM::VST3q32_UPD:
2639 case ARM::VST4d8_UPD:
2640 case ARM::VST4d16_UPD:
2641 case ARM::VST4d32_UPD:
2642 case ARM::VST4q8_UPD:
2643 case ARM::VST4q16_UPD:
2644 case ARM::VST4q32_UPD:
2645 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2646 return MCDisassembler::Fail;
2652 // AddrMode6 Base (register+alignment)
2653 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2654 return MCDisassembler::Fail;
2656 // AddrMode6 Offset (register)
2657 switch (Inst.getOpcode()) {
2660 Inst.addOperand(MCOperand::CreateReg(0));
2661 else if (Rm != 0xF) {
2662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2663 return MCDisassembler::Fail;
2666 case ARM::VST1d8wb_fixed:
2667 case ARM::VST1d16wb_fixed:
2668 case ARM::VST1d32wb_fixed:
2669 case ARM::VST1d64wb_fixed:
2670 case ARM::VST1q8wb_fixed:
2671 case ARM::VST1q16wb_fixed:
2672 case ARM::VST1q32wb_fixed:
2673 case ARM::VST1q64wb_fixed:
2674 case ARM::VST1d8Twb_fixed:
2675 case ARM::VST1d16Twb_fixed:
2676 case ARM::VST1d32Twb_fixed:
2677 case ARM::VST1d64Twb_fixed:
2678 case ARM::VST1d8Qwb_fixed:
2679 case ARM::VST1d16Qwb_fixed:
2680 case ARM::VST1d32Qwb_fixed:
2681 case ARM::VST1d64Qwb_fixed:
2682 case ARM::VST2d8wb_fixed:
2683 case ARM::VST2d16wb_fixed:
2684 case ARM::VST2d32wb_fixed:
2685 case ARM::VST2q8wb_fixed:
2686 case ARM::VST2q16wb_fixed:
2687 case ARM::VST2q32wb_fixed:
2688 case ARM::VST2b8wb_fixed:
2689 case ARM::VST2b16wb_fixed:
2690 case ARM::VST2b32wb_fixed:
2695 // First input register
2696 switch (Inst.getOpcode()) {
2701 case ARM::VST1q16wb_fixed:
2702 case ARM::VST1q16wb_register:
2703 case ARM::VST1q32wb_fixed:
2704 case ARM::VST1q32wb_register:
2705 case ARM::VST1q64wb_fixed:
2706 case ARM::VST1q64wb_register:
2707 case ARM::VST1q8wb_fixed:
2708 case ARM::VST1q8wb_register:
2712 case ARM::VST2d16wb_fixed:
2713 case ARM::VST2d16wb_register:
2714 case ARM::VST2d32wb_fixed:
2715 case ARM::VST2d32wb_register:
2716 case ARM::VST2d8wb_fixed:
2717 case ARM::VST2d8wb_register:
2718 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2719 return MCDisassembler::Fail;
2724 case ARM::VST2b16wb_fixed:
2725 case ARM::VST2b16wb_register:
2726 case ARM::VST2b32wb_fixed:
2727 case ARM::VST2b32wb_register:
2728 case ARM::VST2b8wb_fixed:
2729 case ARM::VST2b8wb_register:
2730 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2731 return MCDisassembler::Fail;
2734 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2735 return MCDisassembler::Fail;
2738 // Second input register
2739 switch (Inst.getOpcode()) {
2743 case ARM::VST3d8_UPD:
2744 case ARM::VST3d16_UPD:
2745 case ARM::VST3d32_UPD:
2749 case ARM::VST4d8_UPD:
2750 case ARM::VST4d16_UPD:
2751 case ARM::VST4d32_UPD:
2752 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2753 return MCDisassembler::Fail;
2758 case ARM::VST3q8_UPD:
2759 case ARM::VST3q16_UPD:
2760 case ARM::VST3q32_UPD:
2764 case ARM::VST4q8_UPD:
2765 case ARM::VST4q16_UPD:
2766 case ARM::VST4q32_UPD:
2767 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2768 return MCDisassembler::Fail;
2774 // Third input register
2775 switch (Inst.getOpcode()) {
2779 case ARM::VST3d8_UPD:
2780 case ARM::VST3d16_UPD:
2781 case ARM::VST3d32_UPD:
2785 case ARM::VST4d8_UPD:
2786 case ARM::VST4d16_UPD:
2787 case ARM::VST4d32_UPD:
2788 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2789 return MCDisassembler::Fail;
2794 case ARM::VST3q8_UPD:
2795 case ARM::VST3q16_UPD:
2796 case ARM::VST3q32_UPD:
2800 case ARM::VST4q8_UPD:
2801 case ARM::VST4q16_UPD:
2802 case ARM::VST4q32_UPD:
2803 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2804 return MCDisassembler::Fail;
2810 // Fourth input register
2811 switch (Inst.getOpcode()) {
2815 case ARM::VST4d8_UPD:
2816 case ARM::VST4d16_UPD:
2817 case ARM::VST4d32_UPD:
2818 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2819 return MCDisassembler::Fail;
2824 case ARM::VST4q8_UPD:
2825 case ARM::VST4q16_UPD:
2826 case ARM::VST4q32_UPD:
2827 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2828 return MCDisassembler::Fail;
2837 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2838 uint64_t Address, const void *Decoder) {
2839 DecodeStatus S = MCDisassembler::Success;
2841 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2842 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2843 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2844 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2845 unsigned align = fieldFromInstruction(Insn, 4, 1);
2846 unsigned size = fieldFromInstruction(Insn, 6, 2);
2848 if (size == 0 && align == 1)
2849 return MCDisassembler::Fail;
2850 align *= (1 << size);
2852 switch (Inst.getOpcode()) {
2853 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2854 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2855 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2856 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2857 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2858 return MCDisassembler::Fail;
2861 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2862 return MCDisassembler::Fail;
2866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2867 return MCDisassembler::Fail;
2870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2871 return MCDisassembler::Fail;
2872 Inst.addOperand(MCOperand::CreateImm(align));
2874 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2875 // variant encodes Rm == 0xf. Anything else is a register offset post-
2876 // increment and we need to add the register operand to the instruction.
2877 if (Rm != 0xD && Rm != 0xF &&
2878 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2879 return MCDisassembler::Fail;
2884 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2885 uint64_t Address, const void *Decoder) {
2886 DecodeStatus S = MCDisassembler::Success;
2888 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2889 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2890 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2891 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2892 unsigned align = fieldFromInstruction(Insn, 4, 1);
2893 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2896 switch (Inst.getOpcode()) {
2897 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2898 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2899 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2900 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2901 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2902 return MCDisassembler::Fail;
2904 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2905 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2906 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2907 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2908 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2909 return MCDisassembler::Fail;
2912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2913 return MCDisassembler::Fail;
2918 Inst.addOperand(MCOperand::CreateImm(0));
2920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2921 return MCDisassembler::Fail;
2922 Inst.addOperand(MCOperand::CreateImm(align));
2924 if (Rm != 0xD && Rm != 0xF) {
2925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2926 return MCDisassembler::Fail;
2932 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2933 uint64_t Address, const void *Decoder) {
2934 DecodeStatus S = MCDisassembler::Success;
2936 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2937 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2938 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2939 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2940 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2942 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2943 return MCDisassembler::Fail;
2944 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2945 return MCDisassembler::Fail;
2946 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2947 return MCDisassembler::Fail;
2949 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2950 return MCDisassembler::Fail;
2953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2954 return MCDisassembler::Fail;
2955 Inst.addOperand(MCOperand::CreateImm(0));
2958 Inst.addOperand(MCOperand::CreateReg(0));
2959 else if (Rm != 0xF) {
2960 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2961 return MCDisassembler::Fail;
2967 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2968 uint64_t Address, const void *Decoder) {
2969 DecodeStatus S = MCDisassembler::Success;
2971 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2972 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2973 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2974 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2975 unsigned size = fieldFromInstruction(Insn, 6, 2);
2976 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2977 unsigned align = fieldFromInstruction(Insn, 4, 1);
2981 return MCDisassembler::Fail;
2992 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2993 return MCDisassembler::Fail;
2994 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2995 return MCDisassembler::Fail;
2996 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2997 return MCDisassembler::Fail;
2998 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2999 return MCDisassembler::Fail;
3001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3002 return MCDisassembler::Fail;
3005 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3006 return MCDisassembler::Fail;
3007 Inst.addOperand(MCOperand::CreateImm(align));
3010 Inst.addOperand(MCOperand::CreateReg(0));
3011 else if (Rm != 0xF) {
3012 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3013 return MCDisassembler::Fail;
3020 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3021 uint64_t Address, const void *Decoder) {
3022 DecodeStatus S = MCDisassembler::Success;
3024 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3025 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3026 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3027 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3028 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3029 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3030 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3031 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3034 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3035 return MCDisassembler::Fail;
3037 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3038 return MCDisassembler::Fail;
3041 Inst.addOperand(MCOperand::CreateImm(imm));
3043 switch (Inst.getOpcode()) {
3044 case ARM::VORRiv4i16:
3045 case ARM::VORRiv2i32:
3046 case ARM::VBICiv4i16:
3047 case ARM::VBICiv2i32:
3048 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3049 return MCDisassembler::Fail;
3051 case ARM::VORRiv8i16:
3052 case ARM::VORRiv4i32:
3053 case ARM::VBICiv8i16:
3054 case ARM::VBICiv4i32:
3055 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3056 return MCDisassembler::Fail;
3065 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3066 uint64_t Address, const void *Decoder) {
3067 DecodeStatus S = MCDisassembler::Success;
3069 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3070 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3071 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3072 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3073 unsigned size = fieldFromInstruction(Insn, 18, 2);
3075 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3076 return MCDisassembler::Fail;
3077 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3078 return MCDisassembler::Fail;
3079 Inst.addOperand(MCOperand::CreateImm(8 << size));
3084 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3085 uint64_t Address, const void *Decoder) {
3086 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3087 return MCDisassembler::Success;
3090 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3091 uint64_t Address, const void *Decoder) {
3092 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3093 return MCDisassembler::Success;
3096 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3097 uint64_t Address, const void *Decoder) {
3098 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3099 return MCDisassembler::Success;
3102 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3103 uint64_t Address, const void *Decoder) {
3104 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3105 return MCDisassembler::Success;
3108 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3109 uint64_t Address, const void *Decoder) {
3110 DecodeStatus S = MCDisassembler::Success;
3112 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3113 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3114 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3115 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3116 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3117 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3118 unsigned op = fieldFromInstruction(Insn, 6, 1);
3120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3121 return MCDisassembler::Fail;
3123 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3124 return MCDisassembler::Fail; // Writeback
3127 switch (Inst.getOpcode()) {
3130 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3131 return MCDisassembler::Fail;
3134 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3135 return MCDisassembler::Fail;
3138 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3139 return MCDisassembler::Fail;
3144 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3145 uint64_t Address, const void *Decoder) {
3146 DecodeStatus S = MCDisassembler::Success;
3148 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3149 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3151 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3152 return MCDisassembler::Fail;
3154 switch(Inst.getOpcode()) {
3156 return MCDisassembler::Fail;
3158 break; // tADR does not explicitly represent the PC as an operand.
3160 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3164 Inst.addOperand(MCOperand::CreateImm(imm));
3168 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3169 uint64_t Address, const void *Decoder) {
3170 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3171 true, 2, Inst, Decoder))
3172 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3173 return MCDisassembler::Success;
3176 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3177 uint64_t Address, const void *Decoder) {
3178 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3179 true, 4, Inst, Decoder))
3180 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3181 return MCDisassembler::Success;
3184 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3185 uint64_t Address, const void *Decoder) {
3186 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3187 true, 2, Inst, Decoder))
3188 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3189 return MCDisassembler::Success;
3192 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3193 uint64_t Address, const void *Decoder) {
3194 DecodeStatus S = MCDisassembler::Success;
3196 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3197 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3199 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3200 return MCDisassembler::Fail;
3201 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3202 return MCDisassembler::Fail;
3207 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3208 uint64_t Address, const void *Decoder) {
3209 DecodeStatus S = MCDisassembler::Success;
3211 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3212 unsigned imm = fieldFromInstruction(Val, 3, 5);
3214 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3215 return MCDisassembler::Fail;
3216 Inst.addOperand(MCOperand::CreateImm(imm));
3221 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3222 uint64_t Address, const void *Decoder) {
3223 unsigned imm = Val << 2;
3225 Inst.addOperand(MCOperand::CreateImm(imm));
3226 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3228 return MCDisassembler::Success;
3231 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3232 uint64_t Address, const void *Decoder) {
3233 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3234 Inst.addOperand(MCOperand::CreateImm(Val));
3236 return MCDisassembler::Success;
3239 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3240 uint64_t Address, const void *Decoder) {
3241 DecodeStatus S = MCDisassembler::Success;
3243 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3244 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3245 unsigned imm = fieldFromInstruction(Val, 0, 2);
3247 // Thumb stores cannot use PC as dest register.
3248 switch (Inst.getOpcode()) {
3253 return MCDisassembler::Fail;
3258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3259 return MCDisassembler::Fail;
3260 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3261 return MCDisassembler::Fail;
3262 Inst.addOperand(MCOperand::CreateImm(imm));
3267 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3268 uint64_t Address, const void *Decoder) {
3269 DecodeStatus S = MCDisassembler::Success;
3271 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3272 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3274 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3276 bool hasMP = featureBits & ARM::FeatureMP;
3277 bool hasV7Ops = featureBits & ARM::HasV7Ops;
3280 switch (Inst.getOpcode()) {
3282 Inst.setOpcode(ARM::t2LDRBpci);
3285 Inst.setOpcode(ARM::t2LDRHpci);
3288 Inst.setOpcode(ARM::t2LDRSHpci);
3291 Inst.setOpcode(ARM::t2LDRSBpci);
3294 Inst.setOpcode(ARM::t2LDRpci);
3297 Inst.setOpcode(ARM::t2PLDpci);
3300 Inst.setOpcode(ARM::t2PLIpci);
3303 return MCDisassembler::Fail;
3306 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3310 switch (Inst.getOpcode()) {
3312 return MCDisassembler::Fail;
3314 Inst.setOpcode(ARM::t2PLDWs);
3317 Inst.setOpcode(ARM::t2PLIs);
3323 switch (Inst.getOpcode()) {
3328 return MCDisassembler::Fail;
3331 if (!hasV7Ops || !hasMP)
3332 return MCDisassembler::Fail;
3335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3336 return MCDisassembler::Fail;
3339 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3340 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3341 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3342 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3343 return MCDisassembler::Fail;
3348 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3349 uint64_t Address, const void* Decoder) {
3350 DecodeStatus S = MCDisassembler::Success;
3352 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3353 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3354 unsigned U = fieldFromInstruction(Insn, 9, 1);
3355 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3358 unsigned add = fieldFromInstruction(Insn, 9, 1);
3360 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3362 bool hasMP = featureBits & ARM::FeatureMP;
3363 bool hasV7Ops = featureBits & ARM::HasV7Ops;
3366 switch (Inst.getOpcode()) {
3368 Inst.setOpcode(ARM::t2LDRpci);
3371 Inst.setOpcode(ARM::t2LDRBpci);
3373 case ARM::t2LDRSBi8:
3374 Inst.setOpcode(ARM::t2LDRSBpci);
3377 Inst.setOpcode(ARM::t2LDRHpci);
3379 case ARM::t2LDRSHi8:
3380 Inst.setOpcode(ARM::t2LDRSHpci);
3383 Inst.setOpcode(ARM::t2PLDpci);
3386 Inst.setOpcode(ARM::t2PLIpci);
3389 return MCDisassembler::Fail;
3391 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3395 switch (Inst.getOpcode()) {
3396 case ARM::t2LDRSHi8:
3397 return MCDisassembler::Fail;
3400 Inst.setOpcode(ARM::t2PLDWi8);
3402 case ARM::t2LDRSBi8:
3403 Inst.setOpcode(ARM::t2PLIi8);
3410 switch (Inst.getOpcode()) {
3415 return MCDisassembler::Fail;
3418 if (!hasV7Ops || !hasMP)
3419 return MCDisassembler::Fail;
3422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3423 return MCDisassembler::Fail;
3426 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3427 return MCDisassembler::Fail;
3431 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3432 uint64_t Address, const void* Decoder) {
3433 DecodeStatus S = MCDisassembler::Success;
3435 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3436 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3437 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3440 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3442 bool hasMP = (featureBits & ARM::FeatureMP);
3443 bool hasV7Ops = (featureBits & ARM::HasV7Ops);
3446 switch (Inst.getOpcode()) {
3448 Inst.setOpcode(ARM::t2LDRpci);
3450 case ARM::t2LDRHi12:
3451 Inst.setOpcode(ARM::t2LDRHpci);
3453 case ARM::t2LDRSHi12:
3454 Inst.setOpcode(ARM::t2LDRSHpci);
3456 case ARM::t2LDRBi12:
3457 Inst.setOpcode(ARM::t2LDRBpci);
3459 case ARM::t2LDRSBi12:
3460 Inst.setOpcode(ARM::t2LDRSBpci);
3463 Inst.setOpcode(ARM::t2PLDpci);
3466 Inst.setOpcode(ARM::t2PLIpci);
3469 return MCDisassembler::Fail;
3471 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3475 switch (Inst.getOpcode()) {
3476 case ARM::t2LDRSHi12:
3477 return MCDisassembler::Fail;
3478 case ARM::t2LDRHi12:
3479 Inst.setOpcode(ARM::t2PLDWi12);
3481 case ARM::t2LDRSBi12:
3482 Inst.setOpcode(ARM::t2PLIi12);
3489 switch (Inst.getOpcode()) {
3494 return MCDisassembler::Fail;
3496 case ARM::t2PLDWi12:
3497 if (!hasV7Ops || !hasMP)
3498 return MCDisassembler::Fail;
3501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3502 return MCDisassembler::Fail;
3505 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3506 return MCDisassembler::Fail;
3510 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3511 uint64_t Address, const void* Decoder) {
3512 DecodeStatus S = MCDisassembler::Success;
3514 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3515 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3516 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3520 switch (Inst.getOpcode()) {
3522 Inst.setOpcode(ARM::t2LDRpci);
3525 Inst.setOpcode(ARM::t2LDRBpci);
3528 Inst.setOpcode(ARM::t2LDRHpci);
3531 Inst.setOpcode(ARM::t2LDRSBpci);
3534 Inst.setOpcode(ARM::t2LDRSHpci);
3537 return MCDisassembler::Fail;
3539 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3542 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3543 return MCDisassembler::Fail;
3544 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3545 return MCDisassembler::Fail;
3549 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3550 uint64_t Address, const void* Decoder) {
3551 DecodeStatus S = MCDisassembler::Success;
3553 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3554 unsigned U = fieldFromInstruction(Insn, 23, 1);
3555 int imm = fieldFromInstruction(Insn, 0, 12);
3557 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3559 bool hasV7Ops = (featureBits & ARM::HasV7Ops);
3562 switch (Inst.getOpcode()) {
3563 case ARM::t2LDRBpci:
3564 case ARM::t2LDRHpci:
3565 Inst.setOpcode(ARM::t2PLDpci);
3567 case ARM::t2LDRSBpci:
3568 Inst.setOpcode(ARM::t2PLIpci);
3570 case ARM::t2LDRSHpci:
3571 return MCDisassembler::Fail;
3577 switch(Inst.getOpcode()) {
3582 return MCDisassembler::Fail;
3585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3586 return MCDisassembler::Fail;
3590 // Special case for #-0.
3596 Inst.addOperand(MCOperand::CreateImm(imm));
3601 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3602 uint64_t Address, const void *Decoder) {
3604 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3606 int imm = Val & 0xFF;
3608 if (!(Val & 0x100)) imm *= -1;
3609 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3612 return MCDisassembler::Success;
3615 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3616 uint64_t Address, const void *Decoder) {
3617 DecodeStatus S = MCDisassembler::Success;
3619 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3620 unsigned imm = fieldFromInstruction(Val, 0, 9);
3622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3623 return MCDisassembler::Fail;
3624 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3625 return MCDisassembler::Fail;
3630 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3631 uint64_t Address, const void *Decoder) {
3632 DecodeStatus S = MCDisassembler::Success;
3634 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3635 unsigned imm = fieldFromInstruction(Val, 0, 8);
3637 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3638 return MCDisassembler::Fail;
3640 Inst.addOperand(MCOperand::CreateImm(imm));
3645 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3646 uint64_t Address, const void *Decoder) {
3647 int imm = Val & 0xFF;
3650 else if (!(Val & 0x100))
3652 Inst.addOperand(MCOperand::CreateImm(imm));
3654 return MCDisassembler::Success;
3658 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3659 uint64_t Address, const void *Decoder) {
3660 DecodeStatus S = MCDisassembler::Success;
3662 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3663 unsigned imm = fieldFromInstruction(Val, 0, 9);
3665 // Thumb stores cannot use PC as dest register.
3666 switch (Inst.getOpcode()) {
3674 return MCDisassembler::Fail;
3680 // Some instructions always use an additive offset.
3681 switch (Inst.getOpcode()) {
3696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3697 return MCDisassembler::Fail;
3698 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3699 return MCDisassembler::Fail;
3704 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3705 uint64_t Address, const void *Decoder) {
3706 DecodeStatus S = MCDisassembler::Success;
3708 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3709 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3710 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3711 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3713 unsigned load = fieldFromInstruction(Insn, 20, 1);
3716 switch (Inst.getOpcode()) {
3717 case ARM::t2LDR_PRE:
3718 case ARM::t2LDR_POST:
3719 Inst.setOpcode(ARM::t2LDRpci);
3721 case ARM::t2LDRB_PRE:
3722 case ARM::t2LDRB_POST:
3723 Inst.setOpcode(ARM::t2LDRBpci);
3725 case ARM::t2LDRH_PRE:
3726 case ARM::t2LDRH_POST:
3727 Inst.setOpcode(ARM::t2LDRHpci);
3729 case ARM::t2LDRSB_PRE:
3730 case ARM::t2LDRSB_POST:
3732 Inst.setOpcode(ARM::t2PLIpci);
3734 Inst.setOpcode(ARM::t2LDRSBpci);
3736 case ARM::t2LDRSH_PRE:
3737 case ARM::t2LDRSH_POST:
3738 Inst.setOpcode(ARM::t2LDRSHpci);
3741 return MCDisassembler::Fail;
3743 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3748 return MCDisassembler::Fail;
3751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3752 return MCDisassembler::Fail;
3755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3756 return MCDisassembler::Fail;
3759 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3760 return MCDisassembler::Fail;
3765 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3766 uint64_t Address, const void *Decoder) {
3767 DecodeStatus S = MCDisassembler::Success;
3769 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3770 unsigned imm = fieldFromInstruction(Val, 0, 12);
3772 // Thumb stores cannot use PC as dest register.
3773 switch (Inst.getOpcode()) {
3775 case ARM::t2STRBi12:
3776 case ARM::t2STRHi12:
3778 return MCDisassembler::Fail;
3783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3784 return MCDisassembler::Fail;
3785 Inst.addOperand(MCOperand::CreateImm(imm));
3791 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3792 uint64_t Address, const void *Decoder) {
3793 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3795 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3796 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3797 Inst.addOperand(MCOperand::CreateImm(imm));
3799 return MCDisassembler::Success;
3802 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3803 uint64_t Address, const void *Decoder) {
3804 DecodeStatus S = MCDisassembler::Success;
3806 if (Inst.getOpcode() == ARM::tADDrSP) {
3807 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3808 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3811 return MCDisassembler::Fail;
3812 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3814 return MCDisassembler::Fail;
3815 } else if (Inst.getOpcode() == ARM::tADDspr) {
3816 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3818 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3819 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3821 return MCDisassembler::Fail;
3827 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3828 uint64_t Address, const void *Decoder) {
3829 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3830 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3832 Inst.addOperand(MCOperand::CreateImm(imod));
3833 Inst.addOperand(MCOperand::CreateImm(flags));
3835 return MCDisassembler::Success;
3838 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3839 uint64_t Address, const void *Decoder) {
3840 DecodeStatus S = MCDisassembler::Success;
3841 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3842 unsigned add = fieldFromInstruction(Insn, 4, 1);
3844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3845 return MCDisassembler::Fail;
3846 Inst.addOperand(MCOperand::CreateImm(add));
3851 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3852 uint64_t Address, const void *Decoder) {
3853 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3854 // Note only one trailing zero not two. Also the J1 and J2 values are from
3855 // the encoded instruction. So here change to I1 and I2 values via:
3856 // I1 = NOT(J1 EOR S);
3857 // I2 = NOT(J2 EOR S);
3858 // and build the imm32 with two trailing zeros as documented:
3859 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3860 unsigned S = (Val >> 23) & 1;
3861 unsigned J1 = (Val >> 22) & 1;
3862 unsigned J2 = (Val >> 21) & 1;
3863 unsigned I1 = !(J1 ^ S);
3864 unsigned I2 = !(J2 ^ S);
3865 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3866 int imm32 = SignExtend32<25>(tmp << 1);
3868 if (!tryAddingSymbolicOperand(Address,
3869 (Address & ~2u) + imm32 + 4,
3870 true, 4, Inst, Decoder))
3871 Inst.addOperand(MCOperand::CreateImm(imm32));
3872 return MCDisassembler::Success;
3875 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3876 uint64_t Address, const void *Decoder) {
3877 if (Val == 0xA || Val == 0xB)
3878 return MCDisassembler::Fail;
3880 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3882 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3883 return MCDisassembler::Fail;
3885 Inst.addOperand(MCOperand::CreateImm(Val));
3886 return MCDisassembler::Success;
3890 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3891 uint64_t Address, const void *Decoder) {
3892 DecodeStatus S = MCDisassembler::Success;
3894 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3895 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3897 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3898 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3899 return MCDisassembler::Fail;
3900 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3901 return MCDisassembler::Fail;
3906 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3907 uint64_t Address, const void *Decoder) {
3908 DecodeStatus S = MCDisassembler::Success;
3910 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3911 if (pred == 0xE || pred == 0xF) {
3912 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3915 return MCDisassembler::Fail;
3917 Inst.setOpcode(ARM::t2DSB);
3920 Inst.setOpcode(ARM::t2DMB);
3923 Inst.setOpcode(ARM::t2ISB);
3927 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3928 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3931 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3932 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3933 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3934 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3935 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3937 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3938 return MCDisassembler::Fail;
3939 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3940 return MCDisassembler::Fail;
3945 // Decode a shifted immediate operand. These basically consist
3946 // of an 8-bit value, and a 4-bit directive that specifies either
3947 // a splat operation or a rotation.
3948 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3949 uint64_t Address, const void *Decoder) {
3950 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3952 unsigned byte = fieldFromInstruction(Val, 8, 2);
3953 unsigned imm = fieldFromInstruction(Val, 0, 8);
3956 Inst.addOperand(MCOperand::CreateImm(imm));
3959 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3962 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3965 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3970 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3971 unsigned rot = fieldFromInstruction(Val, 7, 5);
3972 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3973 Inst.addOperand(MCOperand::CreateImm(imm));
3976 return MCDisassembler::Success;
3980 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3981 uint64_t Address, const void *Decoder){
3982 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3983 true, 2, Inst, Decoder))
3984 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3985 return MCDisassembler::Success;
3988 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3989 uint64_t Address, const void *Decoder){
3990 // Val is passed in as S:J1:J2:imm10:imm11
3991 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3992 // the encoded instruction. So here change to I1 and I2 values via:
3993 // I1 = NOT(J1 EOR S);
3994 // I2 = NOT(J2 EOR S);
3995 // and build the imm32 with one trailing zero as documented:
3996 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3997 unsigned S = (Val >> 23) & 1;
3998 unsigned J1 = (Val >> 22) & 1;
3999 unsigned J2 = (Val >> 21) & 1;
4000 unsigned I1 = !(J1 ^ S);
4001 unsigned I2 = !(J2 ^ S);
4002 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4003 int imm32 = SignExtend32<25>(tmp << 1);
4005 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4006 true, 4, Inst, Decoder))
4007 Inst.addOperand(MCOperand::CreateImm(imm32));
4008 return MCDisassembler::Success;
4011 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4012 uint64_t Address, const void *Decoder) {
4014 return MCDisassembler::Fail;
4016 Inst.addOperand(MCOperand::CreateImm(Val));
4017 return MCDisassembler::Success;
4020 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4021 uint64_t Address, const void *Decoder) {
4023 return MCDisassembler::Fail;
4025 Inst.addOperand(MCOperand::CreateImm(Val));
4026 return MCDisassembler::Success;
4029 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4030 uint64_t Address, const void *Decoder) {
4031 DecodeStatus S = MCDisassembler::Success;
4032 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
4034 if (FeatureBits & ARM::FeatureMClass) {
4035 unsigned ValLow = Val & 0xff;
4037 // Validate the SYSm value first.
4052 case 18: // basepri_max
4053 case 19: // faultmask
4054 if (!(FeatureBits & ARM::HasV7Ops))
4055 // Values basepri, basepri_max and faultmask are only valid for v7m.
4056 return MCDisassembler::Fail;
4059 return MCDisassembler::Fail;
4062 if (Inst.getOpcode() == ARM::t2MSR_M) {
4063 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4064 if (!(FeatureBits & ARM::HasV7Ops)) {
4065 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4068 S = MCDisassembler::SoftFail;
4071 // The ARMv7-M architecture stores an additional 2-bit mask value in
4072 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4073 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4074 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4075 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4076 // only if the processor includes the DSP extension.
4077 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4078 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
4079 S = MCDisassembler::SoftFail;
4085 return MCDisassembler::Fail;
4087 Inst.addOperand(MCOperand::CreateImm(Val));
4091 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4092 uint64_t Address, const void *Decoder) {
4094 unsigned R = fieldFromInstruction(Val, 5, 1);
4095 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4097 // The table of encodings for these banked registers comes from B9.2.3 of the
4098 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4099 // neater. So by fiat, these values are UNPREDICTABLE:
4101 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4102 SysM == 0x1a || SysM == 0x1b)
4103 return MCDisassembler::SoftFail;
4105 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4106 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4107 return MCDisassembler::SoftFail;
4110 Inst.addOperand(MCOperand::CreateImm(Val));
4111 return MCDisassembler::Success;
4114 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4115 uint64_t Address, const void *Decoder) {
4116 DecodeStatus S = MCDisassembler::Success;
4118 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4119 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4120 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4123 S = MCDisassembler::SoftFail;
4125 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4126 return MCDisassembler::Fail;
4127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4128 return MCDisassembler::Fail;
4129 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4130 return MCDisassembler::Fail;
4135 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4136 uint64_t Address, const void *Decoder){
4137 DecodeStatus S = MCDisassembler::Success;
4139 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4140 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4141 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4142 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4144 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4145 return MCDisassembler::Fail;
4147 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4148 S = MCDisassembler::SoftFail;
4150 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4151 return MCDisassembler::Fail;
4152 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4153 return MCDisassembler::Fail;
4154 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4155 return MCDisassembler::Fail;
4160 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4161 uint64_t Address, const void *Decoder) {
4162 DecodeStatus S = MCDisassembler::Success;
4164 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4165 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4166 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4167 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4168 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4169 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4171 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4174 return MCDisassembler::Fail;
4175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4176 return MCDisassembler::Fail;
4177 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4178 return MCDisassembler::Fail;
4179 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4180 return MCDisassembler::Fail;
4185 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4186 uint64_t Address, const void *Decoder) {
4187 DecodeStatus S = MCDisassembler::Success;
4189 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4190 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4191 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4192 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4193 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4194 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4195 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4197 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4198 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4201 return MCDisassembler::Fail;
4202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4203 return MCDisassembler::Fail;
4204 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4205 return MCDisassembler::Fail;
4206 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4207 return MCDisassembler::Fail;
4213 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4214 uint64_t Address, const void *Decoder) {
4215 DecodeStatus S = MCDisassembler::Success;
4217 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4218 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4219 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4220 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4221 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4222 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4224 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4227 return MCDisassembler::Fail;
4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4229 return MCDisassembler::Fail;
4230 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4231 return MCDisassembler::Fail;
4232 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4233 return MCDisassembler::Fail;
4238 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4239 uint64_t Address, const void *Decoder) {
4240 DecodeStatus S = MCDisassembler::Success;
4242 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4243 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4244 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4245 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4246 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4247 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4249 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4252 return MCDisassembler::Fail;
4253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4254 return MCDisassembler::Fail;
4255 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4256 return MCDisassembler::Fail;
4257 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4258 return MCDisassembler::Fail;
4263 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4264 uint64_t Address, const void *Decoder) {
4265 DecodeStatus S = MCDisassembler::Success;
4267 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4268 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4269 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4270 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4271 unsigned size = fieldFromInstruction(Insn, 10, 2);
4277 return MCDisassembler::Fail;
4279 if (fieldFromInstruction(Insn, 4, 1))
4280 return MCDisassembler::Fail; // UNDEFINED
4281 index = fieldFromInstruction(Insn, 5, 3);
4284 if (fieldFromInstruction(Insn, 5, 1))
4285 return MCDisassembler::Fail; // UNDEFINED
4286 index = fieldFromInstruction(Insn, 6, 2);
4287 if (fieldFromInstruction(Insn, 4, 1))
4291 if (fieldFromInstruction(Insn, 6, 1))
4292 return MCDisassembler::Fail; // UNDEFINED
4293 index = fieldFromInstruction(Insn, 7, 1);
4295 switch (fieldFromInstruction(Insn, 4, 2)) {
4301 return MCDisassembler::Fail;
4306 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4307 return MCDisassembler::Fail;
4308 if (Rm != 0xF) { // Writeback
4309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4310 return MCDisassembler::Fail;
4312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4313 return MCDisassembler::Fail;
4314 Inst.addOperand(MCOperand::CreateImm(align));
4317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4318 return MCDisassembler::Fail;
4320 Inst.addOperand(MCOperand::CreateReg(0));
4323 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4324 return MCDisassembler::Fail;
4325 Inst.addOperand(MCOperand::CreateImm(index));
4330 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4331 uint64_t Address, const void *Decoder) {
4332 DecodeStatus S = MCDisassembler::Success;
4334 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4335 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4336 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4337 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4338 unsigned size = fieldFromInstruction(Insn, 10, 2);
4344 return MCDisassembler::Fail;
4346 if (fieldFromInstruction(Insn, 4, 1))
4347 return MCDisassembler::Fail; // UNDEFINED
4348 index = fieldFromInstruction(Insn, 5, 3);
4351 if (fieldFromInstruction(Insn, 5, 1))
4352 return MCDisassembler::Fail; // UNDEFINED
4353 index = fieldFromInstruction(Insn, 6, 2);
4354 if (fieldFromInstruction(Insn, 4, 1))
4358 if (fieldFromInstruction(Insn, 6, 1))
4359 return MCDisassembler::Fail; // UNDEFINED
4360 index = fieldFromInstruction(Insn, 7, 1);
4362 switch (fieldFromInstruction(Insn, 4, 2)) {
4368 return MCDisassembler::Fail;
4373 if (Rm != 0xF) { // Writeback
4374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4375 return MCDisassembler::Fail;
4377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4378 return MCDisassembler::Fail;
4379 Inst.addOperand(MCOperand::CreateImm(align));
4382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4383 return MCDisassembler::Fail;
4385 Inst.addOperand(MCOperand::CreateReg(0));
4388 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4389 return MCDisassembler::Fail;
4390 Inst.addOperand(MCOperand::CreateImm(index));
4396 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4397 uint64_t Address, const void *Decoder) {
4398 DecodeStatus S = MCDisassembler::Success;
4400 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4401 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4402 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4403 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4404 unsigned size = fieldFromInstruction(Insn, 10, 2);
4411 return MCDisassembler::Fail;
4413 index = fieldFromInstruction(Insn, 5, 3);
4414 if (fieldFromInstruction(Insn, 4, 1))
4418 index = fieldFromInstruction(Insn, 6, 2);
4419 if (fieldFromInstruction(Insn, 4, 1))
4421 if (fieldFromInstruction(Insn, 5, 1))
4425 if (fieldFromInstruction(Insn, 5, 1))
4426 return MCDisassembler::Fail; // UNDEFINED
4427 index = fieldFromInstruction(Insn, 7, 1);
4428 if (fieldFromInstruction(Insn, 4, 1) != 0)
4430 if (fieldFromInstruction(Insn, 6, 1))
4435 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4436 return MCDisassembler::Fail;
4437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4438 return MCDisassembler::Fail;
4439 if (Rm != 0xF) { // Writeback
4440 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4441 return MCDisassembler::Fail;
4443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4444 return MCDisassembler::Fail;
4445 Inst.addOperand(MCOperand::CreateImm(align));
4448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4449 return MCDisassembler::Fail;
4451 Inst.addOperand(MCOperand::CreateReg(0));
4454 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4455 return MCDisassembler::Fail;
4456 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4457 return MCDisassembler::Fail;
4458 Inst.addOperand(MCOperand::CreateImm(index));
4463 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4464 uint64_t Address, const void *Decoder) {
4465 DecodeStatus S = MCDisassembler::Success;
4467 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4468 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4469 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4470 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4471 unsigned size = fieldFromInstruction(Insn, 10, 2);
4478 return MCDisassembler::Fail;
4480 index = fieldFromInstruction(Insn, 5, 3);
4481 if (fieldFromInstruction(Insn, 4, 1))
4485 index = fieldFromInstruction(Insn, 6, 2);
4486 if (fieldFromInstruction(Insn, 4, 1))
4488 if (fieldFromInstruction(Insn, 5, 1))
4492 if (fieldFromInstruction(Insn, 5, 1))
4493 return MCDisassembler::Fail; // UNDEFINED
4494 index = fieldFromInstruction(Insn, 7, 1);
4495 if (fieldFromInstruction(Insn, 4, 1) != 0)
4497 if (fieldFromInstruction(Insn, 6, 1))
4502 if (Rm != 0xF) { // Writeback
4503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4504 return MCDisassembler::Fail;
4506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4507 return MCDisassembler::Fail;
4508 Inst.addOperand(MCOperand::CreateImm(align));
4511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4512 return MCDisassembler::Fail;
4514 Inst.addOperand(MCOperand::CreateReg(0));
4517 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4518 return MCDisassembler::Fail;
4519 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4520 return MCDisassembler::Fail;
4521 Inst.addOperand(MCOperand::CreateImm(index));
4527 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4528 uint64_t Address, const void *Decoder) {
4529 DecodeStatus S = MCDisassembler::Success;
4531 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4532 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4533 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4534 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4535 unsigned size = fieldFromInstruction(Insn, 10, 2);
4542 return MCDisassembler::Fail;
4544 if (fieldFromInstruction(Insn, 4, 1))
4545 return MCDisassembler::Fail; // UNDEFINED
4546 index = fieldFromInstruction(Insn, 5, 3);
4549 if (fieldFromInstruction(Insn, 4, 1))
4550 return MCDisassembler::Fail; // UNDEFINED
4551 index = fieldFromInstruction(Insn, 6, 2);
4552 if (fieldFromInstruction(Insn, 5, 1))
4556 if (fieldFromInstruction(Insn, 4, 2))
4557 return MCDisassembler::Fail; // UNDEFINED
4558 index = fieldFromInstruction(Insn, 7, 1);
4559 if (fieldFromInstruction(Insn, 6, 1))
4564 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4565 return MCDisassembler::Fail;
4566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4567 return MCDisassembler::Fail;
4568 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4569 return MCDisassembler::Fail;
4571 if (Rm != 0xF) { // Writeback
4572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4573 return MCDisassembler::Fail;
4575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4576 return MCDisassembler::Fail;
4577 Inst.addOperand(MCOperand::CreateImm(align));
4580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4581 return MCDisassembler::Fail;
4583 Inst.addOperand(MCOperand::CreateReg(0));
4586 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4587 return MCDisassembler::Fail;
4588 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4589 return MCDisassembler::Fail;
4590 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4591 return MCDisassembler::Fail;
4592 Inst.addOperand(MCOperand::CreateImm(index));
4597 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4598 uint64_t Address, const void *Decoder) {
4599 DecodeStatus S = MCDisassembler::Success;
4601 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4602 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4603 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4604 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4605 unsigned size = fieldFromInstruction(Insn, 10, 2);
4612 return MCDisassembler::Fail;
4614 if (fieldFromInstruction(Insn, 4, 1))
4615 return MCDisassembler::Fail; // UNDEFINED
4616 index = fieldFromInstruction(Insn, 5, 3);
4619 if (fieldFromInstruction(Insn, 4, 1))
4620 return MCDisassembler::Fail; // UNDEFINED
4621 index = fieldFromInstruction(Insn, 6, 2);
4622 if (fieldFromInstruction(Insn, 5, 1))
4626 if (fieldFromInstruction(Insn, 4, 2))
4627 return MCDisassembler::Fail; // UNDEFINED
4628 index = fieldFromInstruction(Insn, 7, 1);
4629 if (fieldFromInstruction(Insn, 6, 1))
4634 if (Rm != 0xF) { // Writeback
4635 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4636 return MCDisassembler::Fail;
4638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4639 return MCDisassembler::Fail;
4640 Inst.addOperand(MCOperand::CreateImm(align));
4643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4644 return MCDisassembler::Fail;
4646 Inst.addOperand(MCOperand::CreateReg(0));
4649 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4650 return MCDisassembler::Fail;
4651 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4652 return MCDisassembler::Fail;
4653 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4654 return MCDisassembler::Fail;
4655 Inst.addOperand(MCOperand::CreateImm(index));
4661 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4662 uint64_t Address, const void *Decoder) {
4663 DecodeStatus S = MCDisassembler::Success;
4665 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4666 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4667 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4668 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4669 unsigned size = fieldFromInstruction(Insn, 10, 2);
4676 return MCDisassembler::Fail;
4678 if (fieldFromInstruction(Insn, 4, 1))
4680 index = fieldFromInstruction(Insn, 5, 3);
4683 if (fieldFromInstruction(Insn, 4, 1))
4685 index = fieldFromInstruction(Insn, 6, 2);
4686 if (fieldFromInstruction(Insn, 5, 1))
4690 switch (fieldFromInstruction(Insn, 4, 2)) {
4694 return MCDisassembler::Fail;
4696 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4699 index = fieldFromInstruction(Insn, 7, 1);
4700 if (fieldFromInstruction(Insn, 6, 1))
4705 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4706 return MCDisassembler::Fail;
4707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4708 return MCDisassembler::Fail;
4709 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4710 return MCDisassembler::Fail;
4711 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4712 return MCDisassembler::Fail;
4714 if (Rm != 0xF) { // Writeback
4715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4716 return MCDisassembler::Fail;
4718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4719 return MCDisassembler::Fail;
4720 Inst.addOperand(MCOperand::CreateImm(align));
4723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4724 return MCDisassembler::Fail;
4726 Inst.addOperand(MCOperand::CreateReg(0));
4729 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4730 return MCDisassembler::Fail;
4731 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4732 return MCDisassembler::Fail;
4733 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4734 return MCDisassembler::Fail;
4735 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4736 return MCDisassembler::Fail;
4737 Inst.addOperand(MCOperand::CreateImm(index));
4742 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4743 uint64_t Address, const void *Decoder) {
4744 DecodeStatus S = MCDisassembler::Success;
4746 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4747 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4748 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4749 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4750 unsigned size = fieldFromInstruction(Insn, 10, 2);
4757 return MCDisassembler::Fail;
4759 if (fieldFromInstruction(Insn, 4, 1))
4761 index = fieldFromInstruction(Insn, 5, 3);
4764 if (fieldFromInstruction(Insn, 4, 1))
4766 index = fieldFromInstruction(Insn, 6, 2);
4767 if (fieldFromInstruction(Insn, 5, 1))
4771 switch (fieldFromInstruction(Insn, 4, 2)) {
4775 return MCDisassembler::Fail;
4777 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4780 index = fieldFromInstruction(Insn, 7, 1);
4781 if (fieldFromInstruction(Insn, 6, 1))
4786 if (Rm != 0xF) { // Writeback
4787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4788 return MCDisassembler::Fail;
4790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4791 return MCDisassembler::Fail;
4792 Inst.addOperand(MCOperand::CreateImm(align));
4795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4796 return MCDisassembler::Fail;
4798 Inst.addOperand(MCOperand::CreateReg(0));
4801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4802 return MCDisassembler::Fail;
4803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4804 return MCDisassembler::Fail;
4805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4806 return MCDisassembler::Fail;
4807 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4808 return MCDisassembler::Fail;
4809 Inst.addOperand(MCOperand::CreateImm(index));
4814 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4815 uint64_t Address, const void *Decoder) {
4816 DecodeStatus S = MCDisassembler::Success;
4817 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4818 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4819 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4820 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4821 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4823 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4824 S = MCDisassembler::SoftFail;
4826 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4827 return MCDisassembler::Fail;
4828 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4829 return MCDisassembler::Fail;
4830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4831 return MCDisassembler::Fail;
4832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4833 return MCDisassembler::Fail;
4834 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4835 return MCDisassembler::Fail;
4840 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4841 uint64_t Address, const void *Decoder) {
4842 DecodeStatus S = MCDisassembler::Success;
4843 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4844 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4845 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4846 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4847 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4849 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4850 S = MCDisassembler::SoftFail;
4852 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4853 return MCDisassembler::Fail;
4854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4855 return MCDisassembler::Fail;
4856 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4857 return MCDisassembler::Fail;
4858 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4859 return MCDisassembler::Fail;
4860 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4861 return MCDisassembler::Fail;
4866 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4867 uint64_t Address, const void *Decoder) {
4868 DecodeStatus S = MCDisassembler::Success;
4869 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4870 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4874 S = MCDisassembler::SoftFail;
4878 return MCDisassembler::Fail;
4880 Inst.addOperand(MCOperand::CreateImm(pred));
4881 Inst.addOperand(MCOperand::CreateImm(mask));
4886 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4887 uint64_t Address, const void *Decoder) {
4888 DecodeStatus S = MCDisassembler::Success;
4890 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4891 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4892 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4893 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4894 unsigned W = fieldFromInstruction(Insn, 21, 1);
4895 unsigned U = fieldFromInstruction(Insn, 23, 1);
4896 unsigned P = fieldFromInstruction(Insn, 24, 1);
4897 bool writeback = (W == 1) | (P == 0);
4899 addr |= (U << 8) | (Rn << 9);
4901 if (writeback && (Rn == Rt || Rn == Rt2))
4902 Check(S, MCDisassembler::SoftFail);
4904 Check(S, MCDisassembler::SoftFail);
4907 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4908 return MCDisassembler::Fail;
4910 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4911 return MCDisassembler::Fail;
4912 // Writeback operand
4913 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4914 return MCDisassembler::Fail;
4916 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4917 return MCDisassembler::Fail;
4923 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4924 uint64_t Address, const void *Decoder) {
4925 DecodeStatus S = MCDisassembler::Success;
4927 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4928 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4929 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4930 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4931 unsigned W = fieldFromInstruction(Insn, 21, 1);
4932 unsigned U = fieldFromInstruction(Insn, 23, 1);
4933 unsigned P = fieldFromInstruction(Insn, 24, 1);
4934 bool writeback = (W == 1) | (P == 0);
4936 addr |= (U << 8) | (Rn << 9);
4938 if (writeback && (Rn == Rt || Rn == Rt2))
4939 Check(S, MCDisassembler::SoftFail);
4941 // Writeback operand
4942 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4943 return MCDisassembler::Fail;
4945 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4946 return MCDisassembler::Fail;
4948 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4949 return MCDisassembler::Fail;
4951 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4952 return MCDisassembler::Fail;
4957 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4958 uint64_t Address, const void *Decoder) {
4959 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4960 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4961 if (sign1 != sign2) return MCDisassembler::Fail;
4963 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4964 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4965 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4967 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4969 return MCDisassembler::Success;
4972 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4974 const void *Decoder) {
4975 DecodeStatus S = MCDisassembler::Success;
4977 // Shift of "asr #32" is not allowed in Thumb2 mode.
4978 if (Val == 0x20) S = MCDisassembler::SoftFail;
4979 Inst.addOperand(MCOperand::CreateImm(Val));
4983 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4984 uint64_t Address, const void *Decoder) {
4985 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4986 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4987 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4988 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4991 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4993 DecodeStatus S = MCDisassembler::Success;
4995 if (Rt == Rn || Rn == Rt2)
4996 S = MCDisassembler::SoftFail;
4998 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4999 return MCDisassembler::Fail;
5000 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5001 return MCDisassembler::Fail;
5002 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5003 return MCDisassembler::Fail;
5004 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5005 return MCDisassembler::Fail;
5010 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5011 uint64_t Address, const void *Decoder) {
5012 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5013 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5014 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5015 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5016 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5017 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5018 unsigned op = fieldFromInstruction(Insn, 5, 1);
5020 DecodeStatus S = MCDisassembler::Success;
5022 // VMOVv2f32 is ambiguous with these decodings.
5023 if (!(imm & 0x38) && cmode == 0xF) {
5024 if (op == 1) return MCDisassembler::Fail;
5025 Inst.setOpcode(ARM::VMOVv2f32);
5026 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5029 if (!(imm & 0x20)) return MCDisassembler::Fail;
5031 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5032 return MCDisassembler::Fail;
5033 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5034 return MCDisassembler::Fail;
5035 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5040 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5041 uint64_t Address, const void *Decoder) {
5042 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5043 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5044 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5045 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5046 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5047 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5048 unsigned op = fieldFromInstruction(Insn, 5, 1);
5050 DecodeStatus S = MCDisassembler::Success;
5052 // VMOVv4f32 is ambiguous with these decodings.
5053 if (!(imm & 0x38) && cmode == 0xF) {
5054 if (op == 1) return MCDisassembler::Fail;
5055 Inst.setOpcode(ARM::VMOVv4f32);
5056 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5059 if (!(imm & 0x20)) return MCDisassembler::Fail;
5061 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5062 return MCDisassembler::Fail;
5063 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5064 return MCDisassembler::Fail;
5065 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5070 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5071 uint64_t Address, const void *Decoder) {
5072 DecodeStatus S = MCDisassembler::Success;
5074 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5075 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5076 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5077 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5078 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5080 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5081 S = MCDisassembler::SoftFail;
5083 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5084 return MCDisassembler::Fail;
5085 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5086 return MCDisassembler::Fail;
5087 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5088 return MCDisassembler::Fail;
5089 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5090 return MCDisassembler::Fail;
5091 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5092 return MCDisassembler::Fail;
5097 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
5098 uint64_t Address, const void *Decoder) {
5100 DecodeStatus S = MCDisassembler::Success;
5102 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5103 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5104 unsigned cop = fieldFromInstruction(Val, 8, 4);
5105 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5106 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5108 if ((cop & ~0x1) == 0xa)
5109 return MCDisassembler::Fail;
5112 S = MCDisassembler::SoftFail;
5114 Inst.addOperand(MCOperand::CreateImm(cop));
5115 Inst.addOperand(MCOperand::CreateImm(opc1));
5116 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5117 return MCDisassembler::Fail;
5118 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5119 return MCDisassembler::Fail;
5120 Inst.addOperand(MCOperand::CreateImm(CRm));