1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "llvm/MC/MCDisassembler.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/LEB128.h"
25 #include "llvm/Support/MemoryObject.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
35 // Handles the condition code status of instructions in IT blocks
39 // Returns the condition code for instruction in IT block
41 unsigned CC = ARMCC::AL;
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 ITStates.push_back(CCBits);
77 ITStates.push_back(CCBits ^ 1);
79 ITStates.push_back(CCBits);
83 std::vector<unsigned char> ITStates;
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
91 /// Constructor - Initializes the disassembler.
93 ARMDisassembler(const MCSubtargetInfo &STI) :
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
102 const MemoryObject ®ion, uint64_t address,
103 raw_ostream &vStream,
104 raw_ostream &cStream) const override;
107 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
108 class ThumbDisassembler : public MCDisassembler {
110 /// Constructor - Initializes the disassembler.
112 ThumbDisassembler(const MCSubtargetInfo &STI) :
113 MCDisassembler(STI) {
116 ~ThumbDisassembler() {
119 /// getInstruction - See MCDisassembler.
120 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
121 const MemoryObject ®ion, uint64_t address,
122 raw_ostream &vStream,
123 raw_ostream &cStream) const override;
126 mutable ITStatus ITBlock;
127 DecodeStatus AddThumbPredicate(MCInst&) const;
128 void UpdateThumbVFPPredicate(MCInst&) const;
132 static bool Check(DecodeStatus &Out, DecodeStatus In) {
134 case MCDisassembler::Success:
135 // Out stays the same.
137 case MCDisassembler::SoftFail:
140 case MCDisassembler::Fail:
144 llvm_unreachable("Invalid DecodeStatus!");
148 // Forward declare these because the autogenerated code will reference them.
149 // Definitions are further down.
150 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
153 unsigned RegNo, uint64_t Address,
154 const void *Decoder);
155 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
156 unsigned RegNo, uint64_t Address,
157 const void *Decoder);
158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
175 const void *Decoder);
176 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
181 unsigned RegNo, uint64_t Address,
182 const void *Decoder);
184 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
204 const void *Decoder);
205 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
217 const void *Decoder);
218 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
345 uint64_t Address, const void* Decoder);
346 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
347 uint64_t Address, const void* Decoder);
348 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
349 uint64_t Address, const void* Decoder);
350 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
395 uint64_t Address, const void *Decoder);
397 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
398 uint64_t Address, const void *Decoder);
399 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
400 uint64_t Address, const void *Decoder);
401 #include "ARMGenDisassemblerTables.inc"
403 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
404 return new ARMDisassembler(STI);
407 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
408 return new ThumbDisassembler(STI);
411 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
412 const MemoryObject &Region,
415 raw_ostream &cs) const {
420 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
421 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
423 // We want to read exactly 4 bytes of data.
424 if (Region.readBytes(Address, 4, bytes) == -1) {
426 return MCDisassembler::Fail;
429 // Encoded as a small-endian 32-bit word in the stream.
430 uint32_t insn = (bytes[3] << 24) |
435 // Calling the auto-generated decoder function.
436 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
438 if (result != MCDisassembler::Fail) {
443 // VFP and NEON instructions, similarly, are shared between ARM
446 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
447 if (result != MCDisassembler::Fail) {
453 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
454 if (result != MCDisassembler::Fail) {
460 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
462 if (result != MCDisassembler::Fail) {
464 // Add a fake predicate operand, because we share these instruction
465 // definitions with Thumb2 where these instructions are predicable.
466 if (!DecodePredicateOperand(MI, 0xE, Address, this))
467 return MCDisassembler::Fail;
472 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
474 if (result != MCDisassembler::Fail) {
476 // Add a fake predicate operand, because we share these instruction
477 // definitions with Thumb2 where these instructions are predicable.
478 if (!DecodePredicateOperand(MI, 0xE, Address, this))
479 return MCDisassembler::Fail;
484 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
486 if (result != MCDisassembler::Fail) {
488 // Add a fake predicate operand, because we share these instruction
489 // definitions with Thumb2 where these instructions are predicable.
490 if (!DecodePredicateOperand(MI, 0xE, Address, this))
491 return MCDisassembler::Fail;
496 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address,
498 if (result != MCDisassembler::Fail) {
504 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address,
506 if (result != MCDisassembler::Fail) {
513 return MCDisassembler::Fail;
517 extern const MCInstrDesc ARMInsts[];
520 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
521 /// immediate Value in the MCInst. The immediate Value has had any PC
522 /// adjustment made by the caller. If the instruction is a branch instruction
523 /// then isBranch is true, else false. If the getOpInfo() function was set as
524 /// part of the setupForSymbolicDisassembly() call then that function is called
525 /// to get any symbolic information at the Address for this instruction. If
526 /// that returns non-zero then the symbolic information it returns is used to
527 /// create an MCExpr and that is added as an operand to the MCInst. If
528 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
529 /// Value is done and if a symbol is found an MCExpr is created with that, else
530 /// an MCExpr with Value is created. This function returns true if it adds an
531 /// operand to the MCInst and false otherwise.
532 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
533 bool isBranch, uint64_t InstSize,
534 MCInst &MI, const void *Decoder) {
535 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
536 // FIXME: Does it make sense for value to be negative?
537 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
538 /* Offset */ 0, InstSize);
541 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
542 /// referenced by a load instruction with the base register that is the Pc.
543 /// These can often be values in a literal pool near the Address of the
544 /// instruction. The Address of the instruction and its immediate Value are
545 /// used as a possible literal pool entry. The SymbolLookUp call back will
546 /// return the name of a symbol referenced by the literal pool's entry if
547 /// the referenced address is that of a symbol. Or it will return a pointer to
548 /// a literal 'C' string if the referenced address of the literal pool's entry
549 /// is an address into a section with 'C' string literals.
550 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
551 const void *Decoder) {
552 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
553 Dis->tryAddingPcLoadReferenceComment(Value, Address);
556 // Thumb1 instructions don't have explicit S bits. Rather, they
557 // implicitly set CPSR. Since it's not represented in the encoding, the
558 // auto-generated decoder won't inject the CPSR operand. We need to fix
559 // that as a post-pass.
560 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
561 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
562 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
563 MCInst::iterator I = MI.begin();
564 for (unsigned i = 0; i < NumOps; ++i, ++I) {
565 if (I == MI.end()) break;
566 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
567 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
568 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
576 // Most Thumb instructions don't have explicit predicates in the
577 // encoding, but rather get their predicates from IT context. We need
578 // to fix up the predicate operands using this context information as a
580 MCDisassembler::DecodeStatus
581 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
582 MCDisassembler::DecodeStatus S = Success;
584 // A few instructions actually have predicates encoded in them. Don't
585 // try to overwrite it if we're seeing one of those.
586 switch (MI.getOpcode()) {
597 // Some instructions (mostly conditional branches) are not
598 // allowed in IT blocks.
599 if (ITBlock.instrInITBlock())
608 // Some instructions (mostly unconditional branches) can
609 // only appears at the end of, or outside of, an IT.
610 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
617 // If we're in an IT block, base the predicate on that. Otherwise,
618 // assume a predicate of AL.
620 CC = ITBlock.getITCC();
623 if (ITBlock.instrInITBlock())
624 ITBlock.advanceITState();
626 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
627 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
628 MCInst::iterator I = MI.begin();
629 for (unsigned i = 0; i < NumOps; ++i, ++I) {
630 if (I == MI.end()) break;
631 if (OpInfo[i].isPredicate()) {
632 I = MI.insert(I, MCOperand::CreateImm(CC));
635 MI.insert(I, MCOperand::CreateReg(0));
637 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
642 I = MI.insert(I, MCOperand::CreateImm(CC));
645 MI.insert(I, MCOperand::CreateReg(0));
647 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
652 // Thumb VFP instructions are a special case. Because we share their
653 // encodings between ARM and Thumb modes, and they are predicable in ARM
654 // mode, the auto-generated decoder will give them an (incorrect)
655 // predicate operand. We need to rewrite these operands based on the IT
656 // context as a post-pass.
657 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
659 CC = ITBlock.getITCC();
660 if (ITBlock.instrInITBlock())
661 ITBlock.advanceITState();
663 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
664 MCInst::iterator I = MI.begin();
665 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
666 for (unsigned i = 0; i < NumOps; ++i, ++I) {
667 if (OpInfo[i].isPredicate() ) {
673 I->setReg(ARM::CPSR);
679 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
680 const MemoryObject &Region,
683 raw_ostream &cs) const {
688 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
689 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
691 // We want to read exactly 2 bytes of data.
692 if (Region.readBytes(Address, 2, bytes) == -1) {
694 return MCDisassembler::Fail;
697 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
698 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
700 if (result != MCDisassembler::Fail) {
702 Check(result, AddThumbPredicate(MI));
707 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
711 bool InITBlock = ITBlock.instrInITBlock();
712 Check(result, AddThumbPredicate(MI));
713 AddThumb1SBit(MI, InITBlock);
718 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
720 if (result != MCDisassembler::Fail) {
723 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
724 // the Thumb predicate.
725 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
726 result = MCDisassembler::SoftFail;
728 Check(result, AddThumbPredicate(MI));
730 // If we find an IT instruction, we need to parse its condition
731 // code and mask operands so that we can apply them correctly
732 // to the subsequent instructions.
733 if (MI.getOpcode() == ARM::t2IT) {
735 unsigned Firstcond = MI.getOperand(0).getImm();
736 unsigned Mask = MI.getOperand(1).getImm();
737 ITBlock.setITState(Firstcond, Mask);
743 // We want to read exactly 4 bytes of data.
744 if (Region.readBytes(Address, 4, bytes) == -1) {
746 return MCDisassembler::Fail;
749 uint32_t insn32 = (bytes[3] << 8) |
754 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
756 if (result != MCDisassembler::Fail) {
758 bool InITBlock = ITBlock.instrInITBlock();
759 Check(result, AddThumbPredicate(MI));
760 AddThumb1SBit(MI, InITBlock);
765 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
767 if (result != MCDisassembler::Fail) {
769 Check(result, AddThumbPredicate(MI));
773 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
775 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
776 if (result != MCDisassembler::Fail) {
778 UpdateThumbVFPPredicate(MI);
784 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
785 if (result != MCDisassembler::Fail) {
790 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
792 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
794 if (result != MCDisassembler::Fail) {
796 Check(result, AddThumbPredicate(MI));
801 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
803 uint32_t NEONLdStInsn = insn32;
804 NEONLdStInsn &= 0xF0FFFFFF;
805 NEONLdStInsn |= 0x04000000;
806 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
808 if (result != MCDisassembler::Fail) {
810 Check(result, AddThumbPredicate(MI));
815 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
817 uint32_t NEONDataInsn = insn32;
818 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
819 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
820 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
821 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
823 if (result != MCDisassembler::Fail) {
825 Check(result, AddThumbPredicate(MI));
830 uint32_t NEONCryptoInsn = insn32;
831 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
832 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
833 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
834 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
836 if (result != MCDisassembler::Fail) {
842 uint32_t NEONv8Insn = insn32;
843 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
844 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
846 if (result != MCDisassembler::Fail) {
854 return MCDisassembler::Fail;
858 extern "C" void LLVMInitializeARMDisassembler() {
859 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
860 createARMDisassembler);
861 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
862 createThumbDisassembler);
865 static const uint16_t GPRDecoderTable[] = {
866 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
867 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
868 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
869 ARM::R12, ARM::SP, ARM::LR, ARM::PC
872 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
873 uint64_t Address, const void *Decoder) {
875 return MCDisassembler::Fail;
877 unsigned Register = GPRDecoderTable[RegNo];
878 Inst.addOperand(MCOperand::CreateReg(Register));
879 return MCDisassembler::Success;
883 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
884 uint64_t Address, const void *Decoder) {
885 DecodeStatus S = MCDisassembler::Success;
888 S = MCDisassembler::SoftFail;
890 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
896 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
897 uint64_t Address, const void *Decoder) {
898 DecodeStatus S = MCDisassembler::Success;
902 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
903 return MCDisassembler::Success;
906 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
910 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
911 uint64_t Address, const void *Decoder) {
913 return MCDisassembler::Fail;
914 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
917 static const uint16_t GPRPairDecoderTable[] = {
918 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
919 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
922 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
923 uint64_t Address, const void *Decoder) {
924 DecodeStatus S = MCDisassembler::Success;
927 return MCDisassembler::Fail;
929 if ((RegNo & 1) || RegNo == 0xe)
930 S = MCDisassembler::SoftFail;
932 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
933 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
937 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
938 uint64_t Address, const void *Decoder) {
939 unsigned Register = 0;
960 return MCDisassembler::Fail;
963 Inst.addOperand(MCOperand::CreateReg(Register));
964 return MCDisassembler::Success;
967 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
968 uint64_t Address, const void *Decoder) {
969 DecodeStatus S = MCDisassembler::Success;
970 if (RegNo == 13 || RegNo == 15)
971 S = MCDisassembler::SoftFail;
972 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
976 static const uint16_t SPRDecoderTable[] = {
977 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
978 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
979 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
980 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
981 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
982 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
983 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
984 ARM::S28, ARM::S29, ARM::S30, ARM::S31
987 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
988 uint64_t Address, const void *Decoder) {
990 return MCDisassembler::Fail;
992 unsigned Register = SPRDecoderTable[RegNo];
993 Inst.addOperand(MCOperand::CreateReg(Register));
994 return MCDisassembler::Success;
997 static const uint16_t DPRDecoderTable[] = {
998 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
999 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1000 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1001 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1002 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1003 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1004 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1005 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1008 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1009 uint64_t Address, const void *Decoder) {
1011 return MCDisassembler::Fail;
1013 unsigned Register = DPRDecoderTable[RegNo];
1014 Inst.addOperand(MCOperand::CreateReg(Register));
1015 return MCDisassembler::Success;
1018 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1019 uint64_t Address, const void *Decoder) {
1021 return MCDisassembler::Fail;
1022 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1026 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1027 uint64_t Address, const void *Decoder) {
1029 return MCDisassembler::Fail;
1030 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1033 static const uint16_t QPRDecoderTable[] = {
1034 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1035 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1036 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1037 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1041 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1042 uint64_t Address, const void *Decoder) {
1043 if (RegNo > 31 || (RegNo & 1) != 0)
1044 return MCDisassembler::Fail;
1047 unsigned Register = QPRDecoderTable[RegNo];
1048 Inst.addOperand(MCOperand::CreateReg(Register));
1049 return MCDisassembler::Success;
1052 static const uint16_t DPairDecoderTable[] = {
1053 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1054 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1055 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1056 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1057 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1061 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1062 uint64_t Address, const void *Decoder) {
1064 return MCDisassembler::Fail;
1066 unsigned Register = DPairDecoderTable[RegNo];
1067 Inst.addOperand(MCOperand::CreateReg(Register));
1068 return MCDisassembler::Success;
1071 static const uint16_t DPairSpacedDecoderTable[] = {
1072 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1073 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1074 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1075 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1076 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1077 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1078 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1079 ARM::D28_D30, ARM::D29_D31
1082 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1085 const void *Decoder) {
1087 return MCDisassembler::Fail;
1089 unsigned Register = DPairSpacedDecoderTable[RegNo];
1090 Inst.addOperand(MCOperand::CreateReg(Register));
1091 return MCDisassembler::Success;
1094 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1095 uint64_t Address, const void *Decoder) {
1096 if (Val == 0xF) return MCDisassembler::Fail;
1097 // AL predicate is not allowed on Thumb1 branches.
1098 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1099 return MCDisassembler::Fail;
1100 Inst.addOperand(MCOperand::CreateImm(Val));
1101 if (Val == ARMCC::AL) {
1102 Inst.addOperand(MCOperand::CreateReg(0));
1104 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1105 return MCDisassembler::Success;
1108 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1109 uint64_t Address, const void *Decoder) {
1111 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1113 Inst.addOperand(MCOperand::CreateReg(0));
1114 return MCDisassembler::Success;
1117 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1118 uint64_t Address, const void *Decoder) {
1119 uint32_t imm = Val & 0xFF;
1120 uint32_t rot = (Val & 0xF00) >> 7;
1121 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1122 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1123 return MCDisassembler::Success;
1126 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1127 uint64_t Address, const void *Decoder) {
1128 DecodeStatus S = MCDisassembler::Success;
1130 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1131 unsigned type = fieldFromInstruction(Val, 5, 2);
1132 unsigned imm = fieldFromInstruction(Val, 7, 5);
1134 // Register-immediate
1135 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1136 return MCDisassembler::Fail;
1138 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1141 Shift = ARM_AM::lsl;
1144 Shift = ARM_AM::lsr;
1147 Shift = ARM_AM::asr;
1150 Shift = ARM_AM::ror;
1154 if (Shift == ARM_AM::ror && imm == 0)
1155 Shift = ARM_AM::rrx;
1157 unsigned Op = Shift | (imm << 3);
1158 Inst.addOperand(MCOperand::CreateImm(Op));
1163 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1164 uint64_t Address, const void *Decoder) {
1165 DecodeStatus S = MCDisassembler::Success;
1167 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1168 unsigned type = fieldFromInstruction(Val, 5, 2);
1169 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1171 // Register-register
1172 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1173 return MCDisassembler::Fail;
1174 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1175 return MCDisassembler::Fail;
1177 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1180 Shift = ARM_AM::lsl;
1183 Shift = ARM_AM::lsr;
1186 Shift = ARM_AM::asr;
1189 Shift = ARM_AM::ror;
1193 Inst.addOperand(MCOperand::CreateImm(Shift));
1198 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1199 uint64_t Address, const void *Decoder) {
1200 DecodeStatus S = MCDisassembler::Success;
1202 bool NeedDisjointWriteback = false;
1203 unsigned WritebackReg = 0;
1204 switch (Inst.getOpcode()) {
1207 case ARM::LDMIA_UPD:
1208 case ARM::LDMDB_UPD:
1209 case ARM::LDMIB_UPD:
1210 case ARM::LDMDA_UPD:
1211 case ARM::t2LDMIA_UPD:
1212 case ARM::t2LDMDB_UPD:
1213 case ARM::t2STMIA_UPD:
1214 case ARM::t2STMDB_UPD:
1215 NeedDisjointWriteback = true;
1216 WritebackReg = Inst.getOperand(0).getReg();
1220 // Empty register lists are not allowed.
1221 if (Val == 0) return MCDisassembler::Fail;
1222 for (unsigned i = 0; i < 16; ++i) {
1223 if (Val & (1 << i)) {
1224 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1225 return MCDisassembler::Fail;
1226 // Writeback not allowed if Rn is in the target list.
1227 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1228 Check(S, MCDisassembler::SoftFail);
1235 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1236 uint64_t Address, const void *Decoder) {
1237 DecodeStatus S = MCDisassembler::Success;
1239 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1240 unsigned regs = fieldFromInstruction(Val, 0, 8);
1242 // In case of unpredictable encoding, tweak the operands.
1243 if (regs == 0 || (Vd + regs) > 32) {
1244 regs = Vd + regs > 32 ? 32 - Vd : regs;
1245 regs = std::max( 1u, regs);
1246 S = MCDisassembler::SoftFail;
1249 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1250 return MCDisassembler::Fail;
1251 for (unsigned i = 0; i < (regs - 1); ++i) {
1252 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1253 return MCDisassembler::Fail;
1259 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1260 uint64_t Address, const void *Decoder) {
1261 DecodeStatus S = MCDisassembler::Success;
1263 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1264 unsigned regs = fieldFromInstruction(Val, 1, 7);
1266 // In case of unpredictable encoding, tweak the operands.
1267 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1268 regs = Vd + regs > 32 ? 32 - Vd : regs;
1269 regs = std::max( 1u, regs);
1270 regs = std::min(16u, regs);
1271 S = MCDisassembler::SoftFail;
1274 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1275 return MCDisassembler::Fail;
1276 for (unsigned i = 0; i < (regs - 1); ++i) {
1277 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1278 return MCDisassembler::Fail;
1284 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1285 uint64_t Address, const void *Decoder) {
1286 // This operand encodes a mask of contiguous zeros between a specified MSB
1287 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1288 // the mask of all bits LSB-and-lower, and then xor them to create
1289 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1290 // create the final mask.
1291 unsigned msb = fieldFromInstruction(Val, 5, 5);
1292 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1294 DecodeStatus S = MCDisassembler::Success;
1296 Check(S, MCDisassembler::SoftFail);
1297 // The check above will cause the warning for the "potentially undefined
1298 // instruction encoding" but we can't build a bad MCOperand value here
1299 // with a lsb > msb or else printing the MCInst will cause a crash.
1303 uint32_t msb_mask = 0xFFFFFFFF;
1304 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1305 uint32_t lsb_mask = (1U << lsb) - 1;
1307 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1311 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1312 uint64_t Address, const void *Decoder) {
1313 DecodeStatus S = MCDisassembler::Success;
1315 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1316 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1317 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1318 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1319 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1320 unsigned U = fieldFromInstruction(Insn, 23, 1);
1322 switch (Inst.getOpcode()) {
1323 case ARM::LDC_OFFSET:
1326 case ARM::LDC_OPTION:
1327 case ARM::LDCL_OFFSET:
1329 case ARM::LDCL_POST:
1330 case ARM::LDCL_OPTION:
1331 case ARM::STC_OFFSET:
1334 case ARM::STC_OPTION:
1335 case ARM::STCL_OFFSET:
1337 case ARM::STCL_POST:
1338 case ARM::STCL_OPTION:
1339 case ARM::t2LDC_OFFSET:
1340 case ARM::t2LDC_PRE:
1341 case ARM::t2LDC_POST:
1342 case ARM::t2LDC_OPTION:
1343 case ARM::t2LDCL_OFFSET:
1344 case ARM::t2LDCL_PRE:
1345 case ARM::t2LDCL_POST:
1346 case ARM::t2LDCL_OPTION:
1347 case ARM::t2STC_OFFSET:
1348 case ARM::t2STC_PRE:
1349 case ARM::t2STC_POST:
1350 case ARM::t2STC_OPTION:
1351 case ARM::t2STCL_OFFSET:
1352 case ARM::t2STCL_PRE:
1353 case ARM::t2STCL_POST:
1354 case ARM::t2STCL_OPTION:
1355 if (coproc == 0xA || coproc == 0xB)
1356 return MCDisassembler::Fail;
1362 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1364 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1365 return MCDisassembler::Fail;
1367 Inst.addOperand(MCOperand::CreateImm(coproc));
1368 Inst.addOperand(MCOperand::CreateImm(CRd));
1369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1370 return MCDisassembler::Fail;
1372 switch (Inst.getOpcode()) {
1373 case ARM::t2LDC2_OFFSET:
1374 case ARM::t2LDC2L_OFFSET:
1375 case ARM::t2LDC2_PRE:
1376 case ARM::t2LDC2L_PRE:
1377 case ARM::t2STC2_OFFSET:
1378 case ARM::t2STC2L_OFFSET:
1379 case ARM::t2STC2_PRE:
1380 case ARM::t2STC2L_PRE:
1381 case ARM::LDC2_OFFSET:
1382 case ARM::LDC2L_OFFSET:
1384 case ARM::LDC2L_PRE:
1385 case ARM::STC2_OFFSET:
1386 case ARM::STC2L_OFFSET:
1388 case ARM::STC2L_PRE:
1389 case ARM::t2LDC_OFFSET:
1390 case ARM::t2LDCL_OFFSET:
1391 case ARM::t2LDC_PRE:
1392 case ARM::t2LDCL_PRE:
1393 case ARM::t2STC_OFFSET:
1394 case ARM::t2STCL_OFFSET:
1395 case ARM::t2STC_PRE:
1396 case ARM::t2STCL_PRE:
1397 case ARM::LDC_OFFSET:
1398 case ARM::LDCL_OFFSET:
1401 case ARM::STC_OFFSET:
1402 case ARM::STCL_OFFSET:
1405 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1406 Inst.addOperand(MCOperand::CreateImm(imm));
1408 case ARM::t2LDC2_POST:
1409 case ARM::t2LDC2L_POST:
1410 case ARM::t2STC2_POST:
1411 case ARM::t2STC2L_POST:
1412 case ARM::LDC2_POST:
1413 case ARM::LDC2L_POST:
1414 case ARM::STC2_POST:
1415 case ARM::STC2L_POST:
1416 case ARM::t2LDC_POST:
1417 case ARM::t2LDCL_POST:
1418 case ARM::t2STC_POST:
1419 case ARM::t2STCL_POST:
1421 case ARM::LDCL_POST:
1423 case ARM::STCL_POST:
1427 // The 'option' variant doesn't encode 'U' in the immediate since
1428 // the immediate is unsigned [0,255].
1429 Inst.addOperand(MCOperand::CreateImm(imm));
1433 switch (Inst.getOpcode()) {
1434 case ARM::LDC_OFFSET:
1437 case ARM::LDC_OPTION:
1438 case ARM::LDCL_OFFSET:
1440 case ARM::LDCL_POST:
1441 case ARM::LDCL_OPTION:
1442 case ARM::STC_OFFSET:
1445 case ARM::STC_OPTION:
1446 case ARM::STCL_OFFSET:
1448 case ARM::STCL_POST:
1449 case ARM::STCL_OPTION:
1450 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1451 return MCDisassembler::Fail;
1461 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1462 uint64_t Address, const void *Decoder) {
1463 DecodeStatus S = MCDisassembler::Success;
1465 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1466 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1467 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1468 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1469 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1470 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1471 unsigned P = fieldFromInstruction(Insn, 24, 1);
1472 unsigned W = fieldFromInstruction(Insn, 21, 1);
1474 // On stores, the writeback operand precedes Rt.
1475 switch (Inst.getOpcode()) {
1476 case ARM::STR_POST_IMM:
1477 case ARM::STR_POST_REG:
1478 case ARM::STRB_POST_IMM:
1479 case ARM::STRB_POST_REG:
1480 case ARM::STRT_POST_REG:
1481 case ARM::STRT_POST_IMM:
1482 case ARM::STRBT_POST_REG:
1483 case ARM::STRBT_POST_IMM:
1484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1485 return MCDisassembler::Fail;
1491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1492 return MCDisassembler::Fail;
1494 // On loads, the writeback operand comes after Rt.
1495 switch (Inst.getOpcode()) {
1496 case ARM::LDR_POST_IMM:
1497 case ARM::LDR_POST_REG:
1498 case ARM::LDRB_POST_IMM:
1499 case ARM::LDRB_POST_REG:
1500 case ARM::LDRBT_POST_REG:
1501 case ARM::LDRBT_POST_IMM:
1502 case ARM::LDRT_POST_REG:
1503 case ARM::LDRT_POST_IMM:
1504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1505 return MCDisassembler::Fail;
1511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1512 return MCDisassembler::Fail;
1514 ARM_AM::AddrOpc Op = ARM_AM::add;
1515 if (!fieldFromInstruction(Insn, 23, 1))
1518 bool writeback = (P == 0) || (W == 1);
1519 unsigned idx_mode = 0;
1521 idx_mode = ARMII::IndexModePre;
1522 else if (!P && writeback)
1523 idx_mode = ARMII::IndexModePost;
1525 if (writeback && (Rn == 15 || Rn == Rt))
1526 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1529 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1530 return MCDisassembler::Fail;
1531 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1532 switch( fieldFromInstruction(Insn, 5, 2)) {
1546 return MCDisassembler::Fail;
1548 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1549 if (Opc == ARM_AM::ror && amt == 0)
1551 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1553 Inst.addOperand(MCOperand::CreateImm(imm));
1555 Inst.addOperand(MCOperand::CreateReg(0));
1556 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1557 Inst.addOperand(MCOperand::CreateImm(tmp));
1560 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1561 return MCDisassembler::Fail;
1566 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1567 uint64_t Address, const void *Decoder) {
1568 DecodeStatus S = MCDisassembler::Success;
1570 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1571 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1572 unsigned type = fieldFromInstruction(Val, 5, 2);
1573 unsigned imm = fieldFromInstruction(Val, 7, 5);
1574 unsigned U = fieldFromInstruction(Val, 12, 1);
1576 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1592 if (ShOp == ARM_AM::ror && imm == 0)
1595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1596 return MCDisassembler::Fail;
1597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1598 return MCDisassembler::Fail;
1601 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1603 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1604 Inst.addOperand(MCOperand::CreateImm(shift));
1610 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1611 uint64_t Address, const void *Decoder) {
1612 DecodeStatus S = MCDisassembler::Success;
1614 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1615 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1616 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1617 unsigned type = fieldFromInstruction(Insn, 22, 1);
1618 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1619 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1620 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1621 unsigned W = fieldFromInstruction(Insn, 21, 1);
1622 unsigned P = fieldFromInstruction(Insn, 24, 1);
1623 unsigned Rt2 = Rt + 1;
1625 bool writeback = (W == 1) | (P == 0);
1627 // For {LD,ST}RD, Rt must be even, else undefined.
1628 switch (Inst.getOpcode()) {
1631 case ARM::STRD_POST:
1634 case ARM::LDRD_POST:
1635 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1640 switch (Inst.getOpcode()) {
1643 case ARM::STRD_POST:
1644 if (P == 0 && W == 1)
1645 S = MCDisassembler::SoftFail;
1647 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1648 S = MCDisassembler::SoftFail;
1649 if (type && Rm == 15)
1650 S = MCDisassembler::SoftFail;
1652 S = MCDisassembler::SoftFail;
1653 if (!type && fieldFromInstruction(Insn, 8, 4))
1654 S = MCDisassembler::SoftFail;
1658 case ARM::STRH_POST:
1660 S = MCDisassembler::SoftFail;
1661 if (writeback && (Rn == 15 || Rn == Rt))
1662 S = MCDisassembler::SoftFail;
1663 if (!type && Rm == 15)
1664 S = MCDisassembler::SoftFail;
1668 case ARM::LDRD_POST:
1669 if (type && Rn == 15){
1671 S = MCDisassembler::SoftFail;
1674 if (P == 0 && W == 1)
1675 S = MCDisassembler::SoftFail;
1676 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1677 S = MCDisassembler::SoftFail;
1678 if (!type && writeback && Rn == 15)
1679 S = MCDisassembler::SoftFail;
1680 if (writeback && (Rn == Rt || Rn == Rt2))
1681 S = MCDisassembler::SoftFail;
1685 case ARM::LDRH_POST:
1686 if (type && Rn == 15){
1688 S = MCDisassembler::SoftFail;
1692 S = MCDisassembler::SoftFail;
1693 if (!type && Rm == 15)
1694 S = MCDisassembler::SoftFail;
1695 if (!type && writeback && (Rn == 15 || Rn == Rt))
1696 S = MCDisassembler::SoftFail;
1699 case ARM::LDRSH_PRE:
1700 case ARM::LDRSH_POST:
1702 case ARM::LDRSB_PRE:
1703 case ARM::LDRSB_POST:
1704 if (type && Rn == 15){
1706 S = MCDisassembler::SoftFail;
1709 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1710 S = MCDisassembler::SoftFail;
1711 if (!type && (Rt == 15 || Rm == 15))
1712 S = MCDisassembler::SoftFail;
1713 if (!type && writeback && (Rn == 15 || Rn == Rt))
1714 S = MCDisassembler::SoftFail;
1720 if (writeback) { // Writeback
1722 U |= ARMII::IndexModePre << 9;
1724 U |= ARMII::IndexModePost << 9;
1726 // On stores, the writeback operand precedes Rt.
1727 switch (Inst.getOpcode()) {
1730 case ARM::STRD_POST:
1733 case ARM::STRH_POST:
1734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1735 return MCDisassembler::Fail;
1742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1743 return MCDisassembler::Fail;
1744 switch (Inst.getOpcode()) {
1747 case ARM::STRD_POST:
1750 case ARM::LDRD_POST:
1751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1752 return MCDisassembler::Fail;
1759 // On loads, the writeback operand comes after Rt.
1760 switch (Inst.getOpcode()) {
1763 case ARM::LDRD_POST:
1766 case ARM::LDRH_POST:
1768 case ARM::LDRSH_PRE:
1769 case ARM::LDRSH_POST:
1771 case ARM::LDRSB_PRE:
1772 case ARM::LDRSB_POST:
1775 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1776 return MCDisassembler::Fail;
1783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1784 return MCDisassembler::Fail;
1787 Inst.addOperand(MCOperand::CreateReg(0));
1788 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1791 return MCDisassembler::Fail;
1792 Inst.addOperand(MCOperand::CreateImm(U));
1795 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1796 return MCDisassembler::Fail;
1801 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1802 uint64_t Address, const void *Decoder) {
1803 DecodeStatus S = MCDisassembler::Success;
1805 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1806 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1823 Inst.addOperand(MCOperand::CreateImm(mode));
1824 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1825 return MCDisassembler::Fail;
1830 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1831 uint64_t Address, const void *Decoder) {
1832 DecodeStatus S = MCDisassembler::Success;
1834 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1835 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1836 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1837 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1840 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1843 return MCDisassembler::Fail;
1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1845 return MCDisassembler::Fail;
1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1847 return MCDisassembler::Fail;
1848 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1849 return MCDisassembler::Fail;
1853 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1855 uint64_t Address, const void *Decoder) {
1856 DecodeStatus S = MCDisassembler::Success;
1858 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1859 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1860 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1863 // Ambiguous with RFE and SRS
1864 switch (Inst.getOpcode()) {
1866 Inst.setOpcode(ARM::RFEDA);
1868 case ARM::LDMDA_UPD:
1869 Inst.setOpcode(ARM::RFEDA_UPD);
1872 Inst.setOpcode(ARM::RFEDB);
1874 case ARM::LDMDB_UPD:
1875 Inst.setOpcode(ARM::RFEDB_UPD);
1878 Inst.setOpcode(ARM::RFEIA);
1880 case ARM::LDMIA_UPD:
1881 Inst.setOpcode(ARM::RFEIA_UPD);
1884 Inst.setOpcode(ARM::RFEIB);
1886 case ARM::LDMIB_UPD:
1887 Inst.setOpcode(ARM::RFEIB_UPD);
1890 Inst.setOpcode(ARM::SRSDA);
1892 case ARM::STMDA_UPD:
1893 Inst.setOpcode(ARM::SRSDA_UPD);
1896 Inst.setOpcode(ARM::SRSDB);
1898 case ARM::STMDB_UPD:
1899 Inst.setOpcode(ARM::SRSDB_UPD);
1902 Inst.setOpcode(ARM::SRSIA);
1904 case ARM::STMIA_UPD:
1905 Inst.setOpcode(ARM::SRSIA_UPD);
1908 Inst.setOpcode(ARM::SRSIB);
1910 case ARM::STMIB_UPD:
1911 Inst.setOpcode(ARM::SRSIB_UPD);
1914 return MCDisassembler::Fail;
1917 // For stores (which become SRS's, the only operand is the mode.
1918 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1919 // Check SRS encoding constraints
1920 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1921 fieldFromInstruction(Insn, 20, 1) == 0))
1922 return MCDisassembler::Fail;
1925 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1929 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1933 return MCDisassembler::Fail;
1934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1935 return MCDisassembler::Fail; // Tied
1936 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1937 return MCDisassembler::Fail;
1938 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1939 return MCDisassembler::Fail;
1944 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1945 uint64_t Address, const void *Decoder) {
1946 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1947 unsigned M = fieldFromInstruction(Insn, 17, 1);
1948 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1949 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1951 DecodeStatus S = MCDisassembler::Success;
1953 // This decoder is called from multiple location that do not check
1954 // the full encoding is valid before they do.
1955 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1956 fieldFromInstruction(Insn, 16, 1) != 0 ||
1957 fieldFromInstruction(Insn, 20, 8) != 0x10)
1958 return MCDisassembler::Fail;
1960 // imod == '01' --> UNPREDICTABLE
1961 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1962 // return failure here. The '01' imod value is unprintable, so there's
1963 // nothing useful we could do even if we returned UNPREDICTABLE.
1965 if (imod == 1) return MCDisassembler::Fail;
1968 Inst.setOpcode(ARM::CPS3p);
1969 Inst.addOperand(MCOperand::CreateImm(imod));
1970 Inst.addOperand(MCOperand::CreateImm(iflags));
1971 Inst.addOperand(MCOperand::CreateImm(mode));
1972 } else if (imod && !M) {
1973 Inst.setOpcode(ARM::CPS2p);
1974 Inst.addOperand(MCOperand::CreateImm(imod));
1975 Inst.addOperand(MCOperand::CreateImm(iflags));
1976 if (mode) S = MCDisassembler::SoftFail;
1977 } else if (!imod && M) {
1978 Inst.setOpcode(ARM::CPS1p);
1979 Inst.addOperand(MCOperand::CreateImm(mode));
1980 if (iflags) S = MCDisassembler::SoftFail;
1982 // imod == '00' && M == '0' --> UNPREDICTABLE
1983 Inst.setOpcode(ARM::CPS1p);
1984 Inst.addOperand(MCOperand::CreateImm(mode));
1985 S = MCDisassembler::SoftFail;
1991 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1992 uint64_t Address, const void *Decoder) {
1993 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1994 unsigned M = fieldFromInstruction(Insn, 8, 1);
1995 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1996 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1998 DecodeStatus S = MCDisassembler::Success;
2000 // imod == '01' --> UNPREDICTABLE
2001 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2002 // return failure here. The '01' imod value is unprintable, so there's
2003 // nothing useful we could do even if we returned UNPREDICTABLE.
2005 if (imod == 1) return MCDisassembler::Fail;
2008 Inst.setOpcode(ARM::t2CPS3p);
2009 Inst.addOperand(MCOperand::CreateImm(imod));
2010 Inst.addOperand(MCOperand::CreateImm(iflags));
2011 Inst.addOperand(MCOperand::CreateImm(mode));
2012 } else if (imod && !M) {
2013 Inst.setOpcode(ARM::t2CPS2p);
2014 Inst.addOperand(MCOperand::CreateImm(imod));
2015 Inst.addOperand(MCOperand::CreateImm(iflags));
2016 if (mode) S = MCDisassembler::SoftFail;
2017 } else if (!imod && M) {
2018 Inst.setOpcode(ARM::t2CPS1p);
2019 Inst.addOperand(MCOperand::CreateImm(mode));
2020 if (iflags) S = MCDisassembler::SoftFail;
2022 // imod == '00' && M == '0' --> this is a HINT instruction
2023 int imm = fieldFromInstruction(Insn, 0, 8);
2024 // HINT are defined only for immediate in [0..4]
2025 if(imm > 4) return MCDisassembler::Fail;
2026 Inst.setOpcode(ARM::t2HINT);
2027 Inst.addOperand(MCOperand::CreateImm(imm));
2033 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2034 uint64_t Address, const void *Decoder) {
2035 DecodeStatus S = MCDisassembler::Success;
2037 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2040 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2041 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2042 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2043 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2045 if (Inst.getOpcode() == ARM::t2MOVTi16)
2046 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2047 return MCDisassembler::Fail;
2048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2049 return MCDisassembler::Fail;
2051 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2052 Inst.addOperand(MCOperand::CreateImm(imm));
2057 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2058 uint64_t Address, const void *Decoder) {
2059 DecodeStatus S = MCDisassembler::Success;
2061 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2062 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2065 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2066 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2068 if (Inst.getOpcode() == ARM::MOVTi16)
2069 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2070 return MCDisassembler::Fail;
2072 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2073 return MCDisassembler::Fail;
2075 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2076 Inst.addOperand(MCOperand::CreateImm(imm));
2078 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2079 return MCDisassembler::Fail;
2084 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2085 uint64_t Address, const void *Decoder) {
2086 DecodeStatus S = MCDisassembler::Success;
2088 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2089 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2090 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2091 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2092 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2095 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2097 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2098 return MCDisassembler::Fail;
2099 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2100 return MCDisassembler::Fail;
2101 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2102 return MCDisassembler::Fail;
2103 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2104 return MCDisassembler::Fail;
2106 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2107 return MCDisassembler::Fail;
2112 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2113 uint64_t Address, const void *Decoder) {
2114 DecodeStatus S = MCDisassembler::Success;
2116 unsigned add = fieldFromInstruction(Val, 12, 1);
2117 unsigned imm = fieldFromInstruction(Val, 0, 12);
2118 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2121 return MCDisassembler::Fail;
2123 if (!add) imm *= -1;
2124 if (imm == 0 && !add) imm = INT32_MIN;
2125 Inst.addOperand(MCOperand::CreateImm(imm));
2127 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2132 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2133 uint64_t Address, const void *Decoder) {
2134 DecodeStatus S = MCDisassembler::Success;
2136 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2137 unsigned U = fieldFromInstruction(Val, 8, 1);
2138 unsigned imm = fieldFromInstruction(Val, 0, 8);
2140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2141 return MCDisassembler::Fail;
2144 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2146 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2151 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2152 uint64_t Address, const void *Decoder) {
2153 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2157 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2158 uint64_t Address, const void *Decoder) {
2159 DecodeStatus Status = MCDisassembler::Success;
2161 // Note the J1 and J2 values are from the encoded instruction. So here
2162 // change them to I1 and I2 values via as documented:
2163 // I1 = NOT(J1 EOR S);
2164 // I2 = NOT(J2 EOR S);
2165 // and build the imm32 with one trailing zero as documented:
2166 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2167 unsigned S = fieldFromInstruction(Insn, 26, 1);
2168 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2169 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2170 unsigned I1 = !(J1 ^ S);
2171 unsigned I2 = !(J2 ^ S);
2172 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2173 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2174 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2175 int imm32 = SignExtend32<25>(tmp << 1);
2176 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2177 true, 4, Inst, Decoder))
2178 Inst.addOperand(MCOperand::CreateImm(imm32));
2184 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2185 uint64_t Address, const void *Decoder) {
2186 DecodeStatus S = MCDisassembler::Success;
2188 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2189 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2192 Inst.setOpcode(ARM::BLXi);
2193 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2194 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2195 true, 4, Inst, Decoder))
2196 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2200 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2201 true, 4, Inst, Decoder))
2202 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2203 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2204 return MCDisassembler::Fail;
2210 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2211 uint64_t Address, const void *Decoder) {
2212 DecodeStatus S = MCDisassembler::Success;
2214 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2215 unsigned align = fieldFromInstruction(Val, 4, 2);
2217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2218 return MCDisassembler::Fail;
2220 Inst.addOperand(MCOperand::CreateImm(0));
2222 Inst.addOperand(MCOperand::CreateImm(4 << align));
2227 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2228 uint64_t Address, const void *Decoder) {
2229 DecodeStatus S = MCDisassembler::Success;
2231 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2232 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2233 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2234 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2235 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2236 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2238 // First output register
2239 switch (Inst.getOpcode()) {
2240 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2241 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2242 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2243 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2244 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2245 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2246 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2247 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2248 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2249 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2250 return MCDisassembler::Fail;
2255 case ARM::VLD2b16wb_fixed:
2256 case ARM::VLD2b16wb_register:
2257 case ARM::VLD2b32wb_fixed:
2258 case ARM::VLD2b32wb_register:
2259 case ARM::VLD2b8wb_fixed:
2260 case ARM::VLD2b8wb_register:
2261 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2262 return MCDisassembler::Fail;
2265 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2266 return MCDisassembler::Fail;
2269 // Second output register
2270 switch (Inst.getOpcode()) {
2274 case ARM::VLD3d8_UPD:
2275 case ARM::VLD3d16_UPD:
2276 case ARM::VLD3d32_UPD:
2280 case ARM::VLD4d8_UPD:
2281 case ARM::VLD4d16_UPD:
2282 case ARM::VLD4d32_UPD:
2283 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2284 return MCDisassembler::Fail;
2289 case ARM::VLD3q8_UPD:
2290 case ARM::VLD3q16_UPD:
2291 case ARM::VLD3q32_UPD:
2295 case ARM::VLD4q8_UPD:
2296 case ARM::VLD4q16_UPD:
2297 case ARM::VLD4q32_UPD:
2298 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2299 return MCDisassembler::Fail;
2304 // Third output register
2305 switch(Inst.getOpcode()) {
2309 case ARM::VLD3d8_UPD:
2310 case ARM::VLD3d16_UPD:
2311 case ARM::VLD3d32_UPD:
2315 case ARM::VLD4d8_UPD:
2316 case ARM::VLD4d16_UPD:
2317 case ARM::VLD4d32_UPD:
2318 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2319 return MCDisassembler::Fail;
2324 case ARM::VLD3q8_UPD:
2325 case ARM::VLD3q16_UPD:
2326 case ARM::VLD3q32_UPD:
2330 case ARM::VLD4q8_UPD:
2331 case ARM::VLD4q16_UPD:
2332 case ARM::VLD4q32_UPD:
2333 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2334 return MCDisassembler::Fail;
2340 // Fourth output register
2341 switch (Inst.getOpcode()) {
2345 case ARM::VLD4d8_UPD:
2346 case ARM::VLD4d16_UPD:
2347 case ARM::VLD4d32_UPD:
2348 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2349 return MCDisassembler::Fail;
2354 case ARM::VLD4q8_UPD:
2355 case ARM::VLD4q16_UPD:
2356 case ARM::VLD4q32_UPD:
2357 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2358 return MCDisassembler::Fail;
2364 // Writeback operand
2365 switch (Inst.getOpcode()) {
2366 case ARM::VLD1d8wb_fixed:
2367 case ARM::VLD1d16wb_fixed:
2368 case ARM::VLD1d32wb_fixed:
2369 case ARM::VLD1d64wb_fixed:
2370 case ARM::VLD1d8wb_register:
2371 case ARM::VLD1d16wb_register:
2372 case ARM::VLD1d32wb_register:
2373 case ARM::VLD1d64wb_register:
2374 case ARM::VLD1q8wb_fixed:
2375 case ARM::VLD1q16wb_fixed:
2376 case ARM::VLD1q32wb_fixed:
2377 case ARM::VLD1q64wb_fixed:
2378 case ARM::VLD1q8wb_register:
2379 case ARM::VLD1q16wb_register:
2380 case ARM::VLD1q32wb_register:
2381 case ARM::VLD1q64wb_register:
2382 case ARM::VLD1d8Twb_fixed:
2383 case ARM::VLD1d8Twb_register:
2384 case ARM::VLD1d16Twb_fixed:
2385 case ARM::VLD1d16Twb_register:
2386 case ARM::VLD1d32Twb_fixed:
2387 case ARM::VLD1d32Twb_register:
2388 case ARM::VLD1d64Twb_fixed:
2389 case ARM::VLD1d64Twb_register:
2390 case ARM::VLD1d8Qwb_fixed:
2391 case ARM::VLD1d8Qwb_register:
2392 case ARM::VLD1d16Qwb_fixed:
2393 case ARM::VLD1d16Qwb_register:
2394 case ARM::VLD1d32Qwb_fixed:
2395 case ARM::VLD1d32Qwb_register:
2396 case ARM::VLD1d64Qwb_fixed:
2397 case ARM::VLD1d64Qwb_register:
2398 case ARM::VLD2d8wb_fixed:
2399 case ARM::VLD2d16wb_fixed:
2400 case ARM::VLD2d32wb_fixed:
2401 case ARM::VLD2q8wb_fixed:
2402 case ARM::VLD2q16wb_fixed:
2403 case ARM::VLD2q32wb_fixed:
2404 case ARM::VLD2d8wb_register:
2405 case ARM::VLD2d16wb_register:
2406 case ARM::VLD2d32wb_register:
2407 case ARM::VLD2q8wb_register:
2408 case ARM::VLD2q16wb_register:
2409 case ARM::VLD2q32wb_register:
2410 case ARM::VLD2b8wb_fixed:
2411 case ARM::VLD2b16wb_fixed:
2412 case ARM::VLD2b32wb_fixed:
2413 case ARM::VLD2b8wb_register:
2414 case ARM::VLD2b16wb_register:
2415 case ARM::VLD2b32wb_register:
2416 Inst.addOperand(MCOperand::CreateImm(0));
2418 case ARM::VLD3d8_UPD:
2419 case ARM::VLD3d16_UPD:
2420 case ARM::VLD3d32_UPD:
2421 case ARM::VLD3q8_UPD:
2422 case ARM::VLD3q16_UPD:
2423 case ARM::VLD3q32_UPD:
2424 case ARM::VLD4d8_UPD:
2425 case ARM::VLD4d16_UPD:
2426 case ARM::VLD4d32_UPD:
2427 case ARM::VLD4q8_UPD:
2428 case ARM::VLD4q16_UPD:
2429 case ARM::VLD4q32_UPD:
2430 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2431 return MCDisassembler::Fail;
2437 // AddrMode6 Base (register+alignment)
2438 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2439 return MCDisassembler::Fail;
2441 // AddrMode6 Offset (register)
2442 switch (Inst.getOpcode()) {
2444 // The below have been updated to have explicit am6offset split
2445 // between fixed and register offset. For those instructions not
2446 // yet updated, we need to add an additional reg0 operand for the
2449 // The fixed offset encodes as Rm == 0xd, so we check for that.
2451 Inst.addOperand(MCOperand::CreateReg(0));
2454 // Fall through to handle the register offset variant.
2455 case ARM::VLD1d8wb_fixed:
2456 case ARM::VLD1d16wb_fixed:
2457 case ARM::VLD1d32wb_fixed:
2458 case ARM::VLD1d64wb_fixed:
2459 case ARM::VLD1d8Twb_fixed:
2460 case ARM::VLD1d16Twb_fixed:
2461 case ARM::VLD1d32Twb_fixed:
2462 case ARM::VLD1d64Twb_fixed:
2463 case ARM::VLD1d8Qwb_fixed:
2464 case ARM::VLD1d16Qwb_fixed:
2465 case ARM::VLD1d32Qwb_fixed:
2466 case ARM::VLD1d64Qwb_fixed:
2467 case ARM::VLD1d8wb_register:
2468 case ARM::VLD1d16wb_register:
2469 case ARM::VLD1d32wb_register:
2470 case ARM::VLD1d64wb_register:
2471 case ARM::VLD1q8wb_fixed:
2472 case ARM::VLD1q16wb_fixed:
2473 case ARM::VLD1q32wb_fixed:
2474 case ARM::VLD1q64wb_fixed:
2475 case ARM::VLD1q8wb_register:
2476 case ARM::VLD1q16wb_register:
2477 case ARM::VLD1q32wb_register:
2478 case ARM::VLD1q64wb_register:
2479 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2480 // variant encodes Rm == 0xf. Anything else is a register offset post-
2481 // increment and we need to add the register operand to the instruction.
2482 if (Rm != 0xD && Rm != 0xF &&
2483 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2484 return MCDisassembler::Fail;
2486 case ARM::VLD2d8wb_fixed:
2487 case ARM::VLD2d16wb_fixed:
2488 case ARM::VLD2d32wb_fixed:
2489 case ARM::VLD2b8wb_fixed:
2490 case ARM::VLD2b16wb_fixed:
2491 case ARM::VLD2b32wb_fixed:
2492 case ARM::VLD2q8wb_fixed:
2493 case ARM::VLD2q16wb_fixed:
2494 case ARM::VLD2q32wb_fixed:
2501 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2502 uint64_t Address, const void *Decoder) {
2503 unsigned type = fieldFromInstruction(Insn, 8, 4);
2504 unsigned align = fieldFromInstruction(Insn, 4, 2);
2505 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2506 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2507 if (type == 10 && align == 3) return MCDisassembler::Fail;
2509 unsigned load = fieldFromInstruction(Insn, 21, 1);
2510 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2511 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2514 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2515 uint64_t Address, const void *Decoder) {
2516 unsigned size = fieldFromInstruction(Insn, 6, 2);
2517 if (size == 3) return MCDisassembler::Fail;
2519 unsigned type = fieldFromInstruction(Insn, 8, 4);
2520 unsigned align = fieldFromInstruction(Insn, 4, 2);
2521 if (type == 8 && align == 3) return MCDisassembler::Fail;
2522 if (type == 9 && align == 3) return MCDisassembler::Fail;
2524 unsigned load = fieldFromInstruction(Insn, 21, 1);
2525 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2526 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2529 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2530 uint64_t Address, const void *Decoder) {
2531 unsigned size = fieldFromInstruction(Insn, 6, 2);
2532 if (size == 3) return MCDisassembler::Fail;
2534 unsigned align = fieldFromInstruction(Insn, 4, 2);
2535 if (align & 2) return MCDisassembler::Fail;
2537 unsigned load = fieldFromInstruction(Insn, 21, 1);
2538 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2539 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2542 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2543 uint64_t Address, const void *Decoder) {
2544 unsigned size = fieldFromInstruction(Insn, 6, 2);
2545 if (size == 3) return MCDisassembler::Fail;
2547 unsigned load = fieldFromInstruction(Insn, 21, 1);
2548 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2549 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2552 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2553 uint64_t Address, const void *Decoder) {
2554 DecodeStatus S = MCDisassembler::Success;
2556 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2557 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2558 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2559 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2560 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2561 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2563 // Writeback Operand
2564 switch (Inst.getOpcode()) {
2565 case ARM::VST1d8wb_fixed:
2566 case ARM::VST1d16wb_fixed:
2567 case ARM::VST1d32wb_fixed:
2568 case ARM::VST1d64wb_fixed:
2569 case ARM::VST1d8wb_register:
2570 case ARM::VST1d16wb_register:
2571 case ARM::VST1d32wb_register:
2572 case ARM::VST1d64wb_register:
2573 case ARM::VST1q8wb_fixed:
2574 case ARM::VST1q16wb_fixed:
2575 case ARM::VST1q32wb_fixed:
2576 case ARM::VST1q64wb_fixed:
2577 case ARM::VST1q8wb_register:
2578 case ARM::VST1q16wb_register:
2579 case ARM::VST1q32wb_register:
2580 case ARM::VST1q64wb_register:
2581 case ARM::VST1d8Twb_fixed:
2582 case ARM::VST1d16Twb_fixed:
2583 case ARM::VST1d32Twb_fixed:
2584 case ARM::VST1d64Twb_fixed:
2585 case ARM::VST1d8Twb_register:
2586 case ARM::VST1d16Twb_register:
2587 case ARM::VST1d32Twb_register:
2588 case ARM::VST1d64Twb_register:
2589 case ARM::VST1d8Qwb_fixed:
2590 case ARM::VST1d16Qwb_fixed:
2591 case ARM::VST1d32Qwb_fixed:
2592 case ARM::VST1d64Qwb_fixed:
2593 case ARM::VST1d8Qwb_register:
2594 case ARM::VST1d16Qwb_register:
2595 case ARM::VST1d32Qwb_register:
2596 case ARM::VST1d64Qwb_register:
2597 case ARM::VST2d8wb_fixed:
2598 case ARM::VST2d16wb_fixed:
2599 case ARM::VST2d32wb_fixed:
2600 case ARM::VST2d8wb_register:
2601 case ARM::VST2d16wb_register:
2602 case ARM::VST2d32wb_register:
2603 case ARM::VST2q8wb_fixed:
2604 case ARM::VST2q16wb_fixed:
2605 case ARM::VST2q32wb_fixed:
2606 case ARM::VST2q8wb_register:
2607 case ARM::VST2q16wb_register:
2608 case ARM::VST2q32wb_register:
2609 case ARM::VST2b8wb_fixed:
2610 case ARM::VST2b16wb_fixed:
2611 case ARM::VST2b32wb_fixed:
2612 case ARM::VST2b8wb_register:
2613 case ARM::VST2b16wb_register:
2614 case ARM::VST2b32wb_register:
2616 return MCDisassembler::Fail;
2617 Inst.addOperand(MCOperand::CreateImm(0));
2619 case ARM::VST3d8_UPD:
2620 case ARM::VST3d16_UPD:
2621 case ARM::VST3d32_UPD:
2622 case ARM::VST3q8_UPD:
2623 case ARM::VST3q16_UPD:
2624 case ARM::VST3q32_UPD:
2625 case ARM::VST4d8_UPD:
2626 case ARM::VST4d16_UPD:
2627 case ARM::VST4d32_UPD:
2628 case ARM::VST4q8_UPD:
2629 case ARM::VST4q16_UPD:
2630 case ARM::VST4q32_UPD:
2631 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2632 return MCDisassembler::Fail;
2638 // AddrMode6 Base (register+alignment)
2639 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2640 return MCDisassembler::Fail;
2642 // AddrMode6 Offset (register)
2643 switch (Inst.getOpcode()) {
2646 Inst.addOperand(MCOperand::CreateReg(0));
2647 else if (Rm != 0xF) {
2648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2649 return MCDisassembler::Fail;
2652 case ARM::VST1d8wb_fixed:
2653 case ARM::VST1d16wb_fixed:
2654 case ARM::VST1d32wb_fixed:
2655 case ARM::VST1d64wb_fixed:
2656 case ARM::VST1q8wb_fixed:
2657 case ARM::VST1q16wb_fixed:
2658 case ARM::VST1q32wb_fixed:
2659 case ARM::VST1q64wb_fixed:
2660 case ARM::VST1d8Twb_fixed:
2661 case ARM::VST1d16Twb_fixed:
2662 case ARM::VST1d32Twb_fixed:
2663 case ARM::VST1d64Twb_fixed:
2664 case ARM::VST1d8Qwb_fixed:
2665 case ARM::VST1d16Qwb_fixed:
2666 case ARM::VST1d32Qwb_fixed:
2667 case ARM::VST1d64Qwb_fixed:
2668 case ARM::VST2d8wb_fixed:
2669 case ARM::VST2d16wb_fixed:
2670 case ARM::VST2d32wb_fixed:
2671 case ARM::VST2q8wb_fixed:
2672 case ARM::VST2q16wb_fixed:
2673 case ARM::VST2q32wb_fixed:
2674 case ARM::VST2b8wb_fixed:
2675 case ARM::VST2b16wb_fixed:
2676 case ARM::VST2b32wb_fixed:
2681 // First input register
2682 switch (Inst.getOpcode()) {
2687 case ARM::VST1q16wb_fixed:
2688 case ARM::VST1q16wb_register:
2689 case ARM::VST1q32wb_fixed:
2690 case ARM::VST1q32wb_register:
2691 case ARM::VST1q64wb_fixed:
2692 case ARM::VST1q64wb_register:
2693 case ARM::VST1q8wb_fixed:
2694 case ARM::VST1q8wb_register:
2698 case ARM::VST2d16wb_fixed:
2699 case ARM::VST2d16wb_register:
2700 case ARM::VST2d32wb_fixed:
2701 case ARM::VST2d32wb_register:
2702 case ARM::VST2d8wb_fixed:
2703 case ARM::VST2d8wb_register:
2704 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2705 return MCDisassembler::Fail;
2710 case ARM::VST2b16wb_fixed:
2711 case ARM::VST2b16wb_register:
2712 case ARM::VST2b32wb_fixed:
2713 case ARM::VST2b32wb_register:
2714 case ARM::VST2b8wb_fixed:
2715 case ARM::VST2b8wb_register:
2716 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2717 return MCDisassembler::Fail;
2720 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2721 return MCDisassembler::Fail;
2724 // Second input register
2725 switch (Inst.getOpcode()) {
2729 case ARM::VST3d8_UPD:
2730 case ARM::VST3d16_UPD:
2731 case ARM::VST3d32_UPD:
2735 case ARM::VST4d8_UPD:
2736 case ARM::VST4d16_UPD:
2737 case ARM::VST4d32_UPD:
2738 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2739 return MCDisassembler::Fail;
2744 case ARM::VST3q8_UPD:
2745 case ARM::VST3q16_UPD:
2746 case ARM::VST3q32_UPD:
2750 case ARM::VST4q8_UPD:
2751 case ARM::VST4q16_UPD:
2752 case ARM::VST4q32_UPD:
2753 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2754 return MCDisassembler::Fail;
2760 // Third input register
2761 switch (Inst.getOpcode()) {
2765 case ARM::VST3d8_UPD:
2766 case ARM::VST3d16_UPD:
2767 case ARM::VST3d32_UPD:
2771 case ARM::VST4d8_UPD:
2772 case ARM::VST4d16_UPD:
2773 case ARM::VST4d32_UPD:
2774 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2775 return MCDisassembler::Fail;
2780 case ARM::VST3q8_UPD:
2781 case ARM::VST3q16_UPD:
2782 case ARM::VST3q32_UPD:
2786 case ARM::VST4q8_UPD:
2787 case ARM::VST4q16_UPD:
2788 case ARM::VST4q32_UPD:
2789 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2790 return MCDisassembler::Fail;
2796 // Fourth input register
2797 switch (Inst.getOpcode()) {
2801 case ARM::VST4d8_UPD:
2802 case ARM::VST4d16_UPD:
2803 case ARM::VST4d32_UPD:
2804 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2805 return MCDisassembler::Fail;
2810 case ARM::VST4q8_UPD:
2811 case ARM::VST4q16_UPD:
2812 case ARM::VST4q32_UPD:
2813 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2814 return MCDisassembler::Fail;
2823 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2824 uint64_t Address, const void *Decoder) {
2825 DecodeStatus S = MCDisassembler::Success;
2827 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2828 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2829 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2830 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2831 unsigned align = fieldFromInstruction(Insn, 4, 1);
2832 unsigned size = fieldFromInstruction(Insn, 6, 2);
2834 if (size == 0 && align == 1)
2835 return MCDisassembler::Fail;
2836 align *= (1 << size);
2838 switch (Inst.getOpcode()) {
2839 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2840 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2841 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2842 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2843 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2844 return MCDisassembler::Fail;
2847 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2848 return MCDisassembler::Fail;
2852 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2853 return MCDisassembler::Fail;
2856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2857 return MCDisassembler::Fail;
2858 Inst.addOperand(MCOperand::CreateImm(align));
2860 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2861 // variant encodes Rm == 0xf. Anything else is a register offset post-
2862 // increment and we need to add the register operand to the instruction.
2863 if (Rm != 0xD && Rm != 0xF &&
2864 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2865 return MCDisassembler::Fail;
2870 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2871 uint64_t Address, const void *Decoder) {
2872 DecodeStatus S = MCDisassembler::Success;
2874 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2875 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2876 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2877 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2878 unsigned align = fieldFromInstruction(Insn, 4, 1);
2879 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2882 switch (Inst.getOpcode()) {
2883 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2884 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2885 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2886 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2887 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2888 return MCDisassembler::Fail;
2890 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2891 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2892 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2893 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2894 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2895 return MCDisassembler::Fail;
2898 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2899 return MCDisassembler::Fail;
2904 Inst.addOperand(MCOperand::CreateImm(0));
2906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2907 return MCDisassembler::Fail;
2908 Inst.addOperand(MCOperand::CreateImm(align));
2910 if (Rm != 0xD && Rm != 0xF) {
2911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2912 return MCDisassembler::Fail;
2918 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2919 uint64_t Address, const void *Decoder) {
2920 DecodeStatus S = MCDisassembler::Success;
2922 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2923 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2924 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2925 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2926 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2928 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2929 return MCDisassembler::Fail;
2930 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2931 return MCDisassembler::Fail;
2932 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2933 return MCDisassembler::Fail;
2935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2936 return MCDisassembler::Fail;
2939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2940 return MCDisassembler::Fail;
2941 Inst.addOperand(MCOperand::CreateImm(0));
2944 Inst.addOperand(MCOperand::CreateReg(0));
2945 else if (Rm != 0xF) {
2946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2947 return MCDisassembler::Fail;
2953 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2954 uint64_t Address, const void *Decoder) {
2955 DecodeStatus S = MCDisassembler::Success;
2957 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2958 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2959 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2960 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2961 unsigned size = fieldFromInstruction(Insn, 6, 2);
2962 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2963 unsigned align = fieldFromInstruction(Insn, 4, 1);
2967 return MCDisassembler::Fail;
2980 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2981 return MCDisassembler::Fail;
2982 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2983 return MCDisassembler::Fail;
2984 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2985 return MCDisassembler::Fail;
2986 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2987 return MCDisassembler::Fail;
2989 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2990 return MCDisassembler::Fail;
2993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2994 return MCDisassembler::Fail;
2995 Inst.addOperand(MCOperand::CreateImm(align));
2998 Inst.addOperand(MCOperand::CreateReg(0));
2999 else if (Rm != 0xF) {
3000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3001 return MCDisassembler::Fail;
3008 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3009 uint64_t Address, const void *Decoder) {
3010 DecodeStatus S = MCDisassembler::Success;
3012 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3013 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3014 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3015 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3016 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3017 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3018 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3019 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3022 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3023 return MCDisassembler::Fail;
3025 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3026 return MCDisassembler::Fail;
3029 Inst.addOperand(MCOperand::CreateImm(imm));
3031 switch (Inst.getOpcode()) {
3032 case ARM::VORRiv4i16:
3033 case ARM::VORRiv2i32:
3034 case ARM::VBICiv4i16:
3035 case ARM::VBICiv2i32:
3036 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3037 return MCDisassembler::Fail;
3039 case ARM::VORRiv8i16:
3040 case ARM::VORRiv4i32:
3041 case ARM::VBICiv8i16:
3042 case ARM::VBICiv4i32:
3043 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3044 return MCDisassembler::Fail;
3053 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3054 uint64_t Address, const void *Decoder) {
3055 DecodeStatus S = MCDisassembler::Success;
3057 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3058 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3059 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3060 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3061 unsigned size = fieldFromInstruction(Insn, 18, 2);
3063 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3064 return MCDisassembler::Fail;
3065 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3066 return MCDisassembler::Fail;
3067 Inst.addOperand(MCOperand::CreateImm(8 << size));
3072 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3073 uint64_t Address, const void *Decoder) {
3074 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3075 return MCDisassembler::Success;
3078 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3079 uint64_t Address, const void *Decoder) {
3080 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3081 return MCDisassembler::Success;
3084 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3085 uint64_t Address, const void *Decoder) {
3086 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3087 return MCDisassembler::Success;
3090 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3091 uint64_t Address, const void *Decoder) {
3092 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3093 return MCDisassembler::Success;
3096 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3097 uint64_t Address, const void *Decoder) {
3098 DecodeStatus S = MCDisassembler::Success;
3100 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3101 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3102 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3103 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3104 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3105 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3106 unsigned op = fieldFromInstruction(Insn, 6, 1);
3108 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3109 return MCDisassembler::Fail;
3111 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3112 return MCDisassembler::Fail; // Writeback
3115 switch (Inst.getOpcode()) {
3118 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3119 return MCDisassembler::Fail;
3122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3123 return MCDisassembler::Fail;
3126 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3127 return MCDisassembler::Fail;
3132 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3133 uint64_t Address, const void *Decoder) {
3134 DecodeStatus S = MCDisassembler::Success;
3136 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3137 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3139 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3140 return MCDisassembler::Fail;
3142 switch(Inst.getOpcode()) {
3144 return MCDisassembler::Fail;
3146 break; // tADR does not explicitly represent the PC as an operand.
3148 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3152 Inst.addOperand(MCOperand::CreateImm(imm));
3156 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3157 uint64_t Address, const void *Decoder) {
3158 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3159 true, 2, Inst, Decoder))
3160 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3161 return MCDisassembler::Success;
3164 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3165 uint64_t Address, const void *Decoder) {
3166 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3167 true, 4, Inst, Decoder))
3168 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3169 return MCDisassembler::Success;
3172 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3173 uint64_t Address, const void *Decoder) {
3174 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3175 true, 2, Inst, Decoder))
3176 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3177 return MCDisassembler::Success;
3180 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3181 uint64_t Address, const void *Decoder) {
3182 DecodeStatus S = MCDisassembler::Success;
3184 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3185 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3187 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3188 return MCDisassembler::Fail;
3189 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3190 return MCDisassembler::Fail;
3195 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3196 uint64_t Address, const void *Decoder) {
3197 DecodeStatus S = MCDisassembler::Success;
3199 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3200 unsigned imm = fieldFromInstruction(Val, 3, 5);
3202 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3203 return MCDisassembler::Fail;
3204 Inst.addOperand(MCOperand::CreateImm(imm));
3209 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3210 uint64_t Address, const void *Decoder) {
3211 unsigned imm = Val << 2;
3213 Inst.addOperand(MCOperand::CreateImm(imm));
3214 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3216 return MCDisassembler::Success;
3219 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3220 uint64_t Address, const void *Decoder) {
3221 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3222 Inst.addOperand(MCOperand::CreateImm(Val));
3224 return MCDisassembler::Success;
3227 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3228 uint64_t Address, const void *Decoder) {
3229 DecodeStatus S = MCDisassembler::Success;
3231 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3232 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3233 unsigned imm = fieldFromInstruction(Val, 0, 2);
3235 // Thumb stores cannot use PC as dest register.
3236 switch (Inst.getOpcode()) {
3241 return MCDisassembler::Fail;
3246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3247 return MCDisassembler::Fail;
3248 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3249 return MCDisassembler::Fail;
3250 Inst.addOperand(MCOperand::CreateImm(imm));
3255 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3256 uint64_t Address, const void *Decoder) {
3257 DecodeStatus S = MCDisassembler::Success;
3259 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3260 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3263 switch (Inst.getOpcode()) {
3265 Inst.setOpcode(ARM::t2LDRBpci);
3268 Inst.setOpcode(ARM::t2LDRHpci);
3271 Inst.setOpcode(ARM::t2LDRSHpci);
3274 Inst.setOpcode(ARM::t2LDRSBpci);
3277 Inst.setOpcode(ARM::t2LDRpci);
3280 Inst.setOpcode(ARM::t2PLDpci);
3283 Inst.setOpcode(ARM::t2PLIpci);
3286 return MCDisassembler::Fail;
3289 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3293 switch (Inst.getOpcode()) {
3295 return MCDisassembler::Fail;
3297 // FIXME: this instruction is only available with MP extensions,
3298 // this should be checked first but we don't have access to the
3299 // feature bits here.
3300 Inst.setOpcode(ARM::t2PLDWs);
3307 switch (Inst.getOpcode()) {
3313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3314 return MCDisassembler::Fail;
3317 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3318 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3319 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3320 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3321 return MCDisassembler::Fail;
3326 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3327 uint64_t Address, const void* Decoder) {
3328 DecodeStatus S = MCDisassembler::Success;
3330 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3331 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3332 unsigned U = fieldFromInstruction(Insn, 9, 1);
3333 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3338 switch (Inst.getOpcode()) {
3340 Inst.setOpcode(ARM::t2LDRpci);
3343 Inst.setOpcode(ARM::t2LDRBpci);
3345 case ARM::t2LDRSBi8:
3346 Inst.setOpcode(ARM::t2LDRSBpci);
3349 Inst.setOpcode(ARM::t2LDRHpci);
3351 case ARM::t2LDRSHi8:
3352 Inst.setOpcode(ARM::t2LDRSHpci);
3355 Inst.setOpcode(ARM::t2PLDpci);
3358 Inst.setOpcode(ARM::t2PLIpci);
3361 return MCDisassembler::Fail;
3363 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3367 switch (Inst.getOpcode()) {
3368 case ARM::t2LDRSHi8:
3369 return MCDisassembler::Fail;
3375 switch (Inst.getOpcode()) {
3381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3382 return MCDisassembler::Fail;
3385 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3386 return MCDisassembler::Fail;
3390 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3391 uint64_t Address, const void* Decoder) {
3392 DecodeStatus S = MCDisassembler::Success;
3394 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3395 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3396 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3400 switch (Inst.getOpcode()) {
3402 Inst.setOpcode(ARM::t2LDRpci);
3404 case ARM::t2LDRHi12:
3405 Inst.setOpcode(ARM::t2LDRHpci);
3407 case ARM::t2LDRSHi12:
3408 Inst.setOpcode(ARM::t2LDRSHpci);
3410 case ARM::t2LDRBi12:
3411 Inst.setOpcode(ARM::t2LDRBpci);
3413 case ARM::t2LDRSBi12:
3414 Inst.setOpcode(ARM::t2LDRSBpci);
3417 Inst.setOpcode(ARM::t2PLDpci);
3420 Inst.setOpcode(ARM::t2PLIpci);
3423 return MCDisassembler::Fail;
3425 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3429 switch (Inst.getOpcode()) {
3430 case ARM::t2LDRSHi12:
3431 return MCDisassembler::Fail;
3432 case ARM::t2LDRHi12:
3433 Inst.setOpcode(ARM::t2PLDi12);
3440 switch (Inst.getOpcode()) {
3442 case ARM::t2PLDWi12:
3446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3447 return MCDisassembler::Fail;
3450 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3451 return MCDisassembler::Fail;
3455 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3456 uint64_t Address, const void* Decoder) {
3457 DecodeStatus S = MCDisassembler::Success;
3459 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3460 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3461 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3465 switch (Inst.getOpcode()) {
3467 Inst.setOpcode(ARM::t2LDRpci);
3470 Inst.setOpcode(ARM::t2LDRBpci);
3473 Inst.setOpcode(ARM::t2LDRHpci);
3476 Inst.setOpcode(ARM::t2LDRSBpci);
3479 Inst.setOpcode(ARM::t2LDRSHpci);
3482 return MCDisassembler::Fail;
3484 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3487 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3488 return MCDisassembler::Fail;
3489 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3490 return MCDisassembler::Fail;
3494 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3495 uint64_t Address, const void* Decoder) {
3496 DecodeStatus S = MCDisassembler::Success;
3498 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3499 unsigned U = fieldFromInstruction(Insn, 23, 1);
3500 int imm = fieldFromInstruction(Insn, 0, 12);
3503 switch (Inst.getOpcode()) {
3504 case ARM::t2LDRBpci:
3505 case ARM::t2LDRHpci:
3506 Inst.setOpcode(ARM::t2PLDpci);
3508 case ARM::t2LDRSBpci:
3509 Inst.setOpcode(ARM::t2PLIpci);
3511 case ARM::t2LDRSHpci:
3512 return MCDisassembler::Fail;
3518 switch(Inst.getOpcode()) {
3523 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3524 return MCDisassembler::Fail;
3528 // Special case for #-0.
3534 Inst.addOperand(MCOperand::CreateImm(imm));
3539 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3540 uint64_t Address, const void *Decoder) {
3542 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3544 int imm = Val & 0xFF;
3546 if (!(Val & 0x100)) imm *= -1;
3547 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3550 return MCDisassembler::Success;
3553 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3554 uint64_t Address, const void *Decoder) {
3555 DecodeStatus S = MCDisassembler::Success;
3557 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3558 unsigned imm = fieldFromInstruction(Val, 0, 9);
3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3561 return MCDisassembler::Fail;
3562 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3563 return MCDisassembler::Fail;
3568 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3569 uint64_t Address, const void *Decoder) {
3570 DecodeStatus S = MCDisassembler::Success;
3572 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3573 unsigned imm = fieldFromInstruction(Val, 0, 8);
3575 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3576 return MCDisassembler::Fail;
3578 Inst.addOperand(MCOperand::CreateImm(imm));
3583 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3584 uint64_t Address, const void *Decoder) {
3585 int imm = Val & 0xFF;
3588 else if (!(Val & 0x100))
3590 Inst.addOperand(MCOperand::CreateImm(imm));
3592 return MCDisassembler::Success;
3596 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3597 uint64_t Address, const void *Decoder) {
3598 DecodeStatus S = MCDisassembler::Success;
3600 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3601 unsigned imm = fieldFromInstruction(Val, 0, 9);
3603 // Thumb stores cannot use PC as dest register.
3604 switch (Inst.getOpcode()) {
3612 return MCDisassembler::Fail;
3618 // Some instructions always use an additive offset.
3619 switch (Inst.getOpcode()) {
3634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3635 return MCDisassembler::Fail;
3636 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3637 return MCDisassembler::Fail;
3642 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3643 uint64_t Address, const void *Decoder) {
3644 DecodeStatus S = MCDisassembler::Success;
3646 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3647 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3648 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3649 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3651 unsigned load = fieldFromInstruction(Insn, 20, 1);
3654 switch (Inst.getOpcode()) {
3655 case ARM::t2LDR_PRE:
3656 case ARM::t2LDR_POST:
3657 Inst.setOpcode(ARM::t2LDRpci);
3659 case ARM::t2LDRB_PRE:
3660 case ARM::t2LDRB_POST:
3661 Inst.setOpcode(ARM::t2LDRBpci);
3663 case ARM::t2LDRH_PRE:
3664 case ARM::t2LDRH_POST:
3665 Inst.setOpcode(ARM::t2LDRHpci);
3667 case ARM::t2LDRSB_PRE:
3668 case ARM::t2LDRSB_POST:
3670 Inst.setOpcode(ARM::t2PLIpci);
3672 Inst.setOpcode(ARM::t2LDRSBpci);
3674 case ARM::t2LDRSH_PRE:
3675 case ARM::t2LDRSH_POST:
3676 Inst.setOpcode(ARM::t2LDRSHpci);
3679 return MCDisassembler::Fail;
3681 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3686 return MCDisassembler::Fail;
3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3690 return MCDisassembler::Fail;
3693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3694 return MCDisassembler::Fail;
3697 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3698 return MCDisassembler::Fail;
3703 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3704 uint64_t Address, const void *Decoder) {
3705 DecodeStatus S = MCDisassembler::Success;
3707 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3708 unsigned imm = fieldFromInstruction(Val, 0, 12);
3710 // Thumb stores cannot use PC as dest register.
3711 switch (Inst.getOpcode()) {
3713 case ARM::t2STRBi12:
3714 case ARM::t2STRHi12:
3716 return MCDisassembler::Fail;
3721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3722 return MCDisassembler::Fail;
3723 Inst.addOperand(MCOperand::CreateImm(imm));
3729 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3730 uint64_t Address, const void *Decoder) {
3731 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3733 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3734 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3735 Inst.addOperand(MCOperand::CreateImm(imm));
3737 return MCDisassembler::Success;
3740 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3741 uint64_t Address, const void *Decoder) {
3742 DecodeStatus S = MCDisassembler::Success;
3744 if (Inst.getOpcode() == ARM::tADDrSP) {
3745 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3746 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3749 return MCDisassembler::Fail;
3750 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3752 return MCDisassembler::Fail;
3753 } else if (Inst.getOpcode() == ARM::tADDspr) {
3754 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3756 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3757 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3759 return MCDisassembler::Fail;
3765 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3766 uint64_t Address, const void *Decoder) {
3767 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3768 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3770 Inst.addOperand(MCOperand::CreateImm(imod));
3771 Inst.addOperand(MCOperand::CreateImm(flags));
3773 return MCDisassembler::Success;
3776 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3777 uint64_t Address, const void *Decoder) {
3778 DecodeStatus S = MCDisassembler::Success;
3779 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3780 unsigned add = fieldFromInstruction(Insn, 4, 1);
3782 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3783 return MCDisassembler::Fail;
3784 Inst.addOperand(MCOperand::CreateImm(add));
3789 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3790 uint64_t Address, const void *Decoder) {
3791 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3792 // Note only one trailing zero not two. Also the J1 and J2 values are from
3793 // the encoded instruction. So here change to I1 and I2 values via:
3794 // I1 = NOT(J1 EOR S);
3795 // I2 = NOT(J2 EOR S);
3796 // and build the imm32 with two trailing zeros as documented:
3797 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3798 unsigned S = (Val >> 23) & 1;
3799 unsigned J1 = (Val >> 22) & 1;
3800 unsigned J2 = (Val >> 21) & 1;
3801 unsigned I1 = !(J1 ^ S);
3802 unsigned I2 = !(J2 ^ S);
3803 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3804 int imm32 = SignExtend32<25>(tmp << 1);
3806 if (!tryAddingSymbolicOperand(Address,
3807 (Address & ~2u) + imm32 + 4,
3808 true, 4, Inst, Decoder))
3809 Inst.addOperand(MCOperand::CreateImm(imm32));
3810 return MCDisassembler::Success;
3813 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3814 uint64_t Address, const void *Decoder) {
3815 if (Val == 0xA || Val == 0xB)
3816 return MCDisassembler::Fail;
3818 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3820 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3821 return MCDisassembler::Fail;
3823 Inst.addOperand(MCOperand::CreateImm(Val));
3824 return MCDisassembler::Success;
3828 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3829 uint64_t Address, const void *Decoder) {
3830 DecodeStatus S = MCDisassembler::Success;
3832 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3833 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3835 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3837 return MCDisassembler::Fail;
3838 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3839 return MCDisassembler::Fail;
3844 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3845 uint64_t Address, const void *Decoder) {
3846 DecodeStatus S = MCDisassembler::Success;
3848 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3849 if (pred == 0xE || pred == 0xF) {
3850 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3853 return MCDisassembler::Fail;
3855 Inst.setOpcode(ARM::t2DSB);
3858 Inst.setOpcode(ARM::t2DMB);
3861 Inst.setOpcode(ARM::t2ISB);
3865 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3866 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3869 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3870 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3871 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3872 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3873 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3875 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3876 return MCDisassembler::Fail;
3877 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3878 return MCDisassembler::Fail;
3883 // Decode a shifted immediate operand. These basically consist
3884 // of an 8-bit value, and a 4-bit directive that specifies either
3885 // a splat operation or a rotation.
3886 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3887 uint64_t Address, const void *Decoder) {
3888 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3890 unsigned byte = fieldFromInstruction(Val, 8, 2);
3891 unsigned imm = fieldFromInstruction(Val, 0, 8);
3894 Inst.addOperand(MCOperand::CreateImm(imm));
3897 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3900 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3903 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3908 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3909 unsigned rot = fieldFromInstruction(Val, 7, 5);
3910 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3911 Inst.addOperand(MCOperand::CreateImm(imm));
3914 return MCDisassembler::Success;
3918 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3919 uint64_t Address, const void *Decoder){
3920 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3921 true, 2, Inst, Decoder))
3922 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3923 return MCDisassembler::Success;
3926 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3927 uint64_t Address, const void *Decoder){
3928 // Val is passed in as S:J1:J2:imm10:imm11
3929 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3930 // the encoded instruction. So here change to I1 and I2 values via:
3931 // I1 = NOT(J1 EOR S);
3932 // I2 = NOT(J2 EOR S);
3933 // and build the imm32 with one trailing zero as documented:
3934 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3935 unsigned S = (Val >> 23) & 1;
3936 unsigned J1 = (Val >> 22) & 1;
3937 unsigned J2 = (Val >> 21) & 1;
3938 unsigned I1 = !(J1 ^ S);
3939 unsigned I2 = !(J2 ^ S);
3940 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3941 int imm32 = SignExtend32<25>(tmp << 1);
3943 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3944 true, 4, Inst, Decoder))
3945 Inst.addOperand(MCOperand::CreateImm(imm32));
3946 return MCDisassembler::Success;
3949 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3950 uint64_t Address, const void *Decoder) {
3952 return MCDisassembler::Fail;
3954 Inst.addOperand(MCOperand::CreateImm(Val));
3955 return MCDisassembler::Success;
3958 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
3959 uint64_t Address, const void *Decoder) {
3961 return MCDisassembler::Fail;
3963 Inst.addOperand(MCOperand::CreateImm(Val));
3964 return MCDisassembler::Success;
3967 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3968 uint64_t Address, const void *Decoder) {
3969 if (!Val) return MCDisassembler::Fail;
3970 Inst.addOperand(MCOperand::CreateImm(Val));
3971 return MCDisassembler::Success;
3974 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3975 uint64_t Address, const void *Decoder) {
3976 DecodeStatus S = MCDisassembler::Success;
3978 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3979 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3980 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3983 S = MCDisassembler::SoftFail;
3985 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
3986 return MCDisassembler::Fail;
3987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3988 return MCDisassembler::Fail;
3989 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3990 return MCDisassembler::Fail;
3995 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
3996 uint64_t Address, const void *Decoder){
3997 DecodeStatus S = MCDisassembler::Success;
3999 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4000 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4001 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4002 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4004 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4005 return MCDisassembler::Fail;
4007 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4008 S = MCDisassembler::SoftFail;
4010 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4011 return MCDisassembler::Fail;
4012 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4013 return MCDisassembler::Fail;
4014 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4015 return MCDisassembler::Fail;
4020 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4021 uint64_t Address, const void *Decoder) {
4022 DecodeStatus S = MCDisassembler::Success;
4024 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4025 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4026 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4027 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4028 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4029 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4031 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4034 return MCDisassembler::Fail;
4035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4036 return MCDisassembler::Fail;
4037 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4038 return MCDisassembler::Fail;
4039 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4040 return MCDisassembler::Fail;
4045 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4046 uint64_t Address, const void *Decoder) {
4047 DecodeStatus S = MCDisassembler::Success;
4049 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4050 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4051 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4052 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4053 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4054 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4055 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4057 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4058 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4061 return MCDisassembler::Fail;
4062 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4063 return MCDisassembler::Fail;
4064 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4065 return MCDisassembler::Fail;
4066 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4067 return MCDisassembler::Fail;
4073 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4074 uint64_t Address, const void *Decoder) {
4075 DecodeStatus S = MCDisassembler::Success;
4077 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4078 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4079 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4080 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4081 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4082 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4084 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4087 return MCDisassembler::Fail;
4088 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4089 return MCDisassembler::Fail;
4090 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4091 return MCDisassembler::Fail;
4092 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4093 return MCDisassembler::Fail;
4098 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4099 uint64_t Address, const void *Decoder) {
4100 DecodeStatus S = MCDisassembler::Success;
4102 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4103 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4104 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4105 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4106 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4107 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4109 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4111 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4112 return MCDisassembler::Fail;
4113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4114 return MCDisassembler::Fail;
4115 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4116 return MCDisassembler::Fail;
4117 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4118 return MCDisassembler::Fail;
4123 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4124 uint64_t Address, const void *Decoder) {
4125 DecodeStatus S = MCDisassembler::Success;
4127 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4128 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4129 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4130 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4131 unsigned size = fieldFromInstruction(Insn, 10, 2);
4137 return MCDisassembler::Fail;
4139 if (fieldFromInstruction(Insn, 4, 1))
4140 return MCDisassembler::Fail; // UNDEFINED
4141 index = fieldFromInstruction(Insn, 5, 3);
4144 if (fieldFromInstruction(Insn, 5, 1))
4145 return MCDisassembler::Fail; // UNDEFINED
4146 index = fieldFromInstruction(Insn, 6, 2);
4147 if (fieldFromInstruction(Insn, 4, 1))
4151 if (fieldFromInstruction(Insn, 6, 1))
4152 return MCDisassembler::Fail; // UNDEFINED
4153 index = fieldFromInstruction(Insn, 7, 1);
4155 switch (fieldFromInstruction(Insn, 4, 2)) {
4161 return MCDisassembler::Fail;
4166 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4167 return MCDisassembler::Fail;
4168 if (Rm != 0xF) { // Writeback
4169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4170 return MCDisassembler::Fail;
4172 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4173 return MCDisassembler::Fail;
4174 Inst.addOperand(MCOperand::CreateImm(align));
4177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4178 return MCDisassembler::Fail;
4180 Inst.addOperand(MCOperand::CreateReg(0));
4183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4184 return MCDisassembler::Fail;
4185 Inst.addOperand(MCOperand::CreateImm(index));
4190 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4191 uint64_t Address, const void *Decoder) {
4192 DecodeStatus S = MCDisassembler::Success;
4194 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4195 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4196 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4197 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4198 unsigned size = fieldFromInstruction(Insn, 10, 2);
4204 return MCDisassembler::Fail;
4206 if (fieldFromInstruction(Insn, 4, 1))
4207 return MCDisassembler::Fail; // UNDEFINED
4208 index = fieldFromInstruction(Insn, 5, 3);
4211 if (fieldFromInstruction(Insn, 5, 1))
4212 return MCDisassembler::Fail; // UNDEFINED
4213 index = fieldFromInstruction(Insn, 6, 2);
4214 if (fieldFromInstruction(Insn, 4, 1))
4218 if (fieldFromInstruction(Insn, 6, 1))
4219 return MCDisassembler::Fail; // UNDEFINED
4220 index = fieldFromInstruction(Insn, 7, 1);
4222 switch (fieldFromInstruction(Insn, 4, 2)) {
4228 return MCDisassembler::Fail;
4233 if (Rm != 0xF) { // Writeback
4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4235 return MCDisassembler::Fail;
4237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4238 return MCDisassembler::Fail;
4239 Inst.addOperand(MCOperand::CreateImm(align));
4242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4243 return MCDisassembler::Fail;
4245 Inst.addOperand(MCOperand::CreateReg(0));
4248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4249 return MCDisassembler::Fail;
4250 Inst.addOperand(MCOperand::CreateImm(index));
4256 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4257 uint64_t Address, const void *Decoder) {
4258 DecodeStatus S = MCDisassembler::Success;
4260 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4261 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4262 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4263 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4264 unsigned size = fieldFromInstruction(Insn, 10, 2);
4271 return MCDisassembler::Fail;
4273 index = fieldFromInstruction(Insn, 5, 3);
4274 if (fieldFromInstruction(Insn, 4, 1))
4278 index = fieldFromInstruction(Insn, 6, 2);
4279 if (fieldFromInstruction(Insn, 4, 1))
4281 if (fieldFromInstruction(Insn, 5, 1))
4285 if (fieldFromInstruction(Insn, 5, 1))
4286 return MCDisassembler::Fail; // UNDEFINED
4287 index = fieldFromInstruction(Insn, 7, 1);
4288 if (fieldFromInstruction(Insn, 4, 1) != 0)
4290 if (fieldFromInstruction(Insn, 6, 1))
4295 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4296 return MCDisassembler::Fail;
4297 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4298 return MCDisassembler::Fail;
4299 if (Rm != 0xF) { // Writeback
4300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4301 return MCDisassembler::Fail;
4303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4304 return MCDisassembler::Fail;
4305 Inst.addOperand(MCOperand::CreateImm(align));
4308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4309 return MCDisassembler::Fail;
4311 Inst.addOperand(MCOperand::CreateReg(0));
4314 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4315 return MCDisassembler::Fail;
4316 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4317 return MCDisassembler::Fail;
4318 Inst.addOperand(MCOperand::CreateImm(index));
4323 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4324 uint64_t Address, const void *Decoder) {
4325 DecodeStatus S = MCDisassembler::Success;
4327 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4328 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4329 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4330 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4331 unsigned size = fieldFromInstruction(Insn, 10, 2);
4338 return MCDisassembler::Fail;
4340 index = fieldFromInstruction(Insn, 5, 3);
4341 if (fieldFromInstruction(Insn, 4, 1))
4345 index = fieldFromInstruction(Insn, 6, 2);
4346 if (fieldFromInstruction(Insn, 4, 1))
4348 if (fieldFromInstruction(Insn, 5, 1))
4352 if (fieldFromInstruction(Insn, 5, 1))
4353 return MCDisassembler::Fail; // UNDEFINED
4354 index = fieldFromInstruction(Insn, 7, 1);
4355 if (fieldFromInstruction(Insn, 4, 1) != 0)
4357 if (fieldFromInstruction(Insn, 6, 1))
4362 if (Rm != 0xF) { // Writeback
4363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4364 return MCDisassembler::Fail;
4366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4367 return MCDisassembler::Fail;
4368 Inst.addOperand(MCOperand::CreateImm(align));
4371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4372 return MCDisassembler::Fail;
4374 Inst.addOperand(MCOperand::CreateReg(0));
4377 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4378 return MCDisassembler::Fail;
4379 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4380 return MCDisassembler::Fail;
4381 Inst.addOperand(MCOperand::CreateImm(index));
4387 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4388 uint64_t Address, const void *Decoder) {
4389 DecodeStatus S = MCDisassembler::Success;
4391 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4392 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4393 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4394 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4395 unsigned size = fieldFromInstruction(Insn, 10, 2);
4402 return MCDisassembler::Fail;
4404 if (fieldFromInstruction(Insn, 4, 1))
4405 return MCDisassembler::Fail; // UNDEFINED
4406 index = fieldFromInstruction(Insn, 5, 3);
4409 if (fieldFromInstruction(Insn, 4, 1))
4410 return MCDisassembler::Fail; // UNDEFINED
4411 index = fieldFromInstruction(Insn, 6, 2);
4412 if (fieldFromInstruction(Insn, 5, 1))
4416 if (fieldFromInstruction(Insn, 4, 2))
4417 return MCDisassembler::Fail; // UNDEFINED
4418 index = fieldFromInstruction(Insn, 7, 1);
4419 if (fieldFromInstruction(Insn, 6, 1))
4424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4425 return MCDisassembler::Fail;
4426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4427 return MCDisassembler::Fail;
4428 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4429 return MCDisassembler::Fail;
4431 if (Rm != 0xF) { // Writeback
4432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4433 return MCDisassembler::Fail;
4435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4436 return MCDisassembler::Fail;
4437 Inst.addOperand(MCOperand::CreateImm(align));
4440 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4441 return MCDisassembler::Fail;
4443 Inst.addOperand(MCOperand::CreateReg(0));
4446 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4447 return MCDisassembler::Fail;
4448 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4449 return MCDisassembler::Fail;
4450 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4451 return MCDisassembler::Fail;
4452 Inst.addOperand(MCOperand::CreateImm(index));
4457 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4458 uint64_t Address, const void *Decoder) {
4459 DecodeStatus S = MCDisassembler::Success;
4461 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4462 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4463 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4464 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4465 unsigned size = fieldFromInstruction(Insn, 10, 2);
4472 return MCDisassembler::Fail;
4474 if (fieldFromInstruction(Insn, 4, 1))
4475 return MCDisassembler::Fail; // UNDEFINED
4476 index = fieldFromInstruction(Insn, 5, 3);
4479 if (fieldFromInstruction(Insn, 4, 1))
4480 return MCDisassembler::Fail; // UNDEFINED
4481 index = fieldFromInstruction(Insn, 6, 2);
4482 if (fieldFromInstruction(Insn, 5, 1))
4486 if (fieldFromInstruction(Insn, 4, 2))
4487 return MCDisassembler::Fail; // UNDEFINED
4488 index = fieldFromInstruction(Insn, 7, 1);
4489 if (fieldFromInstruction(Insn, 6, 1))
4494 if (Rm != 0xF) { // Writeback
4495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4496 return MCDisassembler::Fail;
4498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4499 return MCDisassembler::Fail;
4500 Inst.addOperand(MCOperand::CreateImm(align));
4503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4504 return MCDisassembler::Fail;
4506 Inst.addOperand(MCOperand::CreateReg(0));
4509 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4510 return MCDisassembler::Fail;
4511 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4512 return MCDisassembler::Fail;
4513 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4514 return MCDisassembler::Fail;
4515 Inst.addOperand(MCOperand::CreateImm(index));
4521 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4522 uint64_t Address, const void *Decoder) {
4523 DecodeStatus S = MCDisassembler::Success;
4525 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4526 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4527 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4528 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4529 unsigned size = fieldFromInstruction(Insn, 10, 2);
4536 return MCDisassembler::Fail;
4538 if (fieldFromInstruction(Insn, 4, 1))
4540 index = fieldFromInstruction(Insn, 5, 3);
4543 if (fieldFromInstruction(Insn, 4, 1))
4545 index = fieldFromInstruction(Insn, 6, 2);
4546 if (fieldFromInstruction(Insn, 5, 1))
4550 switch (fieldFromInstruction(Insn, 4, 2)) {
4554 return MCDisassembler::Fail;
4556 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4559 index = fieldFromInstruction(Insn, 7, 1);
4560 if (fieldFromInstruction(Insn, 6, 1))
4565 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4566 return MCDisassembler::Fail;
4567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4568 return MCDisassembler::Fail;
4569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4570 return MCDisassembler::Fail;
4571 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4572 return MCDisassembler::Fail;
4574 if (Rm != 0xF) { // Writeback
4575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4576 return MCDisassembler::Fail;
4578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4579 return MCDisassembler::Fail;
4580 Inst.addOperand(MCOperand::CreateImm(align));
4583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4584 return MCDisassembler::Fail;
4586 Inst.addOperand(MCOperand::CreateReg(0));
4589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4590 return MCDisassembler::Fail;
4591 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4592 return MCDisassembler::Fail;
4593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4594 return MCDisassembler::Fail;
4595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4596 return MCDisassembler::Fail;
4597 Inst.addOperand(MCOperand::CreateImm(index));
4602 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4603 uint64_t Address, const void *Decoder) {
4604 DecodeStatus S = MCDisassembler::Success;
4606 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4607 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4608 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4609 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4610 unsigned size = fieldFromInstruction(Insn, 10, 2);
4617 return MCDisassembler::Fail;
4619 if (fieldFromInstruction(Insn, 4, 1))
4621 index = fieldFromInstruction(Insn, 5, 3);
4624 if (fieldFromInstruction(Insn, 4, 1))
4626 index = fieldFromInstruction(Insn, 6, 2);
4627 if (fieldFromInstruction(Insn, 5, 1))
4631 switch (fieldFromInstruction(Insn, 4, 2)) {
4635 return MCDisassembler::Fail;
4637 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4640 index = fieldFromInstruction(Insn, 7, 1);
4641 if (fieldFromInstruction(Insn, 6, 1))
4646 if (Rm != 0xF) { // Writeback
4647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4648 return MCDisassembler::Fail;
4650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4651 return MCDisassembler::Fail;
4652 Inst.addOperand(MCOperand::CreateImm(align));
4655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4656 return MCDisassembler::Fail;
4658 Inst.addOperand(MCOperand::CreateReg(0));
4661 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4662 return MCDisassembler::Fail;
4663 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4664 return MCDisassembler::Fail;
4665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4666 return MCDisassembler::Fail;
4667 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4668 return MCDisassembler::Fail;
4669 Inst.addOperand(MCOperand::CreateImm(index));
4674 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4675 uint64_t Address, const void *Decoder) {
4676 DecodeStatus S = MCDisassembler::Success;
4677 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4678 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4679 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4680 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4681 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4683 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4684 S = MCDisassembler::SoftFail;
4686 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4687 return MCDisassembler::Fail;
4688 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4689 return MCDisassembler::Fail;
4690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4691 return MCDisassembler::Fail;
4692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4693 return MCDisassembler::Fail;
4694 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4695 return MCDisassembler::Fail;
4700 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4701 uint64_t Address, const void *Decoder) {
4702 DecodeStatus S = MCDisassembler::Success;
4703 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4704 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4705 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4706 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4707 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4709 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4710 S = MCDisassembler::SoftFail;
4712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4713 return MCDisassembler::Fail;
4714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4715 return MCDisassembler::Fail;
4716 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4717 return MCDisassembler::Fail;
4718 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4719 return MCDisassembler::Fail;
4720 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4721 return MCDisassembler::Fail;
4726 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4727 uint64_t Address, const void *Decoder) {
4728 DecodeStatus S = MCDisassembler::Success;
4729 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4730 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4734 S = MCDisassembler::SoftFail;
4738 return MCDisassembler::Fail;
4740 Inst.addOperand(MCOperand::CreateImm(pred));
4741 Inst.addOperand(MCOperand::CreateImm(mask));
4746 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4747 uint64_t Address, const void *Decoder) {
4748 DecodeStatus S = MCDisassembler::Success;
4750 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4751 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4752 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4753 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4754 unsigned W = fieldFromInstruction(Insn, 21, 1);
4755 unsigned U = fieldFromInstruction(Insn, 23, 1);
4756 unsigned P = fieldFromInstruction(Insn, 24, 1);
4757 bool writeback = (W == 1) | (P == 0);
4759 addr |= (U << 8) | (Rn << 9);
4761 if (writeback && (Rn == Rt || Rn == Rt2))
4762 Check(S, MCDisassembler::SoftFail);
4764 Check(S, MCDisassembler::SoftFail);
4767 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4768 return MCDisassembler::Fail;
4770 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4771 return MCDisassembler::Fail;
4772 // Writeback operand
4773 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4774 return MCDisassembler::Fail;
4776 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4777 return MCDisassembler::Fail;
4783 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4784 uint64_t Address, const void *Decoder) {
4785 DecodeStatus S = MCDisassembler::Success;
4787 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4788 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4789 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4790 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4791 unsigned W = fieldFromInstruction(Insn, 21, 1);
4792 unsigned U = fieldFromInstruction(Insn, 23, 1);
4793 unsigned P = fieldFromInstruction(Insn, 24, 1);
4794 bool writeback = (W == 1) | (P == 0);
4796 addr |= (U << 8) | (Rn << 9);
4798 if (writeback && (Rn == Rt || Rn == Rt2))
4799 Check(S, MCDisassembler::SoftFail);
4801 // Writeback operand
4802 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4803 return MCDisassembler::Fail;
4805 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4806 return MCDisassembler::Fail;
4808 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4809 return MCDisassembler::Fail;
4811 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4812 return MCDisassembler::Fail;
4817 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4818 uint64_t Address, const void *Decoder) {
4819 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4820 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4821 if (sign1 != sign2) return MCDisassembler::Fail;
4823 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4824 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4825 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4827 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4829 return MCDisassembler::Success;
4832 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4834 const void *Decoder) {
4835 DecodeStatus S = MCDisassembler::Success;
4837 // Shift of "asr #32" is not allowed in Thumb2 mode.
4838 if (Val == 0x20) S = MCDisassembler::SoftFail;
4839 Inst.addOperand(MCOperand::CreateImm(Val));
4843 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4844 uint64_t Address, const void *Decoder) {
4845 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4846 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4847 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4848 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4851 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4853 DecodeStatus S = MCDisassembler::Success;
4855 if (Rt == Rn || Rn == Rt2)
4856 S = MCDisassembler::SoftFail;
4858 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4859 return MCDisassembler::Fail;
4860 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4861 return MCDisassembler::Fail;
4862 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4863 return MCDisassembler::Fail;
4864 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4865 return MCDisassembler::Fail;
4870 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4871 uint64_t Address, const void *Decoder) {
4872 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4873 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4874 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4875 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4876 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4877 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4878 unsigned op = fieldFromInstruction(Insn, 5, 1);
4880 DecodeStatus S = MCDisassembler::Success;
4882 // VMOVv2f32 is ambiguous with these decodings.
4883 if (!(imm & 0x38) && cmode == 0xF) {
4884 if (op == 1) return MCDisassembler::Fail;
4885 Inst.setOpcode(ARM::VMOVv2f32);
4886 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4889 if (!(imm & 0x20)) return MCDisassembler::Fail;
4891 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4892 return MCDisassembler::Fail;
4893 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4894 return MCDisassembler::Fail;
4895 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4900 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4901 uint64_t Address, const void *Decoder) {
4902 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4903 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4904 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4905 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4906 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4907 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4908 unsigned op = fieldFromInstruction(Insn, 5, 1);
4910 DecodeStatus S = MCDisassembler::Success;
4912 // VMOVv4f32 is ambiguous with these decodings.
4913 if (!(imm & 0x38) && cmode == 0xF) {
4914 if (op == 1) return MCDisassembler::Fail;
4915 Inst.setOpcode(ARM::VMOVv4f32);
4916 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4919 if (!(imm & 0x20)) return MCDisassembler::Fail;
4921 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4922 return MCDisassembler::Fail;
4923 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4924 return MCDisassembler::Fail;
4925 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4930 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4931 uint64_t Address, const void *Decoder) {
4932 DecodeStatus S = MCDisassembler::Success;
4934 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4935 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4936 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4937 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4938 unsigned Cond = fieldFromInstruction(Val, 28, 4);
4940 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
4941 S = MCDisassembler::SoftFail;
4943 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4944 return MCDisassembler::Fail;
4945 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4946 return MCDisassembler::Fail;
4947 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4948 return MCDisassembler::Fail;
4949 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4950 return MCDisassembler::Fail;
4951 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4952 return MCDisassembler::Fail;
4957 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4958 uint64_t Address, const void *Decoder) {
4960 DecodeStatus S = MCDisassembler::Success;
4962 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4963 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4964 unsigned cop = fieldFromInstruction(Val, 8, 4);
4965 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4966 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
4968 if ((cop & ~0x1) == 0xa)
4969 return MCDisassembler::Fail;
4972 S = MCDisassembler::SoftFail;
4974 Inst.addOperand(MCOperand::CreateImm(cop));
4975 Inst.addOperand(MCOperand::CreateImm(opc1));
4976 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4977 return MCDisassembler::Fail;
4978 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4979 return MCDisassembler::Fail;
4980 Inst.addOperand(MCOperand::CreateImm(CRm));