1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSectionMachO.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegistry.h"
44 #include "llvm/ADT/SmallPtrSet.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/StringSet.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/FormattedStream.h"
51 #include "llvm/Support/MathExtras.h"
56 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
57 cl::desc("enable experimental asmprinter gunk in the arm backend"));
60 class ARMAsmPrinter : public AsmPrinter {
62 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
63 /// make the right decision when printing asm code for different targets.
64 const ARMSubtarget *Subtarget;
66 /// AFI - Keep a pointer to ARMFunctionInfo for the current
70 /// MCP - Keep a pointer to constantpool entries of the current
72 const MachineConstantPool *MCP;
75 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
76 MCContext &Ctx, MCStreamer &Streamer,
78 : AsmPrinter(O, TM, Ctx, Streamer, T), AFI(NULL), MCP(NULL) {
79 Subtarget = &TM.getSubtarget<ARMSubtarget>();
82 virtual const char *getPassName() const {
83 return "ARM Assembly Printer";
86 void printInstructionThroughMCStreamer(const MachineInstr *MI);
89 void printOperand(const MachineInstr *MI, int OpNum,
90 const char *Modifier = 0);
91 void printSOImmOperand(const MachineInstr *MI, int OpNum);
92 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
93 void printSORegOperand(const MachineInstr *MI, int OpNum);
94 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
95 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
96 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
97 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
98 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
99 const char *Modifier = 0);
100 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
101 const char *Modifier = 0);
102 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
103 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
104 const char *Modifier = 0);
105 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
107 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
108 void printThumbITMask(const MachineInstr *MI, int OpNum);
109 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
110 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
112 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
113 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
117 void printT2SOOperand(const MachineInstr *MI, int OpNum);
118 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
119 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
120 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
121 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
122 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
124 void printPredicateOperand(const MachineInstr *MI, int OpNum);
125 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
126 void printPCLabel(const MachineInstr *MI, int OpNum);
127 void printRegisterList(const MachineInstr *MI, int OpNum);
128 void printCPInstOperand(const MachineInstr *MI, int OpNum,
129 const char *Modifier);
130 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
131 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
132 void printTBAddrMode(const MachineInstr *MI, int OpNum);
133 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
134 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
135 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
137 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
138 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
140 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
141 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
143 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
144 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
146 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
147 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
150 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
151 unsigned AsmVariant, const char *ExtraCode);
152 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
154 const char *ExtraCode);
156 void printInstruction(const MachineInstr *MI); // autogenerated.
157 static const char *getRegisterName(unsigned RegNo);
159 virtual void EmitInstruction(const MachineInstr *MI);
160 bool runOnMachineFunction(MachineFunction &F);
162 virtual void EmitConstantPool() {} // we emit constant pools customly!
163 virtual void EmitFunctionEntryLabel();
164 void EmitStartOfAsmFile(Module &M);
165 void EmitEndOfAsmFile(Module &M);
167 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
168 const MachineBasicBlock *MBB) const;
169 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
171 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
173 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
174 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
175 case 1: O << MAI->getData8bitsDirective(0); break;
176 case 2: O << MAI->getData16bitsDirective(0); break;
177 case 4: O << MAI->getData32bitsDirective(0); break;
178 default: assert(0 && "Unknown CPV size");
181 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
182 SmallString<128> TmpNameStr;
184 if (ACPV->isLSDA()) {
185 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
186 "_LSDA_" << getFunctionNumber();
187 O << TmpNameStr.str();
188 } else if (ACPV->isBlockAddress()) {
189 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
190 } else if (ACPV->isGlobalValue()) {
191 GlobalValue *GV = ACPV->getGV();
192 bool isIndirect = Subtarget->isTargetDarwin() &&
193 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
195 O << *GetGlobalValueSymbol(GV);
197 // FIXME: Remove this when Darwin transition to @GOT like syntax.
198 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
201 MachineModuleInfoMachO &MMIMachO =
202 MMI->getObjFileInfo<MachineModuleInfoMachO>();
204 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
205 MMIMachO.getGVStubEntry(Sym);
207 StubSym = GetGlobalValueSymbol(GV);
210 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
211 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
214 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
215 if (ACPV->getPCAdjustment() != 0) {
216 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
217 << getFunctionNumber() << "_" << ACPV->getLabelId()
218 << "+" << (unsigned)ACPV->getPCAdjustment();
219 if (ACPV->mustAddCurrentAddress())
223 OutStreamer.AddBlankLine();
226 void getAnalysisUsage(AnalysisUsage &AU) const {
227 AsmPrinter::getAnalysisUsage(AU);
228 AU.setPreservesAll();
229 AU.addRequired<MachineModuleInfo>();
230 AU.addRequired<DwarfWriter>();
233 } // end of anonymous namespace
235 #include "ARMGenAsmWriter.inc"
237 void ARMAsmPrinter::EmitFunctionEntryLabel() {
238 if (AFI->isThumbFunction()) {
239 O << "\t.code\t16\n";
240 O << "\t.thumb_func";
241 if (Subtarget->isTargetDarwin())
242 O << '\t' << *CurrentFnSym;
246 OutStreamer.EmitLabel(CurrentFnSym);
249 /// runOnMachineFunction - This uses the printInstruction()
250 /// method to print assembly for each instruction.
252 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
253 AFI = MF.getInfo<ARMFunctionInfo>();
254 MCP = MF.getConstantPool();
256 return AsmPrinter::runOnMachineFunction(MF);
259 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
260 const char *Modifier) {
261 const MachineOperand &MO = MI->getOperand(OpNum);
262 unsigned TF = MO.getTargetFlags();
264 switch (MO.getType()) {
266 assert(0 && "<unknown operand type>");
267 case MachineOperand::MO_Register: {
268 unsigned Reg = MO.getReg();
269 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
270 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
271 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
272 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
274 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
276 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
277 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
278 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
279 &ARM::DPR_VFP2RegClass);
280 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
282 assert(!MO.getSubReg() && "Subregs should be eliminated!");
283 O << getRegisterName(Reg);
287 case MachineOperand::MO_Immediate: {
288 int64_t Imm = MO.getImm();
290 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
291 (TF & ARMII::MO_LO16))
293 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
294 (TF & ARMII::MO_HI16))
299 case MachineOperand::MO_MachineBasicBlock:
300 O << *MO.getMBB()->getSymbol(OutContext);
302 case MachineOperand::MO_GlobalAddress: {
303 bool isCallOp = Modifier && !strcmp(Modifier, "call");
304 GlobalValue *GV = MO.getGlobal();
306 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
307 (TF & ARMII::MO_LO16))
309 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
310 (TF & ARMII::MO_HI16))
312 O << *GetGlobalValueSymbol(GV);
314 printOffset(MO.getOffset());
316 if (isCallOp && Subtarget->isTargetELF() &&
317 TM.getRelocationModel() == Reloc::PIC_)
321 case MachineOperand::MO_ExternalSymbol: {
322 bool isCallOp = Modifier && !strcmp(Modifier, "call");
323 O << *GetExternalSymbolSymbol(MO.getSymbolName());
325 if (isCallOp && Subtarget->isTargetELF() &&
326 TM.getRelocationModel() == Reloc::PIC_)
330 case MachineOperand::MO_ConstantPoolIndex:
331 O << *GetCPISymbol(MO.getIndex());
333 case MachineOperand::MO_JumpTableIndex:
334 O << *GetJTISymbol(MO.getIndex());
339 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
340 const MCAsmInfo *MAI) {
341 // Break it up into two parts that make up a shifter immediate.
342 V = ARM_AM::getSOImmVal(V);
343 assert(V != -1 && "Not a valid so_imm value!");
345 unsigned Imm = ARM_AM::getSOImmValImm(V);
346 unsigned Rot = ARM_AM::getSOImmValRot(V);
348 // Print low-level immediate formation info, per
349 // A5.1.3: "Data-processing operands - Immediate".
351 O << "#" << Imm << ", " << Rot;
352 // Pretty printed version.
354 O.PadToColumn(MAI->getCommentColumn());
355 O << MAI->getCommentString() << ' ';
356 O << (int)ARM_AM::rotr32(Imm, Rot);
363 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
364 /// immediate in bits 0-7.
365 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
366 const MachineOperand &MO = MI->getOperand(OpNum);
367 assert(MO.isImm() && "Not a valid so_imm value!");
368 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
371 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
372 /// followed by an 'orr' to materialize.
373 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
374 const MachineOperand &MO = MI->getOperand(OpNum);
375 assert(MO.isImm() && "Not a valid so_imm value!");
376 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
377 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
378 printSOImm(O, V1, VerboseAsm, MAI);
380 printPredicateOperand(MI, 2);
386 printSOImm(O, V2, VerboseAsm, MAI);
389 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
390 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
392 // REG REG 0,SH_OPC - e.g. R5, ROR R3
393 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
394 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
395 const MachineOperand &MO1 = MI->getOperand(Op);
396 const MachineOperand &MO2 = MI->getOperand(Op+1);
397 const MachineOperand &MO3 = MI->getOperand(Op+2);
399 O << getRegisterName(MO1.getReg());
401 // Print the shift opc.
403 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
407 O << getRegisterName(MO2.getReg());
408 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
410 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
414 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
415 const MachineOperand &MO1 = MI->getOperand(Op);
416 const MachineOperand &MO2 = MI->getOperand(Op+1);
417 const MachineOperand &MO3 = MI->getOperand(Op+2);
419 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
420 printOperand(MI, Op);
424 O << "[" << getRegisterName(MO1.getReg());
427 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
429 << (char)ARM_AM::getAM2Op(MO3.getImm())
430 << ARM_AM::getAM2Offset(MO3.getImm());
436 << (char)ARM_AM::getAM2Op(MO3.getImm())
437 << getRegisterName(MO2.getReg());
439 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
441 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
446 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
447 const MachineOperand &MO1 = MI->getOperand(Op);
448 const MachineOperand &MO2 = MI->getOperand(Op+1);
451 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
452 assert(ImmOffs && "Malformed indexed load / store!");
454 << (char)ARM_AM::getAM2Op(MO2.getImm())
459 O << (char)ARM_AM::getAM2Op(MO2.getImm())
460 << getRegisterName(MO1.getReg());
462 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
464 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
468 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
469 const MachineOperand &MO1 = MI->getOperand(Op);
470 const MachineOperand &MO2 = MI->getOperand(Op+1);
471 const MachineOperand &MO3 = MI->getOperand(Op+2);
473 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
474 O << "[" << getRegisterName(MO1.getReg());
478 << (char)ARM_AM::getAM3Op(MO3.getImm())
479 << getRegisterName(MO2.getReg())
484 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
486 << (char)ARM_AM::getAM3Op(MO3.getImm())
491 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
492 const MachineOperand &MO1 = MI->getOperand(Op);
493 const MachineOperand &MO2 = MI->getOperand(Op+1);
496 O << (char)ARM_AM::getAM3Op(MO2.getImm())
497 << getRegisterName(MO1.getReg());
501 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
502 assert(ImmOffs && "Malformed indexed load / store!");
504 << (char)ARM_AM::getAM3Op(MO2.getImm())
508 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
509 const char *Modifier) {
510 const MachineOperand &MO1 = MI->getOperand(Op);
511 const MachineOperand &MO2 = MI->getOperand(Op+1);
512 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
513 if (Modifier && strcmp(Modifier, "submode") == 0) {
514 if (MO1.getReg() == ARM::SP) {
516 bool isLDM = (MI->getOpcode() == ARM::LDM ||
517 MI->getOpcode() == ARM::LDM_RET ||
518 MI->getOpcode() == ARM::t2LDM ||
519 MI->getOpcode() == ARM::t2LDM_RET);
520 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
522 O << ARM_AM::getAMSubModeStr(Mode);
523 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
524 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
525 if (Mode == ARM_AM::ia)
528 printOperand(MI, Op);
529 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
534 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
535 const char *Modifier) {
536 const MachineOperand &MO1 = MI->getOperand(Op);
537 const MachineOperand &MO2 = MI->getOperand(Op+1);
539 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
540 printOperand(MI, Op);
544 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
546 if (Modifier && strcmp(Modifier, "submode") == 0) {
547 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
548 O << ARM_AM::getAMSubModeStr(Mode);
550 } else if (Modifier && strcmp(Modifier, "base") == 0) {
551 // Used for FSTM{D|S} and LSTM{D|S} operations.
552 O << getRegisterName(MO1.getReg());
553 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
558 O << "[" << getRegisterName(MO1.getReg());
560 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
562 << (char)ARM_AM::getAM5Op(MO2.getImm())
568 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
569 const MachineOperand &MO1 = MI->getOperand(Op);
570 const MachineOperand &MO2 = MI->getOperand(Op+1);
571 const MachineOperand &MO3 = MI->getOperand(Op+2);
572 const MachineOperand &MO4 = MI->getOperand(Op+3);
574 O << "[" << getRegisterName(MO1.getReg());
576 // FIXME: Both darwin as and GNU as violate ARM docs here.
577 O << ", :" << MO4.getImm();
581 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
582 if (MO2.getReg() == 0)
585 O << ", " << getRegisterName(MO2.getReg());
589 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
590 const char *Modifier) {
591 if (Modifier && strcmp(Modifier, "label") == 0) {
592 printPCLabel(MI, Op+1);
596 const MachineOperand &MO1 = MI->getOperand(Op);
597 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
598 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
602 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
603 const MachineOperand &MO = MI->getOperand(Op);
604 uint32_t v = ~MO.getImm();
605 int32_t lsb = CountTrailingZeros_32(v);
606 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
607 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
608 O << "#" << lsb << ", #" << width;
611 //===--------------------------------------------------------------------===//
613 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
614 O << "#" << MI->getOperand(Op).getImm() * 4;
618 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
619 // (3 - the number of trailing zeros) is the number of then / else.
620 unsigned Mask = MI->getOperand(Op).getImm();
621 unsigned NumTZ = CountTrailingZeros_32(Mask);
622 assert(NumTZ <= 3 && "Invalid IT mask!");
623 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
624 bool T = (Mask & (1 << Pos)) == 0;
633 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
634 const MachineOperand &MO1 = MI->getOperand(Op);
635 const MachineOperand &MO2 = MI->getOperand(Op+1);
636 O << "[" << getRegisterName(MO1.getReg());
637 O << ", " << getRegisterName(MO2.getReg()) << "]";
641 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
643 const MachineOperand &MO1 = MI->getOperand(Op);
644 const MachineOperand &MO2 = MI->getOperand(Op+1);
645 const MachineOperand &MO3 = MI->getOperand(Op+2);
647 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
648 printOperand(MI, Op);
652 O << "[" << getRegisterName(MO1.getReg());
654 O << ", " << getRegisterName(MO3.getReg());
655 else if (unsigned ImmOffs = MO2.getImm())
656 O << ", #+" << ImmOffs * Scale;
661 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
662 printThumbAddrModeRI5Operand(MI, Op, 1);
665 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
666 printThumbAddrModeRI5Operand(MI, Op, 2);
669 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
670 printThumbAddrModeRI5Operand(MI, Op, 4);
673 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
674 const MachineOperand &MO1 = MI->getOperand(Op);
675 const MachineOperand &MO2 = MI->getOperand(Op+1);
676 O << "[" << getRegisterName(MO1.getReg());
677 if (unsigned ImmOffs = MO2.getImm())
678 O << ", #+" << ImmOffs*4;
682 //===--------------------------------------------------------------------===//
684 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
685 // register with shift forms.
687 // REG IMM, SH_OPC - e.g. R5, LSL #3
688 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
689 const MachineOperand &MO1 = MI->getOperand(OpNum);
690 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
692 unsigned Reg = MO1.getReg();
693 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
694 O << getRegisterName(Reg);
696 // Print the shift opc.
698 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
701 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
702 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
705 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
707 const MachineOperand &MO1 = MI->getOperand(OpNum);
708 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
710 O << "[" << getRegisterName(MO1.getReg());
712 unsigned OffImm = MO2.getImm();
713 if (OffImm) // Don't print +0.
714 O << ", #+" << OffImm;
718 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
720 const MachineOperand &MO1 = MI->getOperand(OpNum);
721 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
723 O << "[" << getRegisterName(MO1.getReg());
725 int32_t OffImm = (int32_t)MO2.getImm();
728 O << ", #-" << -OffImm;
730 O << ", #+" << OffImm;
734 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
736 const MachineOperand &MO1 = MI->getOperand(OpNum);
737 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
739 O << "[" << getRegisterName(MO1.getReg());
741 int32_t OffImm = (int32_t)MO2.getImm() / 4;
744 O << ", #-" << -OffImm * 4;
746 O << ", #+" << OffImm * 4;
750 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
752 const MachineOperand &MO1 = MI->getOperand(OpNum);
753 int32_t OffImm = (int32_t)MO1.getImm();
756 O << "#-" << -OffImm;
761 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
763 const MachineOperand &MO1 = MI->getOperand(OpNum);
764 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
765 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
767 O << "[" << getRegisterName(MO1.getReg());
769 assert(MO2.getReg() && "Invalid so_reg load / store address!");
770 O << ", " << getRegisterName(MO2.getReg());
772 unsigned ShAmt = MO3.getImm();
774 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
775 O << ", lsl #" << ShAmt;
781 //===--------------------------------------------------------------------===//
783 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
784 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
786 O << ARMCondCodeToString(CC);
789 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
790 unsigned Reg = MI->getOperand(OpNum).getReg();
792 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
797 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
798 int Id = (int)MI->getOperand(OpNum).getImm();
799 O << MAI->getPrivateGlobalPrefix()
800 << "PC" << getFunctionNumber() << "_" << Id;
803 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
805 // Always skip the first operand, it's the optional (and implicit writeback).
806 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
807 if (MI->getOperand(i).isImplicit())
809 if ((int)i != OpNum+1) O << ", ";
815 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
816 const char *Modifier) {
817 assert(Modifier && "This operand only works with a modifier!");
818 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
820 if (!strcmp(Modifier, "label")) {
821 unsigned ID = MI->getOperand(OpNum).getImm();
822 OutStreamer.EmitLabel(GetCPISymbol(ID));
824 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
825 unsigned CPI = MI->getOperand(OpNum).getIndex();
827 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
829 if (MCPE.isMachineConstantPoolEntry()) {
830 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
832 EmitGlobalConstant(MCPE.Val.ConstVal);
837 MCSymbol *ARMAsmPrinter::
838 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
839 const MachineBasicBlock *MBB) const {
840 SmallString<60> Name;
841 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
842 << getFunctionNumber() << '_' << uid << '_' << uid2
843 << "_set_" << MBB->getNumber();
844 return OutContext.GetOrCreateSymbol(Name.str());
847 MCSymbol *ARMAsmPrinter::
848 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
849 SmallString<60> Name;
850 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
851 << getFunctionNumber() << '_' << uid << '_' << uid2;
852 return OutContext.GetOrCreateSymbol(Name.str());
855 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
856 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
858 const MachineOperand &MO1 = MI->getOperand(OpNum);
859 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
861 unsigned JTI = MO1.getIndex();
862 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
863 OutStreamer.EmitLabel(JTISymbol);
865 const char *JTEntryDirective = MAI->getData32bitsDirective();
867 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
868 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
869 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
870 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
871 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
872 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
873 MachineBasicBlock *MBB = JTBBs[i];
874 bool isNew = JTSets.insert(MBB);
876 if (UseSet && isNew) {
878 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
879 << *MBB->getSymbol(OutContext) << '-' << *JTISymbol << '\n';
882 O << JTEntryDirective << ' ';
884 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
885 else if (TM.getRelocationModel() == Reloc::PIC_)
886 O << *MBB->getSymbol(OutContext) << '-' << *JTISymbol;
888 O << *MBB->getSymbol(OutContext);
895 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
896 const MachineOperand &MO1 = MI->getOperand(OpNum);
897 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
898 unsigned JTI = MO1.getIndex();
900 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
901 OutStreamer.EmitLabel(JTISymbol);
903 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
904 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
905 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
906 bool ByteOffset = false, HalfWordOffset = false;
907 if (MI->getOpcode() == ARM::t2TBB)
909 else if (MI->getOpcode() == ARM::t2TBH)
910 HalfWordOffset = true;
912 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
913 MachineBasicBlock *MBB = JTBBs[i];
915 O << MAI->getData8bitsDirective();
916 else if (HalfWordOffset)
917 O << MAI->getData16bitsDirective();
919 if (ByteOffset || HalfWordOffset)
920 O << '(' << *MBB->getSymbol(OutContext) << "-" << *JTISymbol << ")/2";
922 O << "\tb.w " << *MBB->getSymbol(OutContext);
928 // Make sure the instruction that follows TBB is 2-byte aligned.
929 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
930 if (ByteOffset && (JTBBs.size() & 1)) {
936 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
937 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
938 if (MI->getOpcode() == ARM::t2TBH)
943 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
944 O << MI->getOperand(OpNum).getImm();
947 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
948 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
949 O << '#' << FP->getValueAPF().convertToFloat();
951 O.PadToColumn(MAI->getCommentColumn());
952 O << MAI->getCommentString() << ' ';
953 WriteAsOperand(O, FP, /*PrintType=*/false);
957 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
958 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
959 O << '#' << FP->getValueAPF().convertToDouble();
961 O.PadToColumn(MAI->getCommentColumn());
962 O << MAI->getCommentString() << ' ';
963 WriteAsOperand(O, FP, /*PrintType=*/false);
967 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
968 unsigned AsmVariant, const char *ExtraCode){
969 // Does this asm operand have a single letter operand modifier?
970 if (ExtraCode && ExtraCode[0]) {
971 if (ExtraCode[1] != 0) return true; // Unknown modifier.
973 switch (ExtraCode[0]) {
974 default: return true; // Unknown modifier.
975 case 'a': // Print as a memory address.
976 if (MI->getOperand(OpNum).isReg()) {
977 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
981 case 'c': // Don't print "#" before an immediate operand.
982 if (!MI->getOperand(OpNum).isImm())
984 printNoHashImmediate(MI, OpNum);
986 case 'P': // Print a VFP double precision register.
987 case 'q': // Print a NEON quad precision register.
988 printOperand(MI, OpNum);
991 if (TM.getTargetData()->isLittleEndian())
995 if (TM.getTargetData()->isBigEndian())
998 case 'H': // Write second word of DI / DF reference.
999 // Verify that this operand has two consecutive registers.
1000 if (!MI->getOperand(OpNum).isReg() ||
1001 OpNum+1 == MI->getNumOperands() ||
1002 !MI->getOperand(OpNum+1).isReg())
1004 ++OpNum; // Return the high-part.
1008 printOperand(MI, OpNum);
1012 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1013 unsigned OpNum, unsigned AsmVariant,
1014 const char *ExtraCode) {
1015 if (ExtraCode && ExtraCode[0])
1016 return true; // Unknown modifier.
1018 const MachineOperand &MO = MI->getOperand(OpNum);
1019 assert(MO.isReg() && "unexpected inline asm memory operand");
1020 O << "[" << getRegisterName(MO.getReg()) << "]";
1024 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1026 printInstructionThroughMCStreamer(MI);
1028 int Opc = MI->getOpcode();
1029 if (Opc == ARM::CONSTPOOL_ENTRY)
1032 printInstruction(MI);
1033 OutStreamer.AddBlankLine();
1037 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1038 if (Subtarget->isTargetDarwin()) {
1039 Reloc::Model RelocM = TM.getRelocationModel();
1040 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1041 // Declare all the text sections up front (before the DWARF sections
1042 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1043 // them together at the beginning of the object file. This helps
1044 // avoid out-of-range branches that are due a fundamental limitation of
1045 // the way symbol offsets are encoded with the current Darwin ARM
1047 TargetLoweringObjectFileMachO &TLOFMacho =
1048 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1049 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1050 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1051 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1052 if (RelocM == Reloc::DynamicNoPIC) {
1053 const MCSection *sect =
1054 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1055 MCSectionMachO::S_SYMBOL_STUBS,
1056 12, SectionKind::getText());
1057 OutStreamer.SwitchSection(sect);
1059 const MCSection *sect =
1060 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1061 MCSectionMachO::S_SYMBOL_STUBS,
1062 16, SectionKind::getText());
1063 OutStreamer.SwitchSection(sect);
1068 // Use unified assembler syntax.
1069 O << "\t.syntax unified\n";
1071 // Emit ARM Build Attributes
1072 if (Subtarget->isTargetELF()) {
1074 std::string CPUString = Subtarget->getCPUString();
1075 if (CPUString != "generic")
1076 O << "\t.cpu " << CPUString << '\n';
1078 // FIXME: Emit FPU type
1079 if (Subtarget->hasVFP2())
1080 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1082 // Signal various FP modes.
1084 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1085 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1087 if (FiniteOnlyFPMath())
1088 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1090 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1092 // 8-bytes alignment stuff.
1093 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1094 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1096 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1097 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1098 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1099 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1101 // FIXME: Should we signal R9 usage?
1106 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1107 if (Subtarget->isTargetDarwin()) {
1108 // All darwin targets use mach-o.
1109 TargetLoweringObjectFileMachO &TLOFMacho =
1110 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1111 MachineModuleInfoMachO &MMIMacho =
1112 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1116 // Output non-lazy-pointers for external and common global variables.
1117 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1119 if (!Stubs.empty()) {
1120 // Switch with ".non_lazy_symbol_pointer" directive.
1121 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1123 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1124 O << *Stubs[i].first << ":\n\t.indirect_symbol ";
1125 O << *Stubs[i].second << "\n\t.long\t0\n";
1129 Stubs = MMIMacho.GetHiddenGVStubList();
1130 if (!Stubs.empty()) {
1131 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1133 for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
1134 O << *Stubs[i].first << ":\n\t.long " << *Stubs[i].second << "\n";
1137 // Funny Darwin hack: This flag tells the linker that no global symbols
1138 // contain code that falls through to other global symbols (e.g. the obvious
1139 // implementation of multiple entry points). If this doesn't occur, the
1140 // linker can safely perform dead code stripping. Since LLVM never
1141 // generates code that does this, it is always safe to set.
1142 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1146 //===----------------------------------------------------------------------===//
1148 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1149 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1150 switch (MI->getOpcode()) {
1151 case ARM::t2MOVi32imm:
1152 assert(0 && "Should be lowered by thumb2it pass");
1154 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1155 // This is a pseudo op for a label + instruction sequence, which looks like:
1158 // This adds the address of LPC0 to r0.
1161 // FIXME: MOVE TO SHARED PLACE.
1162 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1163 const char *Prefix = MAI->getPrivateGlobalPrefix();
1164 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1165 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1166 OutStreamer.EmitLabel(Label);
1169 // Form and emit tha dd.
1171 AddInst.setOpcode(ARM::ADDrr);
1172 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1173 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1174 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1175 OutStreamer.EmitInstruction(AddInst);
1178 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1179 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1180 /// in the function. The first operand is the ID# for this instruction, the
1181 /// second is the index into the MachineConstantPool that this is, the third
1182 /// is the size in bytes of this constant pool entry.
1183 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1184 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1187 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1189 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1190 if (MCPE.isMachineConstantPoolEntry())
1191 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1193 EmitGlobalConstant(MCPE.Val.ConstVal);
1197 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1198 // This is a hack that lowers as a two instruction sequence.
1199 unsigned DstReg = MI->getOperand(0).getReg();
1200 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1202 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1203 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1207 TmpInst.setOpcode(ARM::MOVi);
1208 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1209 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1212 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1213 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1215 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1216 OutStreamer.EmitInstruction(TmpInst);
1221 TmpInst.setOpcode(ARM::ORRri);
1222 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1223 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1224 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1226 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1227 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1229 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1230 OutStreamer.EmitInstruction(TmpInst);
1234 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1235 // This is a hack that lowers as a two instruction sequence.
1236 unsigned DstReg = MI->getOperand(0).getReg();
1237 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1241 TmpInst.setOpcode(ARM::MOVi16);
1242 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1243 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1246 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1247 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1249 OutStreamer.EmitInstruction(TmpInst);
1254 TmpInst.setOpcode(ARM::MOVTi16);
1255 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1256 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1257 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1260 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1261 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1263 OutStreamer.EmitInstruction(TmpInst);
1271 MCInstLowering.Lower(MI, TmpInst);
1272 OutStreamer.EmitInstruction(TmpInst);
1275 //===----------------------------------------------------------------------===//
1276 // Target Registry Stuff
1277 //===----------------------------------------------------------------------===//
1279 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1280 unsigned SyntaxVariant,
1281 const MCAsmInfo &MAI,
1283 if (SyntaxVariant == 0)
1284 return new ARMInstPrinter(O, MAI, false);
1288 // Force static initialization.
1289 extern "C" void LLVMInitializeARMAsmPrinter() {
1290 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1291 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1293 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1294 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);