1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectFileInfo.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
61 typedef SmallVector<SMLoc, 4> Locs;
66 Locs PersonalityIndexLocs;
71 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
73 bool hasFnStart() const { return !FnStartLocs.empty(); }
74 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76 bool hasPersonality() const {
77 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
80 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
86 void saveFPReg(int Reg) { FPReg = Reg; }
87 int getFPReg() const { return FPReg; }
89 void emitFnStartLocNotes() const {
90 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
92 Parser.Note(*FI, ".fnstart was specified here");
94 void emitCantUnwindLocNotes() const {
95 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96 UE = CantUnwindLocs.end(); UI != UE; ++UI)
97 Parser.Note(*UI, ".cantunwind was specified here");
99 void emitHandlerDataLocNotes() const {
100 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101 HE = HandlerDataLocs.end(); HI != HE; ++HI)
102 Parser.Note(*HI, ".handlerdata was specified here");
104 void emitPersonalityLocNotes() const {
105 for (Locs::const_iterator PI = PersonalityLocs.begin(),
106 PE = PersonalityLocs.end(),
107 PII = PersonalityIndexLocs.begin(),
108 PIE = PersonalityIndexLocs.end();
109 PI != PE || PII != PIE;) {
110 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111 Parser.Note(*PI++, ".personality was specified here");
112 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113 Parser.Note(*PII++, ".personalityindex was specified here");
115 llvm_unreachable(".personality and .personalityindex cannot be "
116 "at the same location");
121 FnStartLocs = Locs();
122 CantUnwindLocs = Locs();
123 PersonalityLocs = Locs();
124 HandlerDataLocs = Locs();
125 PersonalityIndexLocs = Locs();
130 class ARMAsmParser : public MCTargetAsmParser {
131 MCSubtargetInfo &STI;
132 const MCInstrInfo &MII;
133 const MCRegisterInfo *MRI;
136 ARMTargetStreamer &getTargetStreamer() {
137 assert(getParser().getStreamer().getTargetStreamer() &&
138 "do not have a target streamer");
139 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
140 return static_cast<ARMTargetStreamer &>(TS);
143 // Map of register aliases registers via the .req directive.
144 StringMap<unsigned> RegisterReqs;
146 bool NextSymbolIsThumb;
149 ARMCC::CondCodes Cond; // Condition for IT block.
150 unsigned Mask:4; // Condition mask for instructions.
151 // Starting at first 1 (from lsb).
152 // '1' condition as indicated in IT.
153 // '0' inverse of condition (else).
154 // Count of instructions in IT block is
155 // 4 - trailingzeroes(mask)
157 bool FirstCond; // Explicit flag for when we're parsing the
158 // First instruction in the IT block. It's
159 // implied in the mask, so needs special
162 unsigned CurPosition; // Current position in parsing of IT
163 // block. In range [0,3]. Initialized
164 // according to count of instructions in block.
165 // ~0U if no active IT block.
167 bool inITBlock() { return ITState.CurPosition != ~0U;}
168 void forwardITPosition() {
169 if (!inITBlock()) return;
170 // Move to the next instruction in the IT block, if there is one. If not,
171 // mark the block as done.
172 unsigned TZ = countTrailingZeros(ITState.Mask);
173 if (++ITState.CurPosition == 5 - TZ)
174 ITState.CurPosition = ~0U; // Done with the IT block after this.
177 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
178 return getParser().Note(L, Msg, Ranges);
180 bool Warning(SMLoc L, const Twine &Msg,
181 ArrayRef<SMRange> Ranges = None) {
182 return getParser().Warning(L, Msg, Ranges);
184 bool Error(SMLoc L, const Twine &Msg,
185 ArrayRef<SMRange> Ranges = None) {
186 return getParser().Error(L, Msg, Ranges);
189 int tryParseRegister();
190 bool tryParseRegisterWithWriteBack(OperandVector &);
191 int tryParseShiftRegister(OperandVector &);
192 bool parseRegisterList(OperandVector &);
193 bool parseMemory(OperandVector &);
194 bool parseOperand(OperandVector &, StringRef Mnemonic);
195 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
196 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
197 unsigned &ShiftAmount);
198 bool parseLiteralValues(unsigned Size, SMLoc L);
199 bool parseDirectiveThumb(SMLoc L);
200 bool parseDirectiveARM(SMLoc L);
201 bool parseDirectiveThumbFunc(SMLoc L);
202 bool parseDirectiveCode(SMLoc L);
203 bool parseDirectiveSyntax(SMLoc L);
204 bool parseDirectiveReq(StringRef Name, SMLoc L);
205 bool parseDirectiveUnreq(SMLoc L);
206 bool parseDirectiveArch(SMLoc L);
207 bool parseDirectiveEabiAttr(SMLoc L);
208 bool parseDirectiveCPU(SMLoc L);
209 bool parseDirectiveFPU(SMLoc L);
210 bool parseDirectiveFnStart(SMLoc L);
211 bool parseDirectiveFnEnd(SMLoc L);
212 bool parseDirectiveCantUnwind(SMLoc L);
213 bool parseDirectivePersonality(SMLoc L);
214 bool parseDirectiveHandlerData(SMLoc L);
215 bool parseDirectiveSetFP(SMLoc L);
216 bool parseDirectivePad(SMLoc L);
217 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
218 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
219 bool parseDirectiveLtorg(SMLoc L);
220 bool parseDirectiveEven(SMLoc L);
221 bool parseDirectivePersonalityIndex(SMLoc L);
222 bool parseDirectiveUnwindRaw(SMLoc L);
223 bool parseDirectiveTLSDescSeq(SMLoc L);
224 bool parseDirectiveMovSP(SMLoc L);
225 bool parseDirectiveObjectArch(SMLoc L);
226 bool parseDirectiveArchExtension(SMLoc L);
227 bool parseDirectiveAlign(SMLoc L);
228 bool parseDirectiveThumbSet(SMLoc L);
230 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
231 bool &CarrySetting, unsigned &ProcessorIMod,
233 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
234 bool &CanAcceptCarrySet,
235 bool &CanAcceptPredicationCode);
237 bool isThumb() const {
238 // FIXME: Can tablegen auto-generate this?
239 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
241 bool isThumbOne() const {
242 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
244 bool isThumbTwo() const {
245 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
247 bool hasThumb() const {
248 return STI.getFeatureBits() & ARM::HasV4TOps;
250 bool hasV6Ops() const {
251 return STI.getFeatureBits() & ARM::HasV6Ops;
253 bool hasV6MOps() const {
254 return STI.getFeatureBits() & ARM::HasV6MOps;
256 bool hasV7Ops() const {
257 return STI.getFeatureBits() & ARM::HasV7Ops;
259 bool hasV8Ops() const {
260 return STI.getFeatureBits() & ARM::HasV8Ops;
262 bool hasARM() const {
263 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
265 bool hasThumb2DSP() const {
266 return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
268 bool hasD16() const {
269 return STI.getFeatureBits() & ARM::FeatureD16;
273 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
274 setAvailableFeatures(FB);
276 bool isMClass() const {
277 return STI.getFeatureBits() & ARM::FeatureMClass;
280 /// @name Auto-generated Match Functions
283 #define GET_ASSEMBLER_HEADER
284 #include "ARMGenAsmMatcher.inc"
288 OperandMatchResultTy parseITCondCode(OperandVector &);
289 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
290 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
291 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
292 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
293 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
294 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
295 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
296 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
297 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
299 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
300 return parsePKHImm(O, "lsl", 0, 31);
302 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
303 return parsePKHImm(O, "asr", 1, 32);
305 OperandMatchResultTy parseSetEndImm(OperandVector &);
306 OperandMatchResultTy parseShifterImm(OperandVector &);
307 OperandMatchResultTy parseRotImm(OperandVector &);
308 OperandMatchResultTy parseModImm(OperandVector &);
309 OperandMatchResultTy parseBitfield(OperandVector &);
310 OperandMatchResultTy parsePostIdxReg(OperandVector &);
311 OperandMatchResultTy parseAM3Offset(OperandVector &);
312 OperandMatchResultTy parseFPImm(OperandVector &);
313 OperandMatchResultTy parseVectorList(OperandVector &);
314 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
317 // Asm Match Converter Methods
318 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
319 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
321 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
322 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
323 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
324 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
327 enum ARMMatchResultTy {
328 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
329 Match_RequiresNotITBlock,
331 Match_RequiresThumb2,
332 #define GET_OPERAND_DIAGNOSTIC_TYPES
333 #include "ARMGenAsmMatcher.inc"
337 ARMAsmParser(MCSubtargetInfo & _STI, MCAsmParser & _Parser,
338 const MCInstrInfo &MII, const MCTargetOptions &Options)
339 : MCTargetAsmParser(), STI(_STI), MII(MII), UC(_Parser) {
340 MCAsmParserExtension::Initialize(_Parser);
342 // Cache the MCRegisterInfo.
343 MRI = getContext().getRegisterInfo();
345 // Initialize the set of available features.
346 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
348 // Not in an ITBlock to start with.
349 ITState.CurPosition = ~0U;
351 NextSymbolIsThumb = false;
354 // Implementation of the MCTargetAsmParser interface:
355 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
356 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
357 SMLoc NameLoc, OperandVector &Operands) override;
358 bool ParseDirective(AsmToken DirectiveID) override;
360 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
361 unsigned Kind) override;
362 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
364 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
365 OperandVector &Operands, MCStreamer &Out,
367 bool MatchingInlineAsm) override;
368 void onLabelParsed(MCSymbol *Symbol) override;
370 } // end anonymous namespace
374 /// ARMOperand - Instances of this class represent a parsed ARM machine
376 class ARMOperand : public MCParsedAsmOperand {
386 k_InstSyncBarrierOpt,
398 k_VectorListAllLanes,
405 k_BitfieldDescriptor,
409 SMLoc StartLoc, EndLoc, AlignmentLoc;
410 SmallVector<unsigned, 8> Registers;
413 ARMCC::CondCodes Val;
420 struct CoprocOptionOp {
433 ARM_ISB::InstSyncBOpt Val;
437 ARM_PROC::IFlags Val;
457 // A vector register list is a sequential list of 1 to 4 registers.
458 struct VectorListOp {
465 struct VectorIndexOp {
473 /// Combined record for all forms of ARM address expressions.
476 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
478 const MCConstantExpr *OffsetImm; // Offset immediate value
479 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
480 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
481 unsigned ShiftImm; // shift for OffsetReg.
482 unsigned Alignment; // 0 = no alignment specified
483 // n = alignment in bytes (2, 4, 8, 16, or 32)
484 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
487 struct PostIdxRegOp {
490 ARM_AM::ShiftOpc ShiftTy;
494 struct ShifterImmOp {
499 struct RegShiftedRegOp {
500 ARM_AM::ShiftOpc ShiftTy;
506 struct RegShiftedImmOp {
507 ARM_AM::ShiftOpc ShiftTy;
529 struct CoprocOptionOp CoprocOption;
530 struct MBOptOp MBOpt;
531 struct ISBOptOp ISBOpt;
532 struct ITMaskOp ITMask;
533 struct IFlagsOp IFlags;
534 struct MMaskOp MMask;
535 struct BankedRegOp BankedReg;
538 struct VectorListOp VectorList;
539 struct VectorIndexOp VectorIndex;
541 struct MemoryOp Memory;
542 struct PostIdxRegOp PostIdxReg;
543 struct ShifterImmOp ShifterImm;
544 struct RegShiftedRegOp RegShiftedReg;
545 struct RegShiftedImmOp RegShiftedImm;
546 struct RotImmOp RotImm;
547 struct ModImmOp ModImm;
548 struct BitfieldOp Bitfield;
552 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
553 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
555 StartLoc = o.StartLoc;
572 case k_DPRRegisterList:
573 case k_SPRRegisterList:
574 Registers = o.Registers;
577 case k_VectorListAllLanes:
578 case k_VectorListIndexed:
579 VectorList = o.VectorList;
586 CoprocOption = o.CoprocOption;
591 case k_MemBarrierOpt:
594 case k_InstSyncBarrierOpt:
599 case k_PostIndexRegister:
600 PostIdxReg = o.PostIdxReg;
606 BankedReg = o.BankedReg;
611 case k_ShifterImmediate:
612 ShifterImm = o.ShifterImm;
614 case k_ShiftedRegister:
615 RegShiftedReg = o.RegShiftedReg;
617 case k_ShiftedImmediate:
618 RegShiftedImm = o.RegShiftedImm;
620 case k_RotateImmediate:
623 case k_ModifiedImmediate:
626 case k_BitfieldDescriptor:
627 Bitfield = o.Bitfield;
630 VectorIndex = o.VectorIndex;
635 /// getStartLoc - Get the location of the first token of this operand.
636 SMLoc getStartLoc() const override { return StartLoc; }
637 /// getEndLoc - Get the location of the last token of this operand.
638 SMLoc getEndLoc() const override { return EndLoc; }
639 /// getLocRange - Get the range between the first and last token of this
641 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
643 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
644 SMLoc getAlignmentLoc() const {
645 assert(Kind == k_Memory && "Invalid access!");
649 ARMCC::CondCodes getCondCode() const {
650 assert(Kind == k_CondCode && "Invalid access!");
654 unsigned getCoproc() const {
655 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
659 StringRef getToken() const {
660 assert(Kind == k_Token && "Invalid access!");
661 return StringRef(Tok.Data, Tok.Length);
664 unsigned getReg() const override {
665 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
669 const SmallVectorImpl<unsigned> &getRegList() const {
670 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
671 Kind == k_SPRRegisterList) && "Invalid access!");
675 const MCExpr *getImm() const {
676 assert(isImm() && "Invalid access!");
680 unsigned getVectorIndex() const {
681 assert(Kind == k_VectorIndex && "Invalid access!");
682 return VectorIndex.Val;
685 ARM_MB::MemBOpt getMemBarrierOpt() const {
686 assert(Kind == k_MemBarrierOpt && "Invalid access!");
690 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
691 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
695 ARM_PROC::IFlags getProcIFlags() const {
696 assert(Kind == k_ProcIFlags && "Invalid access!");
700 unsigned getMSRMask() const {
701 assert(Kind == k_MSRMask && "Invalid access!");
705 unsigned getBankedReg() const {
706 assert(Kind == k_BankedReg && "Invalid access!");
707 return BankedReg.Val;
710 bool isCoprocNum() const { return Kind == k_CoprocNum; }
711 bool isCoprocReg() const { return Kind == k_CoprocReg; }
712 bool isCoprocOption() const { return Kind == k_CoprocOption; }
713 bool isCondCode() const { return Kind == k_CondCode; }
714 bool isCCOut() const { return Kind == k_CCOut; }
715 bool isITMask() const { return Kind == k_ITCondMask; }
716 bool isITCondCode() const { return Kind == k_CondCode; }
717 bool isImm() const override { return Kind == k_Immediate; }
718 // checks whether this operand is an unsigned offset which fits is a field
719 // of specified width and scaled by a specific number of bits
720 template<unsigned width, unsigned scale>
721 bool isUnsignedOffset() const {
722 if (!isImm()) return false;
723 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
724 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
725 int64_t Val = CE->getValue();
726 int64_t Align = 1LL << scale;
727 int64_t Max = Align * ((1LL << width) - 1);
728 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
732 // checks whether this operand is an signed offset which fits is a field
733 // of specified width and scaled by a specific number of bits
734 template<unsigned width, unsigned scale>
735 bool isSignedOffset() const {
736 if (!isImm()) return false;
737 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
738 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
739 int64_t Val = CE->getValue();
740 int64_t Align = 1LL << scale;
741 int64_t Max = Align * ((1LL << (width-1)) - 1);
742 int64_t Min = -Align * (1LL << (width-1));
743 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
748 // checks whether this operand is a memory operand computed as an offset
749 // applied to PC. the offset may have 8 bits of magnitude and is represented
750 // with two bits of shift. textually it may be either [pc, #imm], #imm or
751 // relocable expression...
752 bool isThumbMemPC() const {
755 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
756 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
757 if (!CE) return false;
758 Val = CE->getValue();
761 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
762 if(Memory.BaseRegNum != ARM::PC) return false;
763 Val = Memory.OffsetImm->getValue();
766 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
768 bool isFPImm() const {
769 if (!isImm()) return false;
770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771 if (!CE) return false;
772 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
775 bool isFBits16() const {
776 if (!isImm()) return false;
777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778 if (!CE) return false;
779 int64_t Value = CE->getValue();
780 return Value >= 0 && Value <= 16;
782 bool isFBits32() const {
783 if (!isImm()) return false;
784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785 if (!CE) return false;
786 int64_t Value = CE->getValue();
787 return Value >= 1 && Value <= 32;
789 bool isImm8s4() const {
790 if (!isImm()) return false;
791 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
792 if (!CE) return false;
793 int64_t Value = CE->getValue();
794 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
796 bool isImm0_1020s4() const {
797 if (!isImm()) return false;
798 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
799 if (!CE) return false;
800 int64_t Value = CE->getValue();
801 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
803 bool isImm0_508s4() const {
804 if (!isImm()) return false;
805 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
806 if (!CE) return false;
807 int64_t Value = CE->getValue();
808 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
810 bool isImm0_508s4Neg() const {
811 if (!isImm()) return false;
812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
813 if (!CE) return false;
814 int64_t Value = -CE->getValue();
815 // explicitly exclude zero. we want that to use the normal 0_508 version.
816 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
818 bool isImm0_239() const {
819 if (!isImm()) return false;
820 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
821 if (!CE) return false;
822 int64_t Value = CE->getValue();
823 return Value >= 0 && Value < 240;
825 bool isImm0_255() const {
826 if (!isImm()) return false;
827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
828 if (!CE) return false;
829 int64_t Value = CE->getValue();
830 return Value >= 0 && Value < 256;
832 bool isImm0_4095() const {
833 if (!isImm()) return false;
834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
835 if (!CE) return false;
836 int64_t Value = CE->getValue();
837 return Value >= 0 && Value < 4096;
839 bool isImm0_4095Neg() const {
840 if (!isImm()) return false;
841 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
842 if (!CE) return false;
843 int64_t Value = -CE->getValue();
844 return Value > 0 && Value < 4096;
846 bool isImm0_1() const {
847 if (!isImm()) return false;
848 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
849 if (!CE) return false;
850 int64_t Value = CE->getValue();
851 return Value >= 0 && Value < 2;
853 bool isImm0_3() const {
854 if (!isImm()) return false;
855 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
856 if (!CE) return false;
857 int64_t Value = CE->getValue();
858 return Value >= 0 && Value < 4;
860 bool isImm0_7() const {
861 if (!isImm()) return false;
862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
863 if (!CE) return false;
864 int64_t Value = CE->getValue();
865 return Value >= 0 && Value < 8;
867 bool isImm0_15() const {
868 if (!isImm()) return false;
869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
870 if (!CE) return false;
871 int64_t Value = CE->getValue();
872 return Value >= 0 && Value < 16;
874 bool isImm0_31() const {
875 if (!isImm()) return false;
876 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
877 if (!CE) return false;
878 int64_t Value = CE->getValue();
879 return Value >= 0 && Value < 32;
881 bool isImm0_63() const {
882 if (!isImm()) return false;
883 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
884 if (!CE) return false;
885 int64_t Value = CE->getValue();
886 return Value >= 0 && Value < 64;
888 bool isImm8() const {
889 if (!isImm()) return false;
890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
891 if (!CE) return false;
892 int64_t Value = CE->getValue();
895 bool isImm16() const {
896 if (!isImm()) return false;
897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
898 if (!CE) return false;
899 int64_t Value = CE->getValue();
902 bool isImm32() const {
903 if (!isImm()) return false;
904 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
905 if (!CE) return false;
906 int64_t Value = CE->getValue();
909 bool isShrImm8() const {
910 if (!isImm()) return false;
911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
912 if (!CE) return false;
913 int64_t Value = CE->getValue();
914 return Value > 0 && Value <= 8;
916 bool isShrImm16() const {
917 if (!isImm()) return false;
918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
919 if (!CE) return false;
920 int64_t Value = CE->getValue();
921 return Value > 0 && Value <= 16;
923 bool isShrImm32() const {
924 if (!isImm()) return false;
925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
926 if (!CE) return false;
927 int64_t Value = CE->getValue();
928 return Value > 0 && Value <= 32;
930 bool isShrImm64() const {
931 if (!isImm()) return false;
932 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933 if (!CE) return false;
934 int64_t Value = CE->getValue();
935 return Value > 0 && Value <= 64;
937 bool isImm1_7() const {
938 if (!isImm()) return false;
939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940 if (!CE) return false;
941 int64_t Value = CE->getValue();
942 return Value > 0 && Value < 8;
944 bool isImm1_15() const {
945 if (!isImm()) return false;
946 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
947 if (!CE) return false;
948 int64_t Value = CE->getValue();
949 return Value > 0 && Value < 16;
951 bool isImm1_31() const {
952 if (!isImm()) return false;
953 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
954 if (!CE) return false;
955 int64_t Value = CE->getValue();
956 return Value > 0 && Value < 32;
958 bool isImm1_16() const {
959 if (!isImm()) return false;
960 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
961 if (!CE) return false;
962 int64_t Value = CE->getValue();
963 return Value > 0 && Value < 17;
965 bool isImm1_32() const {
966 if (!isImm()) return false;
967 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
968 if (!CE) return false;
969 int64_t Value = CE->getValue();
970 return Value > 0 && Value < 33;
972 bool isImm0_32() const {
973 if (!isImm()) return false;
974 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
975 if (!CE) return false;
976 int64_t Value = CE->getValue();
977 return Value >= 0 && Value < 33;
979 bool isImm0_65535() const {
980 if (!isImm()) return false;
981 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
982 if (!CE) return false;
983 int64_t Value = CE->getValue();
984 return Value >= 0 && Value < 65536;
986 bool isImm256_65535Expr() const {
987 if (!isImm()) return false;
988 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
989 // If it's not a constant expression, it'll generate a fixup and be
991 if (!CE) return true;
992 int64_t Value = CE->getValue();
993 return Value >= 256 && Value < 65536;
995 bool isImm0_65535Expr() const {
996 if (!isImm()) return false;
997 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
998 // If it's not a constant expression, it'll generate a fixup and be
1000 if (!CE) return true;
1001 int64_t Value = CE->getValue();
1002 return Value >= 0 && Value < 65536;
1004 bool isImm24bit() const {
1005 if (!isImm()) return false;
1006 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1007 if (!CE) return false;
1008 int64_t Value = CE->getValue();
1009 return Value >= 0 && Value <= 0xffffff;
1011 bool isImmThumbSR() const {
1012 if (!isImm()) return false;
1013 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1014 if (!CE) return false;
1015 int64_t Value = CE->getValue();
1016 return Value > 0 && Value < 33;
1018 bool isPKHLSLImm() const {
1019 if (!isImm()) return false;
1020 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1021 if (!CE) return false;
1022 int64_t Value = CE->getValue();
1023 return Value >= 0 && Value < 32;
1025 bool isPKHASRImm() const {
1026 if (!isImm()) return false;
1027 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1028 if (!CE) return false;
1029 int64_t Value = CE->getValue();
1030 return Value > 0 && Value <= 32;
1032 bool isAdrLabel() const {
1033 // If we have an immediate that's not a constant, treat it as a label
1034 // reference needing a fixup. If it is a constant, but it can't fit
1035 // into shift immediate encoding, we reject it.
1036 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1037 else return (isARMSOImm() || isARMSOImmNeg());
1039 bool isARMSOImm() const {
1040 if (!isImm()) return false;
1041 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1042 if (!CE) return false;
1043 int64_t Value = CE->getValue();
1044 return ARM_AM::getSOImmVal(Value) != -1;
1046 bool isARMSOImmNot() const {
1047 if (!isImm()) return false;
1048 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1049 if (!CE) return false;
1050 int64_t Value = CE->getValue();
1051 return ARM_AM::getSOImmVal(~Value) != -1;
1053 bool isARMSOImmNeg() const {
1054 if (!isImm()) return false;
1055 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1056 if (!CE) return false;
1057 int64_t Value = CE->getValue();
1058 // Only use this when not representable as a plain so_imm.
1059 return ARM_AM::getSOImmVal(Value) == -1 &&
1060 ARM_AM::getSOImmVal(-Value) != -1;
1062 bool isT2SOImm() const {
1063 if (!isImm()) return false;
1064 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1065 if (!CE) return false;
1066 int64_t Value = CE->getValue();
1067 return ARM_AM::getT2SOImmVal(Value) != -1;
1069 bool isT2SOImmNot() const {
1070 if (!isImm()) return false;
1071 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1072 if (!CE) return false;
1073 int64_t Value = CE->getValue();
1074 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1075 ARM_AM::getT2SOImmVal(~Value) != -1;
1077 bool isT2SOImmNeg() const {
1078 if (!isImm()) return false;
1079 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1080 if (!CE) return false;
1081 int64_t Value = CE->getValue();
1082 // Only use this when not representable as a plain so_imm.
1083 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1084 ARM_AM::getT2SOImmVal(-Value) != -1;
1086 bool isSetEndImm() const {
1087 if (!isImm()) return false;
1088 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1089 if (!CE) return false;
1090 int64_t Value = CE->getValue();
1091 return Value == 1 || Value == 0;
1093 bool isReg() const override { return Kind == k_Register; }
1094 bool isRegList() const { return Kind == k_RegisterList; }
1095 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1096 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1097 bool isToken() const override { return Kind == k_Token; }
1098 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1099 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1100 bool isMem() const override { return Kind == k_Memory; }
1101 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1102 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1103 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1104 bool isRotImm() const { return Kind == k_RotateImmediate; }
1105 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1106 bool isModImmNot() const {
1107 if (!isImm()) return false;
1108 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1109 if (!CE) return false;
1110 int64_t Value = CE->getValue();
1111 return ARM_AM::getSOImmVal(~Value) != -1;
1113 bool isModImmNeg() const {
1114 if (!isImm()) return false;
1115 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1116 if (!CE) return false;
1117 int64_t Value = CE->getValue();
1118 return ARM_AM::getSOImmVal(Value) == -1 &&
1119 ARM_AM::getSOImmVal(-Value) != -1;
1121 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1122 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1123 bool isPostIdxReg() const {
1124 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1126 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1129 // No offset of any kind.
1130 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1131 (alignOK || Memory.Alignment == Alignment);
1133 bool isMemPCRelImm12() const {
1134 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1136 // Base register must be PC.
1137 if (Memory.BaseRegNum != ARM::PC)
1139 // Immediate offset in range [-4095, 4095].
1140 if (!Memory.OffsetImm) return true;
1141 int64_t Val = Memory.OffsetImm->getValue();
1142 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1144 bool isAlignedMemory() const {
1145 return isMemNoOffset(true);
1147 bool isAlignedMemoryNone() const {
1148 return isMemNoOffset(false, 0);
1150 bool isDupAlignedMemoryNone() const {
1151 return isMemNoOffset(false, 0);
1153 bool isAlignedMemory16() const {
1154 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1156 return isMemNoOffset(false, 0);
1158 bool isDupAlignedMemory16() const {
1159 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1161 return isMemNoOffset(false, 0);
1163 bool isAlignedMemory32() const {
1164 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1166 return isMemNoOffset(false, 0);
1168 bool isDupAlignedMemory32() const {
1169 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1171 return isMemNoOffset(false, 0);
1173 bool isAlignedMemory64() const {
1174 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1176 return isMemNoOffset(false, 0);
1178 bool isDupAlignedMemory64() const {
1179 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1181 return isMemNoOffset(false, 0);
1183 bool isAlignedMemory64or128() const {
1184 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1186 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1188 return isMemNoOffset(false, 0);
1190 bool isDupAlignedMemory64or128() const {
1191 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1193 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1195 return isMemNoOffset(false, 0);
1197 bool isAlignedMemory64or128or256() const {
1198 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1200 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1202 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1204 return isMemNoOffset(false, 0);
1206 bool isAddrMode2() const {
1207 if (!isMem() || Memory.Alignment != 0) return false;
1208 // Check for register offset.
1209 if (Memory.OffsetRegNum) return true;
1210 // Immediate offset in range [-4095, 4095].
1211 if (!Memory.OffsetImm) return true;
1212 int64_t Val = Memory.OffsetImm->getValue();
1213 return Val > -4096 && Val < 4096;
1215 bool isAM2OffsetImm() const {
1216 if (!isImm()) return false;
1217 // Immediate offset in range [-4095, 4095].
1218 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1219 if (!CE) return false;
1220 int64_t Val = CE->getValue();
1221 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1223 bool isAddrMode3() const {
1224 // If we have an immediate that's not a constant, treat it as a label
1225 // reference needing a fixup. If it is a constant, it's something else
1226 // and we reject it.
1227 if (isImm() && !isa<MCConstantExpr>(getImm()))
1229 if (!isMem() || Memory.Alignment != 0) return false;
1230 // No shifts are legal for AM3.
1231 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1232 // Check for register offset.
1233 if (Memory.OffsetRegNum) return true;
1234 // Immediate offset in range [-255, 255].
1235 if (!Memory.OffsetImm) return true;
1236 int64_t Val = Memory.OffsetImm->getValue();
1237 // The #-0 offset is encoded as INT32_MIN, and we have to check
1239 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1241 bool isAM3Offset() const {
1242 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1244 if (Kind == k_PostIndexRegister)
1245 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1246 // Immediate offset in range [-255, 255].
1247 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1248 if (!CE) return false;
1249 int64_t Val = CE->getValue();
1250 // Special case, #-0 is INT32_MIN.
1251 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1253 bool isAddrMode5() const {
1254 // If we have an immediate that's not a constant, treat it as a label
1255 // reference needing a fixup. If it is a constant, it's something else
1256 // and we reject it.
1257 if (isImm() && !isa<MCConstantExpr>(getImm()))
1259 if (!isMem() || Memory.Alignment != 0) return false;
1260 // Check for register offset.
1261 if (Memory.OffsetRegNum) return false;
1262 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1263 if (!Memory.OffsetImm) return true;
1264 int64_t Val = Memory.OffsetImm->getValue();
1265 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1268 bool isMemTBB() const {
1269 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1270 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1274 bool isMemTBH() const {
1275 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1276 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1277 Memory.Alignment != 0 )
1281 bool isMemRegOffset() const {
1282 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1286 bool isT2MemRegOffset() const {
1287 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1288 Memory.Alignment != 0)
1290 // Only lsl #{0, 1, 2, 3} allowed.
1291 if (Memory.ShiftType == ARM_AM::no_shift)
1293 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1297 bool isMemThumbRR() const {
1298 // Thumb reg+reg addressing is simple. Just two registers, a base and
1299 // an offset. No shifts, negations or any other complicating factors.
1300 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1301 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1303 return isARMLowRegister(Memory.BaseRegNum) &&
1304 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1306 bool isMemThumbRIs4() const {
1307 if (!isMem() || Memory.OffsetRegNum != 0 ||
1308 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1310 // Immediate offset, multiple of 4 in range [0, 124].
1311 if (!Memory.OffsetImm) return true;
1312 int64_t Val = Memory.OffsetImm->getValue();
1313 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1315 bool isMemThumbRIs2() const {
1316 if (!isMem() || Memory.OffsetRegNum != 0 ||
1317 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1319 // Immediate offset, multiple of 4 in range [0, 62].
1320 if (!Memory.OffsetImm) return true;
1321 int64_t Val = Memory.OffsetImm->getValue();
1322 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1324 bool isMemThumbRIs1() const {
1325 if (!isMem() || Memory.OffsetRegNum != 0 ||
1326 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1328 // Immediate offset in range [0, 31].
1329 if (!Memory.OffsetImm) return true;
1330 int64_t Val = Memory.OffsetImm->getValue();
1331 return Val >= 0 && Val <= 31;
1333 bool isMemThumbSPI() const {
1334 if (!isMem() || Memory.OffsetRegNum != 0 ||
1335 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1337 // Immediate offset, multiple of 4 in range [0, 1020].
1338 if (!Memory.OffsetImm) return true;
1339 int64_t Val = Memory.OffsetImm->getValue();
1340 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1342 bool isMemImm8s4Offset() const {
1343 // If we have an immediate that's not a constant, treat it as a label
1344 // reference needing a fixup. If it is a constant, it's something else
1345 // and we reject it.
1346 if (isImm() && !isa<MCConstantExpr>(getImm()))
1348 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1350 // Immediate offset a multiple of 4 in range [-1020, 1020].
1351 if (!Memory.OffsetImm) return true;
1352 int64_t Val = Memory.OffsetImm->getValue();
1353 // Special case, #-0 is INT32_MIN.
1354 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1356 bool isMemImm0_1020s4Offset() const {
1357 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1359 // Immediate offset a multiple of 4 in range [0, 1020].
1360 if (!Memory.OffsetImm) return true;
1361 int64_t Val = Memory.OffsetImm->getValue();
1362 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1364 bool isMemImm8Offset() const {
1365 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1367 // Base reg of PC isn't allowed for these encodings.
1368 if (Memory.BaseRegNum == ARM::PC) return false;
1369 // Immediate offset in range [-255, 255].
1370 if (!Memory.OffsetImm) return true;
1371 int64_t Val = Memory.OffsetImm->getValue();
1372 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1374 bool isMemPosImm8Offset() const {
1375 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1377 // Immediate offset in range [0, 255].
1378 if (!Memory.OffsetImm) return true;
1379 int64_t Val = Memory.OffsetImm->getValue();
1380 return Val >= 0 && Val < 256;
1382 bool isMemNegImm8Offset() const {
1383 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1385 // Base reg of PC isn't allowed for these encodings.
1386 if (Memory.BaseRegNum == ARM::PC) return false;
1387 // Immediate offset in range [-255, -1].
1388 if (!Memory.OffsetImm) return false;
1389 int64_t Val = Memory.OffsetImm->getValue();
1390 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1392 bool isMemUImm12Offset() const {
1393 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1395 // Immediate offset in range [0, 4095].
1396 if (!Memory.OffsetImm) return true;
1397 int64_t Val = Memory.OffsetImm->getValue();
1398 return (Val >= 0 && Val < 4096);
1400 bool isMemImm12Offset() const {
1401 // If we have an immediate that's not a constant, treat it as a label
1402 // reference needing a fixup. If it is a constant, it's something else
1403 // and we reject it.
1404 if (isImm() && !isa<MCConstantExpr>(getImm()))
1407 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1409 // Immediate offset in range [-4095, 4095].
1410 if (!Memory.OffsetImm) return true;
1411 int64_t Val = Memory.OffsetImm->getValue();
1412 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1414 bool isPostIdxImm8() const {
1415 if (!isImm()) return false;
1416 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1417 if (!CE) return false;
1418 int64_t Val = CE->getValue();
1419 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1421 bool isPostIdxImm8s4() const {
1422 if (!isImm()) return false;
1423 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1424 if (!CE) return false;
1425 int64_t Val = CE->getValue();
1426 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1430 bool isMSRMask() const { return Kind == k_MSRMask; }
1431 bool isBankedReg() const { return Kind == k_BankedReg; }
1432 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1435 bool isSingleSpacedVectorList() const {
1436 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1438 bool isDoubleSpacedVectorList() const {
1439 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1441 bool isVecListOneD() const {
1442 if (!isSingleSpacedVectorList()) return false;
1443 return VectorList.Count == 1;
1446 bool isVecListDPair() const {
1447 if (!isSingleSpacedVectorList()) return false;
1448 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1449 .contains(VectorList.RegNum));
1452 bool isVecListThreeD() const {
1453 if (!isSingleSpacedVectorList()) return false;
1454 return VectorList.Count == 3;
1457 bool isVecListFourD() const {
1458 if (!isSingleSpacedVectorList()) return false;
1459 return VectorList.Count == 4;
1462 bool isVecListDPairSpaced() const {
1463 if (Kind != k_VectorList) return false;
1464 if (isSingleSpacedVectorList()) return false;
1465 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1466 .contains(VectorList.RegNum));
1469 bool isVecListThreeQ() const {
1470 if (!isDoubleSpacedVectorList()) return false;
1471 return VectorList.Count == 3;
1474 bool isVecListFourQ() const {
1475 if (!isDoubleSpacedVectorList()) return false;
1476 return VectorList.Count == 4;
1479 bool isSingleSpacedVectorAllLanes() const {
1480 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1482 bool isDoubleSpacedVectorAllLanes() const {
1483 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1485 bool isVecListOneDAllLanes() const {
1486 if (!isSingleSpacedVectorAllLanes()) return false;
1487 return VectorList.Count == 1;
1490 bool isVecListDPairAllLanes() const {
1491 if (!isSingleSpacedVectorAllLanes()) return false;
1492 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1493 .contains(VectorList.RegNum));
1496 bool isVecListDPairSpacedAllLanes() const {
1497 if (!isDoubleSpacedVectorAllLanes()) return false;
1498 return VectorList.Count == 2;
1501 bool isVecListThreeDAllLanes() const {
1502 if (!isSingleSpacedVectorAllLanes()) return false;
1503 return VectorList.Count == 3;
1506 bool isVecListThreeQAllLanes() const {
1507 if (!isDoubleSpacedVectorAllLanes()) return false;
1508 return VectorList.Count == 3;
1511 bool isVecListFourDAllLanes() const {
1512 if (!isSingleSpacedVectorAllLanes()) return false;
1513 return VectorList.Count == 4;
1516 bool isVecListFourQAllLanes() const {
1517 if (!isDoubleSpacedVectorAllLanes()) return false;
1518 return VectorList.Count == 4;
1521 bool isSingleSpacedVectorIndexed() const {
1522 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1524 bool isDoubleSpacedVectorIndexed() const {
1525 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1527 bool isVecListOneDByteIndexed() const {
1528 if (!isSingleSpacedVectorIndexed()) return false;
1529 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1532 bool isVecListOneDHWordIndexed() const {
1533 if (!isSingleSpacedVectorIndexed()) return false;
1534 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1537 bool isVecListOneDWordIndexed() const {
1538 if (!isSingleSpacedVectorIndexed()) return false;
1539 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1542 bool isVecListTwoDByteIndexed() const {
1543 if (!isSingleSpacedVectorIndexed()) return false;
1544 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1547 bool isVecListTwoDHWordIndexed() const {
1548 if (!isSingleSpacedVectorIndexed()) return false;
1549 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1552 bool isVecListTwoQWordIndexed() const {
1553 if (!isDoubleSpacedVectorIndexed()) return false;
1554 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1557 bool isVecListTwoQHWordIndexed() const {
1558 if (!isDoubleSpacedVectorIndexed()) return false;
1559 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1562 bool isVecListTwoDWordIndexed() const {
1563 if (!isSingleSpacedVectorIndexed()) return false;
1564 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1567 bool isVecListThreeDByteIndexed() const {
1568 if (!isSingleSpacedVectorIndexed()) return false;
1569 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1572 bool isVecListThreeDHWordIndexed() const {
1573 if (!isSingleSpacedVectorIndexed()) return false;
1574 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1577 bool isVecListThreeQWordIndexed() const {
1578 if (!isDoubleSpacedVectorIndexed()) return false;
1579 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1582 bool isVecListThreeQHWordIndexed() const {
1583 if (!isDoubleSpacedVectorIndexed()) return false;
1584 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1587 bool isVecListThreeDWordIndexed() const {
1588 if (!isSingleSpacedVectorIndexed()) return false;
1589 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1592 bool isVecListFourDByteIndexed() const {
1593 if (!isSingleSpacedVectorIndexed()) return false;
1594 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1597 bool isVecListFourDHWordIndexed() const {
1598 if (!isSingleSpacedVectorIndexed()) return false;
1599 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1602 bool isVecListFourQWordIndexed() const {
1603 if (!isDoubleSpacedVectorIndexed()) return false;
1604 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1607 bool isVecListFourQHWordIndexed() const {
1608 if (!isDoubleSpacedVectorIndexed()) return false;
1609 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1612 bool isVecListFourDWordIndexed() const {
1613 if (!isSingleSpacedVectorIndexed()) return false;
1614 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1617 bool isVectorIndex8() const {
1618 if (Kind != k_VectorIndex) return false;
1619 return VectorIndex.Val < 8;
1621 bool isVectorIndex16() const {
1622 if (Kind != k_VectorIndex) return false;
1623 return VectorIndex.Val < 4;
1625 bool isVectorIndex32() const {
1626 if (Kind != k_VectorIndex) return false;
1627 return VectorIndex.Val < 2;
1630 bool isNEONi8splat() const {
1631 if (!isImm()) return false;
1632 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1633 // Must be a constant.
1634 if (!CE) return false;
1635 int64_t Value = CE->getValue();
1636 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1638 return Value >= 0 && Value < 256;
1641 bool isNEONi16splat() const {
1642 if (isNEONByteReplicate(2))
1643 return false; // Leave that for bytes replication and forbid by default.
1646 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1647 // Must be a constant.
1648 if (!CE) return false;
1649 unsigned Value = CE->getValue();
1650 return ARM_AM::isNEONi16splat(Value);
1653 bool isNEONi16splatNot() const {
1656 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1657 // Must be a constant.
1658 if (!CE) return false;
1659 unsigned Value = CE->getValue();
1660 return ARM_AM::isNEONi16splat(~Value & 0xffff);
1663 bool isNEONi32splat() const {
1664 if (isNEONByteReplicate(4))
1665 return false; // Leave that for bytes replication and forbid by default.
1668 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1669 // Must be a constant.
1670 if (!CE) return false;
1671 unsigned Value = CE->getValue();
1672 return ARM_AM::isNEONi32splat(Value);
1675 bool isNEONi32splatNot() const {
1678 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1679 // Must be a constant.
1680 if (!CE) return false;
1681 unsigned Value = CE->getValue();
1682 return ARM_AM::isNEONi32splat(~Value);
1685 bool isNEONByteReplicate(unsigned NumBytes) const {
1688 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1689 // Must be a constant.
1692 int64_t Value = CE->getValue();
1694 return false; // Don't bother with zero.
1696 unsigned char B = Value & 0xff;
1697 for (unsigned i = 1; i < NumBytes; ++i) {
1699 if ((Value & 0xff) != B)
1704 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1705 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1706 bool isNEONi32vmov() const {
1707 if (isNEONByteReplicate(4))
1708 return false; // Let it to be classified as byte-replicate case.
1711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1712 // Must be a constant.
1715 int64_t Value = CE->getValue();
1716 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1717 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1718 // FIXME: This is probably wrong and a copy and paste from previous example
1719 return (Value >= 0 && Value < 256) ||
1720 (Value >= 0x0100 && Value <= 0xff00) ||
1721 (Value >= 0x010000 && Value <= 0xff0000) ||
1722 (Value >= 0x01000000 && Value <= 0xff000000) ||
1723 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1724 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1726 bool isNEONi32vmovNeg() const {
1727 if (!isImm()) return false;
1728 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1729 // Must be a constant.
1730 if (!CE) return false;
1731 int64_t Value = ~CE->getValue();
1732 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1733 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1734 // FIXME: This is probably wrong and a copy and paste from previous example
1735 return (Value >= 0 && Value < 256) ||
1736 (Value >= 0x0100 && Value <= 0xff00) ||
1737 (Value >= 0x010000 && Value <= 0xff0000) ||
1738 (Value >= 0x01000000 && Value <= 0xff000000) ||
1739 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1740 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1743 bool isNEONi64splat() const {
1744 if (!isImm()) return false;
1745 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1746 // Must be a constant.
1747 if (!CE) return false;
1748 uint64_t Value = CE->getValue();
1749 // i64 value with each byte being either 0 or 0xff.
1750 for (unsigned i = 0; i < 8; ++i)
1751 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1755 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1756 // Add as immediates when possible. Null MCExpr = 0.
1758 Inst.addOperand(MCOperand::CreateImm(0));
1759 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1760 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1762 Inst.addOperand(MCOperand::CreateExpr(Expr));
1765 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1766 assert(N == 2 && "Invalid number of operands!");
1767 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1768 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1769 Inst.addOperand(MCOperand::CreateReg(RegNum));
1772 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1773 assert(N == 1 && "Invalid number of operands!");
1774 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1777 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1778 assert(N == 1 && "Invalid number of operands!");
1779 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1782 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1783 assert(N == 1 && "Invalid number of operands!");
1784 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1787 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1788 assert(N == 1 && "Invalid number of operands!");
1789 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1792 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1793 assert(N == 1 && "Invalid number of operands!");
1794 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1797 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1798 assert(N == 1 && "Invalid number of operands!");
1799 Inst.addOperand(MCOperand::CreateReg(getReg()));
1802 void addRegOperands(MCInst &Inst, unsigned N) const {
1803 assert(N == 1 && "Invalid number of operands!");
1804 Inst.addOperand(MCOperand::CreateReg(getReg()));
1807 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1808 assert(N == 3 && "Invalid number of operands!");
1809 assert(isRegShiftedReg() &&
1810 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1811 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1812 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1813 Inst.addOperand(MCOperand::CreateImm(
1814 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1817 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1818 assert(N == 2 && "Invalid number of operands!");
1819 assert(isRegShiftedImm() &&
1820 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1821 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1822 // Shift of #32 is encoded as 0 where permitted
1823 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1824 Inst.addOperand(MCOperand::CreateImm(
1825 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1828 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1829 assert(N == 1 && "Invalid number of operands!");
1830 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1834 void addRegListOperands(MCInst &Inst, unsigned N) const {
1835 assert(N == 1 && "Invalid number of operands!");
1836 const SmallVectorImpl<unsigned> &RegList = getRegList();
1837 for (SmallVectorImpl<unsigned>::const_iterator
1838 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1839 Inst.addOperand(MCOperand::CreateReg(*I));
1842 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1843 addRegListOperands(Inst, N);
1846 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1847 addRegListOperands(Inst, N);
1850 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1851 assert(N == 1 && "Invalid number of operands!");
1852 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1853 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1856 void addModImmOperands(MCInst &Inst, unsigned N) const {
1857 assert(N == 1 && "Invalid number of operands!");
1859 // Support for fixups (MCFixup)
1861 return addImmOperands(Inst, N);
1863 if (Inst.getOpcode() == ARM::ADDri &&
1864 Inst.getOperand(1).getReg() == ARM::PC) {
1865 // Instructions of the form [ADD <rd>, pc, #imm] are manually aliased
1866 // in processInstruction() to use ADR. We must keep the immediate in
1867 // its unencoded form in order to not clash with this aliasing.
1868 Inst.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(ModImm.Bits,
1871 Inst.addOperand(MCOperand::CreateImm(ModImm.Bits | (ModImm.Rot << 7)));
1875 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1876 assert(N == 1 && "Invalid number of operands!");
1877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1878 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1879 Inst.addOperand(MCOperand::CreateImm(Enc));
1882 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1883 assert(N == 1 && "Invalid number of operands!");
1884 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1885 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1886 Inst.addOperand(MCOperand::CreateImm(Enc));
1889 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1890 assert(N == 1 && "Invalid number of operands!");
1891 // Munge the lsb/width into a bitfield mask.
1892 unsigned lsb = Bitfield.LSB;
1893 unsigned width = Bitfield.Width;
1894 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1895 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1896 (32 - (lsb + width)));
1897 Inst.addOperand(MCOperand::CreateImm(Mask));
1900 void addImmOperands(MCInst &Inst, unsigned N) const {
1901 assert(N == 1 && "Invalid number of operands!");
1902 addExpr(Inst, getImm());
1905 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1906 assert(N == 1 && "Invalid number of operands!");
1907 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1908 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1911 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1912 assert(N == 1 && "Invalid number of operands!");
1913 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1914 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1917 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1918 assert(N == 1 && "Invalid number of operands!");
1919 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1920 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1921 Inst.addOperand(MCOperand::CreateImm(Val));
1924 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1925 assert(N == 1 && "Invalid number of operands!");
1926 // FIXME: We really want to scale the value here, but the LDRD/STRD
1927 // instruction don't encode operands that way yet.
1928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1929 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1932 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1933 assert(N == 1 && "Invalid number of operands!");
1934 // The immediate is scaled by four in the encoding and is stored
1935 // in the MCInst as such. Lop off the low two bits here.
1936 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1937 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1940 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1941 assert(N == 1 && "Invalid number of operands!");
1942 // The immediate is scaled by four in the encoding and is stored
1943 // in the MCInst as such. Lop off the low two bits here.
1944 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1945 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1948 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1949 assert(N == 1 && "Invalid number of operands!");
1950 // The immediate is scaled by four in the encoding and is stored
1951 // in the MCInst as such. Lop off the low two bits here.
1952 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1953 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1956 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1957 assert(N == 1 && "Invalid number of operands!");
1958 // The constant encodes as the immediate-1, and we store in the instruction
1959 // the bits as encoded, so subtract off one here.
1960 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1961 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1964 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1965 assert(N == 1 && "Invalid number of operands!");
1966 // The constant encodes as the immediate-1, and we store in the instruction
1967 // the bits as encoded, so subtract off one here.
1968 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1969 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1972 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1973 assert(N == 1 && "Invalid number of operands!");
1974 // The constant encodes as the immediate, except for 32, which encodes as
1976 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1977 unsigned Imm = CE->getValue();
1978 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1981 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1982 assert(N == 1 && "Invalid number of operands!");
1983 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1984 // the instruction as well.
1985 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1986 int Val = CE->getValue();
1987 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1990 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1991 assert(N == 1 && "Invalid number of operands!");
1992 // The operand is actually a t2_so_imm, but we have its bitwise
1993 // negation in the assembly source, so twiddle it here.
1994 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1995 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1998 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1999 assert(N == 1 && "Invalid number of operands!");
2000 // The operand is actually a t2_so_imm, but we have its
2001 // negation in the assembly source, so twiddle it here.
2002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2003 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
2006 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2007 assert(N == 1 && "Invalid number of operands!");
2008 // The operand is actually an imm0_4095, but we have its
2009 // negation in the assembly source, so twiddle it here.
2010 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2011 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
2014 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2015 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2016 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
2020 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2021 assert(SR && "Unknown value type!");
2022 Inst.addOperand(MCOperand::CreateExpr(SR));
2025 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2026 assert(N == 1 && "Invalid number of operands!");
2028 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2030 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
2034 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2035 assert(SR && "Unknown value type!");
2036 Inst.addOperand(MCOperand::CreateExpr(SR));
2040 assert(isMem() && "Unknown value type!");
2041 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2042 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
2045 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
2046 assert(N == 1 && "Invalid number of operands!");
2047 // The operand is actually a so_imm, but we have its bitwise
2048 // negation in the assembly source, so twiddle it here.
2049 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2050 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
2053 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
2054 assert(N == 1 && "Invalid number of operands!");
2055 // The operand is actually a so_imm, but we have its
2056 // negation in the assembly source, so twiddle it here.
2057 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2058 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
2061 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2062 assert(N == 1 && "Invalid number of operands!");
2063 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
2066 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2067 assert(N == 1 && "Invalid number of operands!");
2068 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
2071 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2072 assert(N == 1 && "Invalid number of operands!");
2073 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2076 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2077 assert(N == 1 && "Invalid number of operands!");
2078 int32_t Imm = Memory.OffsetImm->getValue();
2079 Inst.addOperand(MCOperand::CreateImm(Imm));
2082 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2083 assert(N == 1 && "Invalid number of operands!");
2084 assert(isImm() && "Not an immediate!");
2086 // If we have an immediate that's not a constant, treat it as a label
2087 // reference needing a fixup.
2088 if (!isa<MCConstantExpr>(getImm())) {
2089 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2093 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2094 int Val = CE->getValue();
2095 Inst.addOperand(MCOperand::CreateImm(Val));
2098 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2099 assert(N == 2 && "Invalid number of operands!");
2100 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2101 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2104 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2105 addAlignedMemoryOperands(Inst, N);
2108 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2109 addAlignedMemoryOperands(Inst, N);
2112 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2113 addAlignedMemoryOperands(Inst, N);
2116 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2117 addAlignedMemoryOperands(Inst, N);
2120 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2121 addAlignedMemoryOperands(Inst, N);
2124 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2125 addAlignedMemoryOperands(Inst, N);
2128 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2129 addAlignedMemoryOperands(Inst, N);
2132 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2133 addAlignedMemoryOperands(Inst, N);
2136 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2137 addAlignedMemoryOperands(Inst, N);
2140 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2141 addAlignedMemoryOperands(Inst, N);
2144 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2145 addAlignedMemoryOperands(Inst, N);
2148 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2149 assert(N == 3 && "Invalid number of operands!");
2150 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2151 if (!Memory.OffsetRegNum) {
2152 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2153 // Special case for #-0
2154 if (Val == INT32_MIN) Val = 0;
2155 if (Val < 0) Val = -Val;
2156 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2158 // For register offset, we encode the shift type and negation flag
2160 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2161 Memory.ShiftImm, Memory.ShiftType);
2163 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2164 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2165 Inst.addOperand(MCOperand::CreateImm(Val));
2168 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2169 assert(N == 2 && "Invalid number of operands!");
2170 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2171 assert(CE && "non-constant AM2OffsetImm operand!");
2172 int32_t Val = CE->getValue();
2173 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2174 // Special case for #-0
2175 if (Val == INT32_MIN) Val = 0;
2176 if (Val < 0) Val = -Val;
2177 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2178 Inst.addOperand(MCOperand::CreateReg(0));
2179 Inst.addOperand(MCOperand::CreateImm(Val));
2182 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2183 assert(N == 3 && "Invalid number of operands!");
2184 // If we have an immediate that's not a constant, treat it as a label
2185 // reference needing a fixup. If it is a constant, it's something else
2186 // and we reject it.
2188 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2189 Inst.addOperand(MCOperand::CreateReg(0));
2190 Inst.addOperand(MCOperand::CreateImm(0));
2194 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2195 if (!Memory.OffsetRegNum) {
2196 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2197 // Special case for #-0
2198 if (Val == INT32_MIN) Val = 0;
2199 if (Val < 0) Val = -Val;
2200 Val = ARM_AM::getAM3Opc(AddSub, Val);
2202 // For register offset, we encode the shift type and negation flag
2204 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2206 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2207 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2208 Inst.addOperand(MCOperand::CreateImm(Val));
2211 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2212 assert(N == 2 && "Invalid number of operands!");
2213 if (Kind == k_PostIndexRegister) {
2215 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2216 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2217 Inst.addOperand(MCOperand::CreateImm(Val));
2222 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2223 int32_t Val = CE->getValue();
2224 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2225 // Special case for #-0
2226 if (Val == INT32_MIN) Val = 0;
2227 if (Val < 0) Val = -Val;
2228 Val = ARM_AM::getAM3Opc(AddSub, Val);
2229 Inst.addOperand(MCOperand::CreateReg(0));
2230 Inst.addOperand(MCOperand::CreateImm(Val));
2233 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2234 assert(N == 2 && "Invalid number of operands!");
2235 // If we have an immediate that's not a constant, treat it as a label
2236 // reference needing a fixup. If it is a constant, it's something else
2237 // and we reject it.
2239 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2240 Inst.addOperand(MCOperand::CreateImm(0));
2244 // The lower two bits are always zero and as such are not encoded.
2245 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2246 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2247 // Special case for #-0
2248 if (Val == INT32_MIN) Val = 0;
2249 if (Val < 0) Val = -Val;
2250 Val = ARM_AM::getAM5Opc(AddSub, Val);
2251 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2252 Inst.addOperand(MCOperand::CreateImm(Val));
2255 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2256 assert(N == 2 && "Invalid number of operands!");
2257 // If we have an immediate that's not a constant, treat it as a label
2258 // reference needing a fixup. If it is a constant, it's something else
2259 // and we reject it.
2261 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2262 Inst.addOperand(MCOperand::CreateImm(0));
2266 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2267 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2268 Inst.addOperand(MCOperand::CreateImm(Val));
2271 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2272 assert(N == 2 && "Invalid number of operands!");
2273 // The lower two bits are always zero and as such are not encoded.
2274 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2275 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2276 Inst.addOperand(MCOperand::CreateImm(Val));
2279 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2280 assert(N == 2 && "Invalid number of operands!");
2281 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2282 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2283 Inst.addOperand(MCOperand::CreateImm(Val));
2286 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2287 addMemImm8OffsetOperands(Inst, N);
2290 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2291 addMemImm8OffsetOperands(Inst, N);
2294 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2295 assert(N == 2 && "Invalid number of operands!");
2296 // If this is an immediate, it's a label reference.
2298 addExpr(Inst, getImm());
2299 Inst.addOperand(MCOperand::CreateImm(0));
2303 // Otherwise, it's a normal memory reg+offset.
2304 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2305 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2306 Inst.addOperand(MCOperand::CreateImm(Val));
2309 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2310 assert(N == 2 && "Invalid number of operands!");
2311 // If this is an immediate, it's a label reference.
2313 addExpr(Inst, getImm());
2314 Inst.addOperand(MCOperand::CreateImm(0));
2318 // Otherwise, it's a normal memory reg+offset.
2319 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2320 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2321 Inst.addOperand(MCOperand::CreateImm(Val));
2324 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2325 assert(N == 2 && "Invalid number of operands!");
2326 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2327 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2330 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2331 assert(N == 2 && "Invalid number of operands!");
2332 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2333 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2336 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2337 assert(N == 3 && "Invalid number of operands!");
2339 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2340 Memory.ShiftImm, Memory.ShiftType);
2341 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2342 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2343 Inst.addOperand(MCOperand::CreateImm(Val));
2346 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2347 assert(N == 3 && "Invalid number of operands!");
2348 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2349 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2350 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2353 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2354 assert(N == 2 && "Invalid number of operands!");
2355 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2356 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2359 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2360 assert(N == 2 && "Invalid number of operands!");
2361 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2362 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2363 Inst.addOperand(MCOperand::CreateImm(Val));
2366 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2367 assert(N == 2 && "Invalid number of operands!");
2368 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2369 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2370 Inst.addOperand(MCOperand::CreateImm(Val));
2373 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2374 assert(N == 2 && "Invalid number of operands!");
2375 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2376 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2377 Inst.addOperand(MCOperand::CreateImm(Val));
2380 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2381 assert(N == 2 && "Invalid number of operands!");
2382 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2383 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2384 Inst.addOperand(MCOperand::CreateImm(Val));
2387 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2388 assert(N == 1 && "Invalid number of operands!");
2389 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2390 assert(CE && "non-constant post-idx-imm8 operand!");
2391 int Imm = CE->getValue();
2392 bool isAdd = Imm >= 0;
2393 if (Imm == INT32_MIN) Imm = 0;
2394 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2395 Inst.addOperand(MCOperand::CreateImm(Imm));
2398 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2399 assert(N == 1 && "Invalid number of operands!");
2400 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2401 assert(CE && "non-constant post-idx-imm8s4 operand!");
2402 int Imm = CE->getValue();
2403 bool isAdd = Imm >= 0;
2404 if (Imm == INT32_MIN) Imm = 0;
2405 // Immediate is scaled by 4.
2406 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2407 Inst.addOperand(MCOperand::CreateImm(Imm));
2410 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2411 assert(N == 2 && "Invalid number of operands!");
2412 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2413 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2416 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2417 assert(N == 2 && "Invalid number of operands!");
2418 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2419 // The sign, shift type, and shift amount are encoded in a single operand
2420 // using the AM2 encoding helpers.
2421 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2422 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2423 PostIdxReg.ShiftTy);
2424 Inst.addOperand(MCOperand::CreateImm(Imm));
2427 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2428 assert(N == 1 && "Invalid number of operands!");
2429 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2432 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2433 assert(N == 1 && "Invalid number of operands!");
2434 Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
2437 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2438 assert(N == 1 && "Invalid number of operands!");
2439 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2442 void addVecListOperands(MCInst &Inst, unsigned N) const {
2443 assert(N == 1 && "Invalid number of operands!");
2444 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2447 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2448 assert(N == 2 && "Invalid number of operands!");
2449 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2450 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2453 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2454 assert(N == 1 && "Invalid number of operands!");
2455 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2458 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2459 assert(N == 1 && "Invalid number of operands!");
2460 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2463 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2464 assert(N == 1 && "Invalid number of operands!");
2465 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2468 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2469 assert(N == 1 && "Invalid number of operands!");
2470 // The immediate encodes the type of constant as well as the value.
2471 // Mask in that this is an i8 splat.
2472 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2473 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2476 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2477 assert(N == 1 && "Invalid number of operands!");
2478 // The immediate encodes the type of constant as well as the value.
2479 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2480 unsigned Value = CE->getValue();
2481 Value = ARM_AM::encodeNEONi16splat(Value);
2482 Inst.addOperand(MCOperand::CreateImm(Value));
2485 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2486 assert(N == 1 && "Invalid number of operands!");
2487 // The immediate encodes the type of constant as well as the value.
2488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2489 unsigned Value = CE->getValue();
2490 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2491 Inst.addOperand(MCOperand::CreateImm(Value));
2494 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2495 assert(N == 1 && "Invalid number of operands!");
2496 // The immediate encodes the type of constant as well as the value.
2497 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2498 unsigned Value = CE->getValue();
2499 Value = ARM_AM::encodeNEONi32splat(Value);
2500 Inst.addOperand(MCOperand::CreateImm(Value));
2503 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2504 assert(N == 1 && "Invalid number of operands!");
2505 // The immediate encodes the type of constant as well as the value.
2506 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2507 unsigned Value = CE->getValue();
2508 Value = ARM_AM::encodeNEONi32splat(~Value);
2509 Inst.addOperand(MCOperand::CreateImm(Value));
2512 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2513 assert(N == 1 && "Invalid number of operands!");
2514 // The immediate encodes the type of constant as well as the value.
2515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2516 unsigned Value = CE->getValue();
2517 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2518 Inst.getOpcode() == ARM::VMOVv16i8) &&
2519 "All vmvn instructions that wants to replicate non-zero byte "
2520 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2521 unsigned B = ((~Value) & 0xff);
2522 B |= 0xe00; // cmode = 0b1110
2523 Inst.addOperand(MCOperand::CreateImm(B));
2525 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2526 assert(N == 1 && "Invalid number of operands!");
2527 // The immediate encodes the type of constant as well as the value.
2528 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2529 unsigned Value = CE->getValue();
2530 if (Value >= 256 && Value <= 0xffff)
2531 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2532 else if (Value > 0xffff && Value <= 0xffffff)
2533 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2534 else if (Value > 0xffffff)
2535 Value = (Value >> 24) | 0x600;
2536 Inst.addOperand(MCOperand::CreateImm(Value));
2539 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2540 assert(N == 1 && "Invalid number of operands!");
2541 // The immediate encodes the type of constant as well as the value.
2542 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2543 unsigned Value = CE->getValue();
2544 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2545 Inst.getOpcode() == ARM::VMOVv16i8) &&
2546 "All instructions that wants to replicate non-zero byte "
2547 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2548 unsigned B = Value & 0xff;
2549 B |= 0xe00; // cmode = 0b1110
2550 Inst.addOperand(MCOperand::CreateImm(B));
2552 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2553 assert(N == 1 && "Invalid number of operands!");
2554 // The immediate encodes the type of constant as well as the value.
2555 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2556 unsigned Value = ~CE->getValue();
2557 if (Value >= 256 && Value <= 0xffff)
2558 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2559 else if (Value > 0xffff && Value <= 0xffffff)
2560 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2561 else if (Value > 0xffffff)
2562 Value = (Value >> 24) | 0x600;
2563 Inst.addOperand(MCOperand::CreateImm(Value));
2566 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2567 assert(N == 1 && "Invalid number of operands!");
2568 // The immediate encodes the type of constant as well as the value.
2569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2570 uint64_t Value = CE->getValue();
2572 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2573 Imm |= (Value & 1) << i;
2575 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2578 void print(raw_ostream &OS) const override;
2580 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2581 auto Op = make_unique<ARMOperand>(k_ITCondMask);
2582 Op->ITMask.Mask = Mask;
2588 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2590 auto Op = make_unique<ARMOperand>(k_CondCode);
2597 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2598 auto Op = make_unique<ARMOperand>(k_CoprocNum);
2599 Op->Cop.Val = CopVal;
2605 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2606 auto Op = make_unique<ARMOperand>(k_CoprocReg);
2607 Op->Cop.Val = CopVal;
2613 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2615 auto Op = make_unique<ARMOperand>(k_CoprocOption);
2622 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2623 auto Op = make_unique<ARMOperand>(k_CCOut);
2624 Op->Reg.RegNum = RegNum;
2630 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2631 auto Op = make_unique<ARMOperand>(k_Token);
2632 Op->Tok.Data = Str.data();
2633 Op->Tok.Length = Str.size();
2639 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2641 auto Op = make_unique<ARMOperand>(k_Register);
2642 Op->Reg.RegNum = RegNum;
2648 static std::unique_ptr<ARMOperand>
2649 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2650 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2652 auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2653 Op->RegShiftedReg.ShiftTy = ShTy;
2654 Op->RegShiftedReg.SrcReg = SrcReg;
2655 Op->RegShiftedReg.ShiftReg = ShiftReg;
2656 Op->RegShiftedReg.ShiftImm = ShiftImm;
2662 static std::unique_ptr<ARMOperand>
2663 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2664 unsigned ShiftImm, SMLoc S, SMLoc E) {
2665 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2666 Op->RegShiftedImm.ShiftTy = ShTy;
2667 Op->RegShiftedImm.SrcReg = SrcReg;
2668 Op->RegShiftedImm.ShiftImm = ShiftImm;
2674 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2676 auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2677 Op->ShifterImm.isASR = isASR;
2678 Op->ShifterImm.Imm = Imm;
2684 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2686 auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2687 Op->RotImm.Imm = Imm;
2693 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2695 auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2696 Op->ModImm.Bits = Bits;
2697 Op->ModImm.Rot = Rot;
2703 static std::unique_ptr<ARMOperand>
2704 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2705 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2706 Op->Bitfield.LSB = LSB;
2707 Op->Bitfield.Width = Width;
2713 static std::unique_ptr<ARMOperand>
2714 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2715 SMLoc StartLoc, SMLoc EndLoc) {
2716 assert (Regs.size() > 0 && "RegList contains no registers?");
2717 KindTy Kind = k_RegisterList;
2719 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2720 Kind = k_DPRRegisterList;
2721 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2722 contains(Regs.front().second))
2723 Kind = k_SPRRegisterList;
2725 // Sort based on the register encoding values.
2726 array_pod_sort(Regs.begin(), Regs.end());
2728 auto Op = make_unique<ARMOperand>(Kind);
2729 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2730 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2731 Op->Registers.push_back(I->second);
2732 Op->StartLoc = StartLoc;
2733 Op->EndLoc = EndLoc;
2737 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2739 bool isDoubleSpaced,
2741 auto Op = make_unique<ARMOperand>(k_VectorList);
2742 Op->VectorList.RegNum = RegNum;
2743 Op->VectorList.Count = Count;
2744 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2750 static std::unique_ptr<ARMOperand>
2751 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2753 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2754 Op->VectorList.RegNum = RegNum;
2755 Op->VectorList.Count = Count;
2756 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2762 static std::unique_ptr<ARMOperand>
2763 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2764 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2765 auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2766 Op->VectorList.RegNum = RegNum;
2767 Op->VectorList.Count = Count;
2768 Op->VectorList.LaneIndex = Index;
2769 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2775 static std::unique_ptr<ARMOperand>
2776 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2777 auto Op = make_unique<ARMOperand>(k_VectorIndex);
2778 Op->VectorIndex.Val = Idx;
2784 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2786 auto Op = make_unique<ARMOperand>(k_Immediate);
2793 static std::unique_ptr<ARMOperand>
2794 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2795 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2796 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2797 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2798 auto Op = make_unique<ARMOperand>(k_Memory);
2799 Op->Memory.BaseRegNum = BaseRegNum;
2800 Op->Memory.OffsetImm = OffsetImm;
2801 Op->Memory.OffsetRegNum = OffsetRegNum;
2802 Op->Memory.ShiftType = ShiftType;
2803 Op->Memory.ShiftImm = ShiftImm;
2804 Op->Memory.Alignment = Alignment;
2805 Op->Memory.isNegative = isNegative;
2808 Op->AlignmentLoc = AlignmentLoc;
2812 static std::unique_ptr<ARMOperand>
2813 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2814 unsigned ShiftImm, SMLoc S, SMLoc E) {
2815 auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2816 Op->PostIdxReg.RegNum = RegNum;
2817 Op->PostIdxReg.isAdd = isAdd;
2818 Op->PostIdxReg.ShiftTy = ShiftTy;
2819 Op->PostIdxReg.ShiftImm = ShiftImm;
2825 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2827 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2828 Op->MBOpt.Val = Opt;
2834 static std::unique_ptr<ARMOperand>
2835 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2836 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2837 Op->ISBOpt.Val = Opt;
2843 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2845 auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2846 Op->IFlags.Val = IFlags;
2852 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2853 auto Op = make_unique<ARMOperand>(k_MSRMask);
2854 Op->MMask.Val = MMask;
2860 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2861 auto Op = make_unique<ARMOperand>(k_BankedReg);
2862 Op->BankedReg.Val = Reg;
2869 } // end anonymous namespace.
2871 void ARMOperand::print(raw_ostream &OS) const {
2874 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2877 OS << "<ccout " << getReg() << ">";
2879 case k_ITCondMask: {
2880 static const char *const MaskStr[] = {
2881 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2882 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2884 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2885 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2889 OS << "<coprocessor number: " << getCoproc() << ">";
2892 OS << "<coprocessor register: " << getCoproc() << ">";
2894 case k_CoprocOption:
2895 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2898 OS << "<mask: " << getMSRMask() << ">";
2901 OS << "<banked reg: " << getBankedReg() << ">";
2904 getImm()->print(OS);
2906 case k_MemBarrierOpt:
2907 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2909 case k_InstSyncBarrierOpt:
2910 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2914 << " base:" << Memory.BaseRegNum;
2917 case k_PostIndexRegister:
2918 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2919 << PostIdxReg.RegNum;
2920 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2921 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2922 << PostIdxReg.ShiftImm;
2925 case k_ProcIFlags: {
2926 OS << "<ARM_PROC::";
2927 unsigned IFlags = getProcIFlags();
2928 for (int i=2; i >= 0; --i)
2929 if (IFlags & (1 << i))
2930 OS << ARM_PROC::IFlagsToString(1 << i);
2935 OS << "<register " << getReg() << ">";
2937 case k_ShifterImmediate:
2938 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2939 << " #" << ShifterImm.Imm << ">";
2941 case k_ShiftedRegister:
2942 OS << "<so_reg_reg "
2943 << RegShiftedReg.SrcReg << " "
2944 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2945 << " " << RegShiftedReg.ShiftReg << ">";
2947 case k_ShiftedImmediate:
2948 OS << "<so_reg_imm "
2949 << RegShiftedImm.SrcReg << " "
2950 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2951 << " #" << RegShiftedImm.ShiftImm << ">";
2953 case k_RotateImmediate:
2954 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2956 case k_ModifiedImmediate:
2957 OS << "<mod_imm #" << ModImm.Bits << ", #"
2958 << ModImm.Rot << ")>";
2960 case k_BitfieldDescriptor:
2961 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2962 << ", width: " << Bitfield.Width << ">";
2964 case k_RegisterList:
2965 case k_DPRRegisterList:
2966 case k_SPRRegisterList: {
2967 OS << "<register_list ";
2969 const SmallVectorImpl<unsigned> &RegList = getRegList();
2970 for (SmallVectorImpl<unsigned>::const_iterator
2971 I = RegList.begin(), E = RegList.end(); I != E; ) {
2973 if (++I < E) OS << ", ";
2980 OS << "<vector_list " << VectorList.Count << " * "
2981 << VectorList.RegNum << ">";
2983 case k_VectorListAllLanes:
2984 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2985 << VectorList.RegNum << ">";
2987 case k_VectorListIndexed:
2988 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2989 << VectorList.Count << " * " << VectorList.RegNum << ">";
2992 OS << "'" << getToken() << "'";
2995 OS << "<vectorindex " << getVectorIndex() << ">";
3000 /// @name Auto-generated Match Functions
3003 static unsigned MatchRegisterName(StringRef Name);
3007 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3008 SMLoc &StartLoc, SMLoc &EndLoc) {
3009 const AsmToken &Tok = getParser().getTok();
3010 StartLoc = Tok.getLoc();
3011 EndLoc = Tok.getEndLoc();
3012 RegNo = tryParseRegister();
3014 return (RegNo == (unsigned)-1);
3017 /// Try to parse a register name. The token must be an Identifier when called,
3018 /// and if it is a register name the token is eaten and the register number is
3019 /// returned. Otherwise return -1.
3021 int ARMAsmParser::tryParseRegister() {
3022 MCAsmParser &Parser = getParser();
3023 const AsmToken &Tok = Parser.getTok();
3024 if (Tok.isNot(AsmToken::Identifier)) return -1;
3026 std::string lowerCase = Tok.getString().lower();
3027 unsigned RegNum = MatchRegisterName(lowerCase);
3029 RegNum = StringSwitch<unsigned>(lowerCase)
3030 .Case("r13", ARM::SP)
3031 .Case("r14", ARM::LR)
3032 .Case("r15", ARM::PC)
3033 .Case("ip", ARM::R12)
3034 // Additional register name aliases for 'gas' compatibility.
3035 .Case("a1", ARM::R0)
3036 .Case("a2", ARM::R1)
3037 .Case("a3", ARM::R2)
3038 .Case("a4", ARM::R3)
3039 .Case("v1", ARM::R4)
3040 .Case("v2", ARM::R5)
3041 .Case("v3", ARM::R6)
3042 .Case("v4", ARM::R7)
3043 .Case("v5", ARM::R8)
3044 .Case("v6", ARM::R9)
3045 .Case("v7", ARM::R10)
3046 .Case("v8", ARM::R11)
3047 .Case("sb", ARM::R9)
3048 .Case("sl", ARM::R10)
3049 .Case("fp", ARM::R11)
3053 // Check for aliases registered via .req. Canonicalize to lower case.
3054 // That's more consistent since register names are case insensitive, and
3055 // it's how the original entry was passed in from MC/MCParser/AsmParser.
3056 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3057 // If no match, return failure.
3058 if (Entry == RegisterReqs.end())
3060 Parser.Lex(); // Eat identifier token.
3061 return Entry->getValue();
3064 // Some FPUs only have 16 D registers, so D16-D31 are invalid
3065 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3068 Parser.Lex(); // Eat identifier token.
3073 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3074 // If a recoverable error occurs, return 1. If an irrecoverable error
3075 // occurs, return -1. An irrecoverable error is one where tokens have been
3076 // consumed in the process of trying to parse the shifter (i.e., when it is
3077 // indeed a shifter operand, but malformed).
3078 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3079 MCAsmParser &Parser = getParser();
3080 SMLoc S = Parser.getTok().getLoc();
3081 const AsmToken &Tok = Parser.getTok();
3082 if (Tok.isNot(AsmToken::Identifier))
3085 std::string lowerCase = Tok.getString().lower();
3086 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3087 .Case("asl", ARM_AM::lsl)
3088 .Case("lsl", ARM_AM::lsl)
3089 .Case("lsr", ARM_AM::lsr)
3090 .Case("asr", ARM_AM::asr)
3091 .Case("ror", ARM_AM::ror)
3092 .Case("rrx", ARM_AM::rrx)
3093 .Default(ARM_AM::no_shift);
3095 if (ShiftTy == ARM_AM::no_shift)
3098 Parser.Lex(); // Eat the operator.
3100 // The source register for the shift has already been added to the
3101 // operand list, so we need to pop it off and combine it into the shifted
3102 // register operand instead.
3103 std::unique_ptr<ARMOperand> PrevOp(
3104 (ARMOperand *)Operands.pop_back_val().release());
3105 if (!PrevOp->isReg())
3106 return Error(PrevOp->getStartLoc(), "shift must be of a register");
3107 int SrcReg = PrevOp->getReg();
3112 if (ShiftTy == ARM_AM::rrx) {
3113 // RRX Doesn't have an explicit shift amount. The encoder expects
3114 // the shift register to be the same as the source register. Seems odd,
3118 // Figure out if this is shifted by a constant or a register (for non-RRX).
3119 if (Parser.getTok().is(AsmToken::Hash) ||
3120 Parser.getTok().is(AsmToken::Dollar)) {
3121 Parser.Lex(); // Eat hash.
3122 SMLoc ImmLoc = Parser.getTok().getLoc();
3123 const MCExpr *ShiftExpr = nullptr;
3124 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3125 Error(ImmLoc, "invalid immediate shift value");
3128 // The expression must be evaluatable as an immediate.
3129 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3131 Error(ImmLoc, "invalid immediate shift value");
3134 // Range check the immediate.
3135 // lsl, ror: 0 <= imm <= 31
3136 // lsr, asr: 0 <= imm <= 32
3137 Imm = CE->getValue();
3139 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3140 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3141 Error(ImmLoc, "immediate shift value out of range");
3144 // shift by zero is a nop. Always send it through as lsl.
3145 // ('as' compatibility)
3147 ShiftTy = ARM_AM::lsl;
3148 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3149 SMLoc L = Parser.getTok().getLoc();
3150 EndLoc = Parser.getTok().getEndLoc();
3151 ShiftReg = tryParseRegister();
3152 if (ShiftReg == -1) {
3153 Error(L, "expected immediate or register in shift operand");
3157 Error(Parser.getTok().getLoc(),
3158 "expected immediate or register in shift operand");
3163 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3164 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3168 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3175 /// Try to parse a register name. The token must be an Identifier when called.
3176 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3177 /// if there is a "writeback". 'true' if it's not a register.
3179 /// TODO this is likely to change to allow different register types and or to
3180 /// parse for a specific register type.
3181 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3182 MCAsmParser &Parser = getParser();
3183 const AsmToken &RegTok = Parser.getTok();
3184 int RegNo = tryParseRegister();
3188 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3189 RegTok.getEndLoc()));
3191 const AsmToken &ExclaimTok = Parser.getTok();
3192 if (ExclaimTok.is(AsmToken::Exclaim)) {
3193 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3194 ExclaimTok.getLoc()));
3195 Parser.Lex(); // Eat exclaim token
3199 // Also check for an index operand. This is only legal for vector registers,
3200 // but that'll get caught OK in operand matching, so we don't need to
3201 // explicitly filter everything else out here.
3202 if (Parser.getTok().is(AsmToken::LBrac)) {
3203 SMLoc SIdx = Parser.getTok().getLoc();
3204 Parser.Lex(); // Eat left bracket token.
3206 const MCExpr *ImmVal;
3207 if (getParser().parseExpression(ImmVal))
3209 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3211 return TokError("immediate value expected for vector index");
3213 if (Parser.getTok().isNot(AsmToken::RBrac))
3214 return Error(Parser.getTok().getLoc(), "']' expected");
3216 SMLoc E = Parser.getTok().getEndLoc();
3217 Parser.Lex(); // Eat right bracket token.
3219 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3227 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3228 /// instruction with a symbolic operand name.
3229 /// We accept "crN" syntax for GAS compatibility.
3230 /// <operand-name> ::= <prefix><number>
3231 /// If CoprocOp is 'c', then:
3232 /// <prefix> ::= c | cr
3233 /// If CoprocOp is 'p', then :
3235 /// <number> ::= integer in range [0, 15]
3236 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3237 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3239 if (Name.size() < 2 || Name[0] != CoprocOp)
3241 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3243 switch (Name.size()) {
3264 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3265 // However, old cores (v5/v6) did use them in that way.
3266 case '0': return 10;
3267 case '1': return 11;
3268 case '2': return 12;
3269 case '3': return 13;
3270 case '4': return 14;
3271 case '5': return 15;
3276 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3277 ARMAsmParser::OperandMatchResultTy
3278 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3279 MCAsmParser &Parser = getParser();
3280 SMLoc S = Parser.getTok().getLoc();
3281 const AsmToken &Tok = Parser.getTok();
3282 if (!Tok.is(AsmToken::Identifier))
3283 return MatchOperand_NoMatch;
3284 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3285 .Case("eq", ARMCC::EQ)
3286 .Case("ne", ARMCC::NE)
3287 .Case("hs", ARMCC::HS)
3288 .Case("cs", ARMCC::HS)
3289 .Case("lo", ARMCC::LO)
3290 .Case("cc", ARMCC::LO)
3291 .Case("mi", ARMCC::MI)
3292 .Case("pl", ARMCC::PL)
3293 .Case("vs", ARMCC::VS)
3294 .Case("vc", ARMCC::VC)
3295 .Case("hi", ARMCC::HI)
3296 .Case("ls", ARMCC::LS)
3297 .Case("ge", ARMCC::GE)
3298 .Case("lt", ARMCC::LT)
3299 .Case("gt", ARMCC::GT)
3300 .Case("le", ARMCC::LE)
3301 .Case("al", ARMCC::AL)
3304 return MatchOperand_NoMatch;
3305 Parser.Lex(); // Eat the token.
3307 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3309 return MatchOperand_Success;
3312 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3313 /// token must be an Identifier when called, and if it is a coprocessor
3314 /// number, the token is eaten and the operand is added to the operand list.
3315 ARMAsmParser::OperandMatchResultTy
3316 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3317 MCAsmParser &Parser = getParser();
3318 SMLoc S = Parser.getTok().getLoc();
3319 const AsmToken &Tok = Parser.getTok();
3320 if (Tok.isNot(AsmToken::Identifier))
3321 return MatchOperand_NoMatch;
3323 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3325 return MatchOperand_NoMatch;
3326 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3327 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3328 return MatchOperand_NoMatch;
3330 Parser.Lex(); // Eat identifier token.
3331 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3332 return MatchOperand_Success;
3335 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3336 /// token must be an Identifier when called, and if it is a coprocessor
3337 /// number, the token is eaten and the operand is added to the operand list.
3338 ARMAsmParser::OperandMatchResultTy
3339 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3340 MCAsmParser &Parser = getParser();
3341 SMLoc S = Parser.getTok().getLoc();
3342 const AsmToken &Tok = Parser.getTok();
3343 if (Tok.isNot(AsmToken::Identifier))
3344 return MatchOperand_NoMatch;
3346 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3348 return MatchOperand_NoMatch;
3350 Parser.Lex(); // Eat identifier token.
3351 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3352 return MatchOperand_Success;
3355 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3356 /// coproc_option : '{' imm0_255 '}'
3357 ARMAsmParser::OperandMatchResultTy
3358 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3359 MCAsmParser &Parser = getParser();
3360 SMLoc S = Parser.getTok().getLoc();
3362 // If this isn't a '{', this isn't a coprocessor immediate operand.
3363 if (Parser.getTok().isNot(AsmToken::LCurly))
3364 return MatchOperand_NoMatch;
3365 Parser.Lex(); // Eat the '{'
3368 SMLoc Loc = Parser.getTok().getLoc();
3369 if (getParser().parseExpression(Expr)) {
3370 Error(Loc, "illegal expression");
3371 return MatchOperand_ParseFail;
3373 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3374 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3375 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3376 return MatchOperand_ParseFail;
3378 int Val = CE->getValue();
3380 // Check for and consume the closing '}'
3381 if (Parser.getTok().isNot(AsmToken::RCurly))
3382 return MatchOperand_ParseFail;
3383 SMLoc E = Parser.getTok().getEndLoc();
3384 Parser.Lex(); // Eat the '}'
3386 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3387 return MatchOperand_Success;
3390 // For register list parsing, we need to map from raw GPR register numbering
3391 // to the enumeration values. The enumeration values aren't sorted by
3392 // register number due to our using "sp", "lr" and "pc" as canonical names.
3393 static unsigned getNextRegister(unsigned Reg) {
3394 // If this is a GPR, we need to do it manually, otherwise we can rely
3395 // on the sort ordering of the enumeration since the other reg-classes
3397 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3400 default: llvm_unreachable("Invalid GPR number!");
3401 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3402 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3403 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3404 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3405 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3406 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3407 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3408 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3412 // Return the low-subreg of a given Q register.
3413 static unsigned getDRegFromQReg(unsigned QReg) {
3415 default: llvm_unreachable("expected a Q register!");
3416 case ARM::Q0: return ARM::D0;
3417 case ARM::Q1: return ARM::D2;
3418 case ARM::Q2: return ARM::D4;
3419 case ARM::Q3: return ARM::D6;
3420 case ARM::Q4: return ARM::D8;
3421 case ARM::Q5: return ARM::D10;
3422 case ARM::Q6: return ARM::D12;
3423 case ARM::Q7: return ARM::D14;
3424 case ARM::Q8: return ARM::D16;
3425 case ARM::Q9: return ARM::D18;
3426 case ARM::Q10: return ARM::D20;
3427 case ARM::Q11: return ARM::D22;
3428 case ARM::Q12: return ARM::D24;
3429 case ARM::Q13: return ARM::D26;
3430 case ARM::Q14: return ARM::D28;
3431 case ARM::Q15: return ARM::D30;
3435 /// Parse a register list.
3436 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3437 MCAsmParser &Parser = getParser();
3438 assert(Parser.getTok().is(AsmToken::LCurly) &&
3439 "Token is not a Left Curly Brace");
3440 SMLoc S = Parser.getTok().getLoc();
3441 Parser.Lex(); // Eat '{' token.
3442 SMLoc RegLoc = Parser.getTok().getLoc();
3444 // Check the first register in the list to see what register class
3445 // this is a list of.
3446 int Reg = tryParseRegister();
3448 return Error(RegLoc, "register expected");
3450 // The reglist instructions have at most 16 registers, so reserve
3451 // space for that many.
3453 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3455 // Allow Q regs and just interpret them as the two D sub-registers.
3456 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3457 Reg = getDRegFromQReg(Reg);
3458 EReg = MRI->getEncodingValue(Reg);
3459 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3462 const MCRegisterClass *RC;
3463 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3464 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3465 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3466 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3467 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3468 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3470 return Error(RegLoc, "invalid register in register list");
3472 // Store the register.
3473 EReg = MRI->getEncodingValue(Reg);
3474 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3476 // This starts immediately after the first register token in the list,
3477 // so we can see either a comma or a minus (range separator) as a legal
3479 while (Parser.getTok().is(AsmToken::Comma) ||
3480 Parser.getTok().is(AsmToken::Minus)) {
3481 if (Parser.getTok().is(AsmToken::Minus)) {
3482 Parser.Lex(); // Eat the minus.
3483 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3484 int EndReg = tryParseRegister();
3486 return Error(AfterMinusLoc, "register expected");
3487 // Allow Q regs and just interpret them as the two D sub-registers.
3488 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3489 EndReg = getDRegFromQReg(EndReg) + 1;
3490 // If the register is the same as the start reg, there's nothing
3494 // The register must be in the same register class as the first.
3495 if (!RC->contains(EndReg))
3496 return Error(AfterMinusLoc, "invalid register in register list");
3497 // Ranges must go from low to high.
3498 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3499 return Error(AfterMinusLoc, "bad range in register list");
3501 // Add all the registers in the range to the register list.
3502 while (Reg != EndReg) {
3503 Reg = getNextRegister(Reg);
3504 EReg = MRI->getEncodingValue(Reg);
3505 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3509 Parser.Lex(); // Eat the comma.
3510 RegLoc = Parser.getTok().getLoc();
3512 const AsmToken RegTok = Parser.getTok();
3513 Reg = tryParseRegister();
3515 return Error(RegLoc, "register expected");
3516 // Allow Q regs and just interpret them as the two D sub-registers.
3517 bool isQReg = false;
3518 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3519 Reg = getDRegFromQReg(Reg);
3522 // The register must be in the same register class as the first.
3523 if (!RC->contains(Reg))
3524 return Error(RegLoc, "invalid register in register list");
3525 // List must be monotonically increasing.
3526 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3527 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3528 Warning(RegLoc, "register list not in ascending order");
3530 return Error(RegLoc, "register list not in ascending order");
3532 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3533 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3534 ") in register list");
3537 // VFP register lists must also be contiguous.
3538 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3540 return Error(RegLoc, "non-contiguous register range");
3541 EReg = MRI->getEncodingValue(Reg);
3542 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3544 EReg = MRI->getEncodingValue(++Reg);
3545 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3549 if (Parser.getTok().isNot(AsmToken::RCurly))
3550 return Error(Parser.getTok().getLoc(), "'}' expected");
3551 SMLoc E = Parser.getTok().getEndLoc();
3552 Parser.Lex(); // Eat '}' token.
3554 // Push the register list operand.
3555 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3557 // The ARM system instruction variants for LDM/STM have a '^' token here.
3558 if (Parser.getTok().is(AsmToken::Caret)) {
3559 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3560 Parser.Lex(); // Eat '^' token.
3566 // Helper function to parse the lane index for vector lists.
3567 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3568 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3569 MCAsmParser &Parser = getParser();
3570 Index = 0; // Always return a defined index value.
3571 if (Parser.getTok().is(AsmToken::LBrac)) {
3572 Parser.Lex(); // Eat the '['.
3573 if (Parser.getTok().is(AsmToken::RBrac)) {
3574 // "Dn[]" is the 'all lanes' syntax.
3575 LaneKind = AllLanes;
3576 EndLoc = Parser.getTok().getEndLoc();
3577 Parser.Lex(); // Eat the ']'.
3578 return MatchOperand_Success;
3581 // There's an optional '#' token here. Normally there wouldn't be, but
3582 // inline assemble puts one in, and it's friendly to accept that.
3583 if (Parser.getTok().is(AsmToken::Hash))
3584 Parser.Lex(); // Eat '#' or '$'.
3586 const MCExpr *LaneIndex;
3587 SMLoc Loc = Parser.getTok().getLoc();
3588 if (getParser().parseExpression(LaneIndex)) {
3589 Error(Loc, "illegal expression");
3590 return MatchOperand_ParseFail;
3592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3594 Error(Loc, "lane index must be empty or an integer");
3595 return MatchOperand_ParseFail;
3597 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3598 Error(Parser.getTok().getLoc(), "']' expected");
3599 return MatchOperand_ParseFail;
3601 EndLoc = Parser.getTok().getEndLoc();
3602 Parser.Lex(); // Eat the ']'.
3603 int64_t Val = CE->getValue();
3605 // FIXME: Make this range check context sensitive for .8, .16, .32.
3606 if (Val < 0 || Val > 7) {
3607 Error(Parser.getTok().getLoc(), "lane index out of range");
3608 return MatchOperand_ParseFail;
3611 LaneKind = IndexedLane;
3612 return MatchOperand_Success;
3615 return MatchOperand_Success;
3618 // parse a vector register list
3619 ARMAsmParser::OperandMatchResultTy
3620 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3621 MCAsmParser &Parser = getParser();
3622 VectorLaneTy LaneKind;
3624 SMLoc S = Parser.getTok().getLoc();
3625 // As an extension (to match gas), support a plain D register or Q register
3626 // (without encosing curly braces) as a single or double entry list,
3628 if (Parser.getTok().is(AsmToken::Identifier)) {
3629 SMLoc E = Parser.getTok().getEndLoc();
3630 int Reg = tryParseRegister();
3632 return MatchOperand_NoMatch;
3633 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3634 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3635 if (Res != MatchOperand_Success)
3639 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3642 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3646 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3651 return MatchOperand_Success;
3653 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3654 Reg = getDRegFromQReg(Reg);
3655 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3656 if (Res != MatchOperand_Success)
3660 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3661 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3662 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3665 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3666 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3667 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3671 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3676 return MatchOperand_Success;
3678 Error(S, "vector register expected");
3679 return MatchOperand_ParseFail;
3682 if (Parser.getTok().isNot(AsmToken::LCurly))
3683 return MatchOperand_NoMatch;
3685 Parser.Lex(); // Eat '{' token.
3686 SMLoc RegLoc = Parser.getTok().getLoc();
3688 int Reg = tryParseRegister();
3690 Error(RegLoc, "register expected");
3691 return MatchOperand_ParseFail;
3695 unsigned FirstReg = Reg;
3696 // The list is of D registers, but we also allow Q regs and just interpret
3697 // them as the two D sub-registers.
3698 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3699 FirstReg = Reg = getDRegFromQReg(Reg);
3700 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3701 // it's ambiguous with four-register single spaced.
3707 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3708 return MatchOperand_ParseFail;
3710 while (Parser.getTok().is(AsmToken::Comma) ||
3711 Parser.getTok().is(AsmToken::Minus)) {
3712 if (Parser.getTok().is(AsmToken::Minus)) {
3714 Spacing = 1; // Register range implies a single spaced list.
3715 else if (Spacing == 2) {
3716 Error(Parser.getTok().getLoc(),
3717 "sequential registers in double spaced list");
3718 return MatchOperand_ParseFail;
3720 Parser.Lex(); // Eat the minus.
3721 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3722 int EndReg = tryParseRegister();
3724 Error(AfterMinusLoc, "register expected");
3725 return MatchOperand_ParseFail;
3727 // Allow Q regs and just interpret them as the two D sub-registers.
3728 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3729 EndReg = getDRegFromQReg(EndReg) + 1;
3730 // If the register is the same as the start reg, there's nothing
3734 // The register must be in the same register class as the first.
3735 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3736 Error(AfterMinusLoc, "invalid register in register list");
3737 return MatchOperand_ParseFail;
3739 // Ranges must go from low to high.
3741 Error(AfterMinusLoc, "bad range in register list");
3742 return MatchOperand_ParseFail;
3744 // Parse the lane specifier if present.
3745 VectorLaneTy NextLaneKind;
3746 unsigned NextLaneIndex;
3747 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3748 MatchOperand_Success)
3749 return MatchOperand_ParseFail;
3750 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3751 Error(AfterMinusLoc, "mismatched lane index in register list");
3752 return MatchOperand_ParseFail;
3755 // Add all the registers in the range to the register list.
3756 Count += EndReg - Reg;
3760 Parser.Lex(); // Eat the comma.
3761 RegLoc = Parser.getTok().getLoc();
3763 Reg = tryParseRegister();
3765 Error(RegLoc, "register expected");
3766 return MatchOperand_ParseFail;
3768 // vector register lists must be contiguous.
3769 // It's OK to use the enumeration values directly here rather, as the
3770 // VFP register classes have the enum sorted properly.
3772 // The list is of D registers, but we also allow Q regs and just interpret
3773 // them as the two D sub-registers.
3774 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3776 Spacing = 1; // Register range implies a single spaced list.
3777 else if (Spacing == 2) {
3779 "invalid register in double-spaced list (must be 'D' register')");
3780 return MatchOperand_ParseFail;
3782 Reg = getDRegFromQReg(Reg);
3783 if (Reg != OldReg + 1) {
3784 Error(RegLoc, "non-contiguous register range");
3785 return MatchOperand_ParseFail;
3789 // Parse the lane specifier if present.
3790 VectorLaneTy NextLaneKind;
3791 unsigned NextLaneIndex;
3792 SMLoc LaneLoc = Parser.getTok().getLoc();
3793 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3794 MatchOperand_Success)
3795 return MatchOperand_ParseFail;
3796 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3797 Error(LaneLoc, "mismatched lane index in register list");
3798 return MatchOperand_ParseFail;
3802 // Normal D register.
3803 // Figure out the register spacing (single or double) of the list if
3804 // we don't know it already.
3806 Spacing = 1 + (Reg == OldReg + 2);
3808 // Just check that it's contiguous and keep going.
3809 if (Reg != OldReg + Spacing) {
3810 Error(RegLoc, "non-contiguous register range");
3811 return MatchOperand_ParseFail;
3814 // Parse the lane specifier if present.
3815 VectorLaneTy NextLaneKind;
3816 unsigned NextLaneIndex;
3817 SMLoc EndLoc = Parser.getTok().getLoc();
3818 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3819 return MatchOperand_ParseFail;
3820 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3821 Error(EndLoc, "mismatched lane index in register list");
3822 return MatchOperand_ParseFail;
3826 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3827 Error(Parser.getTok().getLoc(), "'}' expected");
3828 return MatchOperand_ParseFail;
3830 E = Parser.getTok().getEndLoc();
3831 Parser.Lex(); // Eat '}' token.
3835 // Two-register operands have been converted to the
3836 // composite register classes.
3838 const MCRegisterClass *RC = (Spacing == 1) ?
3839 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3840 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3841 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3844 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3845 (Spacing == 2), S, E));
3848 // Two-register operands have been converted to the
3849 // composite register classes.
3851 const MCRegisterClass *RC = (Spacing == 1) ?
3852 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3853 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3854 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3856 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3861 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3867 return MatchOperand_Success;
3870 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3871 ARMAsmParser::OperandMatchResultTy
3872 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3873 MCAsmParser &Parser = getParser();
3874 SMLoc S = Parser.getTok().getLoc();
3875 const AsmToken &Tok = Parser.getTok();
3878 if (Tok.is(AsmToken::Identifier)) {
3879 StringRef OptStr = Tok.getString();
3881 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3882 .Case("sy", ARM_MB::SY)
3883 .Case("st", ARM_MB::ST)
3884 .Case("ld", ARM_MB::LD)
3885 .Case("sh", ARM_MB::ISH)
3886 .Case("ish", ARM_MB::ISH)
3887 .Case("shst", ARM_MB::ISHST)
3888 .Case("ishst", ARM_MB::ISHST)
3889 .Case("ishld", ARM_MB::ISHLD)
3890 .Case("nsh", ARM_MB::NSH)
3891 .Case("un", ARM_MB::NSH)
3892 .Case("nshst", ARM_MB::NSHST)
3893 .Case("nshld", ARM_MB::NSHLD)
3894 .Case("unst", ARM_MB::NSHST)
3895 .Case("osh", ARM_MB::OSH)
3896 .Case("oshst", ARM_MB::OSHST)
3897 .Case("oshld", ARM_MB::OSHLD)
3900 // ishld, oshld, nshld and ld are only available from ARMv8.
3901 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3902 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3906 return MatchOperand_NoMatch;
3908 Parser.Lex(); // Eat identifier token.
3909 } else if (Tok.is(AsmToken::Hash) ||
3910 Tok.is(AsmToken::Dollar) ||
3911 Tok.is(AsmToken::Integer)) {
3912 if (Parser.getTok().isNot(AsmToken::Integer))
3913 Parser.Lex(); // Eat '#' or '$'.
3914 SMLoc Loc = Parser.getTok().getLoc();
3916 const MCExpr *MemBarrierID;
3917 if (getParser().parseExpression(MemBarrierID)) {
3918 Error(Loc, "illegal expression");
3919 return MatchOperand_ParseFail;
3922 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3924 Error(Loc, "constant expression expected");
3925 return MatchOperand_ParseFail;
3928 int Val = CE->getValue();
3930 Error(Loc, "immediate value out of range");
3931 return MatchOperand_ParseFail;
3934 Opt = ARM_MB::RESERVED_0 + Val;
3936 return MatchOperand_ParseFail;
3938 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3939 return MatchOperand_Success;
3942 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3943 ARMAsmParser::OperandMatchResultTy
3944 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3945 MCAsmParser &Parser = getParser();
3946 SMLoc S = Parser.getTok().getLoc();
3947 const AsmToken &Tok = Parser.getTok();
3950 if (Tok.is(AsmToken::Identifier)) {
3951 StringRef OptStr = Tok.getString();
3953 if (OptStr.equals_lower("sy"))
3956 return MatchOperand_NoMatch;
3958 Parser.Lex(); // Eat identifier token.
3959 } else if (Tok.is(AsmToken::Hash) ||
3960 Tok.is(AsmToken::Dollar) ||
3961 Tok.is(AsmToken::Integer)) {
3962 if (Parser.getTok().isNot(AsmToken::Integer))
3963 Parser.Lex(); // Eat '#' or '$'.
3964 SMLoc Loc = Parser.getTok().getLoc();
3966 const MCExpr *ISBarrierID;
3967 if (getParser().parseExpression(ISBarrierID)) {
3968 Error(Loc, "illegal expression");
3969 return MatchOperand_ParseFail;
3972 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3974 Error(Loc, "constant expression expected");
3975 return MatchOperand_ParseFail;
3978 int Val = CE->getValue();
3980 Error(Loc, "immediate value out of range");
3981 return MatchOperand_ParseFail;
3984 Opt = ARM_ISB::RESERVED_0 + Val;
3986 return MatchOperand_ParseFail;
3988 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3989 (ARM_ISB::InstSyncBOpt)Opt, S));
3990 return MatchOperand_Success;
3994 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3995 ARMAsmParser::OperandMatchResultTy
3996 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3997 MCAsmParser &Parser = getParser();
3998 SMLoc S = Parser.getTok().getLoc();
3999 const AsmToken &Tok = Parser.getTok();
4000 if (!Tok.is(AsmToken::Identifier))
4001 return MatchOperand_NoMatch;
4002 StringRef IFlagsStr = Tok.getString();
4004 // An iflags string of "none" is interpreted to mean that none of the AIF
4005 // bits are set. Not a terribly useful instruction, but a valid encoding.
4006 unsigned IFlags = 0;
4007 if (IFlagsStr != "none") {
4008 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4009 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
4010 .Case("a", ARM_PROC::A)
4011 .Case("i", ARM_PROC::I)
4012 .Case("f", ARM_PROC::F)
4015 // If some specific iflag is already set, it means that some letter is
4016 // present more than once, this is not acceptable.
4017 if (Flag == ~0U || (IFlags & Flag))
4018 return MatchOperand_NoMatch;
4024 Parser.Lex(); // Eat identifier token.
4025 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4026 return MatchOperand_Success;
4029 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4030 ARMAsmParser::OperandMatchResultTy
4031 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4032 MCAsmParser &Parser = getParser();
4033 SMLoc S = Parser.getTok().getLoc();
4034 const AsmToken &Tok = Parser.getTok();
4035 if (!Tok.is(AsmToken::Identifier))
4036 return MatchOperand_NoMatch;
4037 StringRef Mask = Tok.getString();
4040 // See ARMv6-M 10.1.1
4041 std::string Name = Mask.lower();
4042 unsigned FlagsVal = StringSwitch<unsigned>(Name)
4043 // Note: in the documentation:
4044 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
4045 // for MSR APSR_nzcvq.
4046 // but we do make it an alias here. This is so to get the "mask encoding"
4047 // bits correct on MSR APSR writes.
4049 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
4050 // should really only be allowed when writing a special register. Note
4051 // they get dropped in the MRS instruction reading a special register as
4052 // the SYSm field is only 8 bits.
4053 .Case("apsr", 0x800)
4054 .Case("apsr_nzcvq", 0x800)
4055 .Case("apsr_g", 0x400)
4056 .Case("apsr_nzcvqg", 0xc00)
4057 .Case("iapsr", 0x801)
4058 .Case("iapsr_nzcvq", 0x801)
4059 .Case("iapsr_g", 0x401)
4060 .Case("iapsr_nzcvqg", 0xc01)
4061 .Case("eapsr", 0x802)
4062 .Case("eapsr_nzcvq", 0x802)
4063 .Case("eapsr_g", 0x402)
4064 .Case("eapsr_nzcvqg", 0xc02)
4065 .Case("xpsr", 0x803)
4066 .Case("xpsr_nzcvq", 0x803)
4067 .Case("xpsr_g", 0x403)
4068 .Case("xpsr_nzcvqg", 0xc03)
4069 .Case("ipsr", 0x805)
4070 .Case("epsr", 0x806)
4071 .Case("iepsr", 0x807)
4074 .Case("primask", 0x810)
4075 .Case("basepri", 0x811)
4076 .Case("basepri_max", 0x812)
4077 .Case("faultmask", 0x813)
4078 .Case("control", 0x814)
4081 if (FlagsVal == ~0U)
4082 return MatchOperand_NoMatch;
4084 if (!hasThumb2DSP() && (FlagsVal & 0x400))
4085 // The _g and _nzcvqg versions are only valid if the DSP extension is
4087 return MatchOperand_NoMatch;
4089 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4090 // basepri, basepri_max and faultmask only valid for V7m.
4091 return MatchOperand_NoMatch;
4093 Parser.Lex(); // Eat identifier token.
4094 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4095 return MatchOperand_Success;
4098 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4099 size_t Start = 0, Next = Mask.find('_');
4100 StringRef Flags = "";
4101 std::string SpecReg = Mask.slice(Start, Next).lower();
4102 if (Next != StringRef::npos)
4103 Flags = Mask.slice(Next+1, Mask.size());
4105 // FlagsVal contains the complete mask:
4107 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4108 unsigned FlagsVal = 0;
4110 if (SpecReg == "apsr") {
4111 FlagsVal = StringSwitch<unsigned>(Flags)
4112 .Case("nzcvq", 0x8) // same as CPSR_f
4113 .Case("g", 0x4) // same as CPSR_s
4114 .Case("nzcvqg", 0xc) // same as CPSR_fs
4117 if (FlagsVal == ~0U) {
4119 return MatchOperand_NoMatch;
4121 FlagsVal = 8; // No flag
4123 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4124 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4125 if (Flags == "all" || Flags == "")
4127 for (int i = 0, e = Flags.size(); i != e; ++i) {
4128 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4135 // If some specific flag is already set, it means that some letter is
4136 // present more than once, this is not acceptable.
4137 if (FlagsVal == ~0U || (FlagsVal & Flag))
4138 return MatchOperand_NoMatch;
4141 } else // No match for special register.
4142 return MatchOperand_NoMatch;
4144 // Special register without flags is NOT equivalent to "fc" flags.
4145 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4146 // two lines would enable gas compatibility at the expense of breaking
4152 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4153 if (SpecReg == "spsr")
4156 Parser.Lex(); // Eat identifier token.
4157 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4158 return MatchOperand_Success;
4161 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4162 /// use in the MRS/MSR instructions added to support virtualization.
4163 ARMAsmParser::OperandMatchResultTy
4164 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4165 MCAsmParser &Parser = getParser();
4166 SMLoc S = Parser.getTok().getLoc();
4167 const AsmToken &Tok = Parser.getTok();
4168 if (!Tok.is(AsmToken::Identifier))
4169 return MatchOperand_NoMatch;
4170 StringRef RegName = Tok.getString();
4172 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4174 unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4175 .Case("r8_usr", 0x00)
4176 .Case("r9_usr", 0x01)
4177 .Case("r10_usr", 0x02)
4178 .Case("r11_usr", 0x03)
4179 .Case("r12_usr", 0x04)
4180 .Case("sp_usr", 0x05)
4181 .Case("lr_usr", 0x06)
4182 .Case("r8_fiq", 0x08)
4183 .Case("r9_fiq", 0x09)
4184 .Case("r10_fiq", 0x0a)
4185 .Case("r11_fiq", 0x0b)
4186 .Case("r12_fiq", 0x0c)
4187 .Case("sp_fiq", 0x0d)
4188 .Case("lr_fiq", 0x0e)
4189 .Case("lr_irq", 0x10)
4190 .Case("sp_irq", 0x11)
4191 .Case("lr_svc", 0x12)
4192 .Case("sp_svc", 0x13)
4193 .Case("lr_abt", 0x14)
4194 .Case("sp_abt", 0x15)
4195 .Case("lr_und", 0x16)
4196 .Case("sp_und", 0x17)
4197 .Case("lr_mon", 0x1c)
4198 .Case("sp_mon", 0x1d)
4199 .Case("elr_hyp", 0x1e)
4200 .Case("sp_hyp", 0x1f)
4201 .Case("spsr_fiq", 0x2e)
4202 .Case("spsr_irq", 0x30)
4203 .Case("spsr_svc", 0x32)
4204 .Case("spsr_abt", 0x34)
4205 .Case("spsr_und", 0x36)
4206 .Case("spsr_mon", 0x3c)
4207 .Case("spsr_hyp", 0x3e)
4210 if (Encoding == ~0U)
4211 return MatchOperand_NoMatch;
4213 Parser.Lex(); // Eat identifier token.
4214 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4215 return MatchOperand_Success;
4218 ARMAsmParser::OperandMatchResultTy
4219 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4221 MCAsmParser &Parser = getParser();
4222 const AsmToken &Tok = Parser.getTok();
4223 if (Tok.isNot(AsmToken::Identifier)) {
4224 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4225 return MatchOperand_ParseFail;
4227 StringRef ShiftName = Tok.getString();
4228 std::string LowerOp = Op.lower();
4229 std::string UpperOp = Op.upper();
4230 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4231 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4232 return MatchOperand_ParseFail;
4234 Parser.Lex(); // Eat shift type token.
4236 // There must be a '#' and a shift amount.
4237 if (Parser.getTok().isNot(AsmToken::Hash) &&
4238 Parser.getTok().isNot(AsmToken::Dollar)) {
4239 Error(Parser.getTok().getLoc(), "'#' expected");
4240 return MatchOperand_ParseFail;
4242 Parser.Lex(); // Eat hash token.
4244 const MCExpr *ShiftAmount;
4245 SMLoc Loc = Parser.getTok().getLoc();
4247 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4248 Error(Loc, "illegal expression");
4249 return MatchOperand_ParseFail;
4251 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4253 Error(Loc, "constant expression expected");
4254 return MatchOperand_ParseFail;
4256 int Val = CE->getValue();
4257 if (Val < Low || Val > High) {
4258 Error(Loc, "immediate value out of range");
4259 return MatchOperand_ParseFail;
4262 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4264 return MatchOperand_Success;
4267 ARMAsmParser::OperandMatchResultTy
4268 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4269 MCAsmParser &Parser = getParser();
4270 const AsmToken &Tok = Parser.getTok();
4271 SMLoc S = Tok.getLoc();
4272 if (Tok.isNot(AsmToken::Identifier)) {
4273 Error(S, "'be' or 'le' operand expected");
4274 return MatchOperand_ParseFail;
4276 int Val = StringSwitch<int>(Tok.getString().lower())
4280 Parser.Lex(); // Eat the token.
4283 Error(S, "'be' or 'le' operand expected");
4284 return MatchOperand_ParseFail;
4286 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4288 S, Tok.getEndLoc()));
4289 return MatchOperand_Success;
4292 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4293 /// instructions. Legal values are:
4294 /// lsl #n 'n' in [0,31]
4295 /// asr #n 'n' in [1,32]
4296 /// n == 32 encoded as n == 0.
4297 ARMAsmParser::OperandMatchResultTy
4298 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4299 MCAsmParser &Parser = getParser();
4300 const AsmToken &Tok = Parser.getTok();
4301 SMLoc S = Tok.getLoc();
4302 if (Tok.isNot(AsmToken::Identifier)) {
4303 Error(S, "shift operator 'asr' or 'lsl' expected");
4304 return MatchOperand_ParseFail;
4306 StringRef ShiftName = Tok.getString();
4308 if (ShiftName == "lsl" || ShiftName == "LSL")
4310 else if (ShiftName == "asr" || ShiftName == "ASR")
4313 Error(S, "shift operator 'asr' or 'lsl' expected");
4314 return MatchOperand_ParseFail;
4316 Parser.Lex(); // Eat the operator.
4318 // A '#' and a shift amount.
4319 if (Parser.getTok().isNot(AsmToken::Hash) &&
4320 Parser.getTok().isNot(AsmToken::Dollar)) {
4321 Error(Parser.getTok().getLoc(), "'#' expected");
4322 return MatchOperand_ParseFail;
4324 Parser.Lex(); // Eat hash token.
4325 SMLoc ExLoc = Parser.getTok().getLoc();
4327 const MCExpr *ShiftAmount;
4329 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4330 Error(ExLoc, "malformed shift expression");
4331 return MatchOperand_ParseFail;
4333 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4335 Error(ExLoc, "shift amount must be an immediate");
4336 return MatchOperand_ParseFail;
4339 int64_t Val = CE->getValue();
4341 // Shift amount must be in [1,32]
4342 if (Val < 1 || Val > 32) {
4343 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4344 return MatchOperand_ParseFail;
4346 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4347 if (isThumb() && Val == 32) {
4348 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4349 return MatchOperand_ParseFail;
4351 if (Val == 32) Val = 0;
4353 // Shift amount must be in [1,32]
4354 if (Val < 0 || Val > 31) {
4355 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4356 return MatchOperand_ParseFail;
4360 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4362 return MatchOperand_Success;
4365 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4366 /// of instructions. Legal values are:
4367 /// ror #n 'n' in {0, 8, 16, 24}
4368 ARMAsmParser::OperandMatchResultTy
4369 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4370 MCAsmParser &Parser = getParser();
4371 const AsmToken &Tok = Parser.getTok();
4372 SMLoc S = Tok.getLoc();
4373 if (Tok.isNot(AsmToken::Identifier))
4374 return MatchOperand_NoMatch;
4375 StringRef ShiftName = Tok.getString();
4376 if (ShiftName != "ror" && ShiftName != "ROR")
4377 return MatchOperand_NoMatch;
4378 Parser.Lex(); // Eat the operator.
4380 // A '#' and a rotate amount.
4381 if (Parser.getTok().isNot(AsmToken::Hash) &&
4382 Parser.getTok().isNot(AsmToken::Dollar)) {
4383 Error(Parser.getTok().getLoc(), "'#' expected");
4384 return MatchOperand_ParseFail;
4386 Parser.Lex(); // Eat hash token.
4387 SMLoc ExLoc = Parser.getTok().getLoc();
4389 const MCExpr *ShiftAmount;
4391 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4392 Error(ExLoc, "malformed rotate expression");
4393 return MatchOperand_ParseFail;
4395 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4397 Error(ExLoc, "rotate amount must be an immediate");
4398 return MatchOperand_ParseFail;
4401 int64_t Val = CE->getValue();
4402 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4403 // normally, zero is represented in asm by omitting the rotate operand
4405 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4406 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4407 return MatchOperand_ParseFail;
4410 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4412 return MatchOperand_Success;
4415 ARMAsmParser::OperandMatchResultTy
4416 ARMAsmParser::parseModImm(OperandVector &Operands) {
4417 MCAsmParser &Parser = getParser();
4418 MCAsmLexer &Lexer = getLexer();
4421 SMLoc S = Parser.getTok().getLoc();
4423 // 1) A mod_imm operand can appear in the place of a register name:
4425 // add r0, r0, #mod_imm
4426 // to correctly handle the latter, we bail out as soon as we see an
4429 // 2) Similarly, we do not want to parse into complex operands:
4431 // mov r0, :lower16:(_foo)
4432 if (Parser.getTok().is(AsmToken::Identifier) ||
4433 Parser.getTok().is(AsmToken::Colon))
4434 return MatchOperand_NoMatch;
4436 // Hash (dollar) is optional as per the ARMARM
4437 if (Parser.getTok().is(AsmToken::Hash) ||
4438 Parser.getTok().is(AsmToken::Dollar)) {
4439 // Avoid parsing into complex operands (#:)
4440 if (Lexer.peekTok().is(AsmToken::Colon))
4441 return MatchOperand_NoMatch;
4443 // Eat the hash (dollar)
4448 Sx1 = Parser.getTok().getLoc();
4449 const MCExpr *Imm1Exp;
4450 if (getParser().parseExpression(Imm1Exp, Ex1)) {
4451 Error(Sx1, "malformed expression");
4452 return MatchOperand_ParseFail;
4455 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4458 // Immediate must fit within 32-bits
4459 Imm1 = CE->getValue();
4460 if (Imm1 < INT32_MIN || Imm1 > UINT32_MAX) {
4461 Error(Sx1, "immediate operand must be representable with 32 bits");
4462 return MatchOperand_ParseFail;
4465 int Enc = ARM_AM::getSOImmVal(Imm1);
4466 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4468 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4471 return MatchOperand_Success;
4474 // We have parsed an immediate which is not for us, fallback to a plain
4475 // immediate. This can happen for instruction aliases. For an example,
4476 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4477 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4478 // instruction with a mod_imm operand. The alias is defined such that the
4479 // parser method is shared, that's why we have to do this here.
4480 if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4481 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4482 return MatchOperand_Success;
4485 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4486 // MCFixup). Fallback to a plain immediate.
4487 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4488 return MatchOperand_Success;
4491 // From this point onward, we expect the input to be a (#bits, #rot) pair
4492 if (Parser.getTok().isNot(AsmToken::Comma)) {
4493 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4494 return MatchOperand_ParseFail;
4498 Error(Sx1, "immediate operand must a number in the range [0, 255]");
4499 return MatchOperand_ParseFail;
4507 Sx2 = Parser.getTok().getLoc();
4509 // Eat the optional hash (dollar)
4510 if (Parser.getTok().is(AsmToken::Hash) ||
4511 Parser.getTok().is(AsmToken::Dollar))
4514 const MCExpr *Imm2Exp;
4515 if (getParser().parseExpression(Imm2Exp, Ex2)) {
4516 Error(Sx2, "malformed expression");
4517 return MatchOperand_ParseFail;
4520 CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4523 Imm2 = CE->getValue();
4524 if (!(Imm2 & ~0x1E)) {
4526 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4527 return MatchOperand_Success;
4529 Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4530 return MatchOperand_ParseFail;
4532 Error(Sx2, "constant expression expected");
4533 return MatchOperand_ParseFail;
4537 ARMAsmParser::OperandMatchResultTy
4538 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4539 MCAsmParser &Parser = getParser();
4540 SMLoc S = Parser.getTok().getLoc();
4541 // The bitfield descriptor is really two operands, the LSB and the width.
4542 if (Parser.getTok().isNot(AsmToken::Hash) &&
4543 Parser.getTok().isNot(AsmToken::Dollar)) {
4544 Error(Parser.getTok().getLoc(), "'#' expected");
4545 return MatchOperand_ParseFail;
4547 Parser.Lex(); // Eat hash token.
4549 const MCExpr *LSBExpr;
4550 SMLoc E = Parser.getTok().getLoc();
4551 if (getParser().parseExpression(LSBExpr)) {
4552 Error(E, "malformed immediate expression");
4553 return MatchOperand_ParseFail;
4555 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4557 Error(E, "'lsb' operand must be an immediate");
4558 return MatchOperand_ParseFail;
4561 int64_t LSB = CE->getValue();
4562 // The LSB must be in the range [0,31]
4563 if (LSB < 0 || LSB > 31) {
4564 Error(E, "'lsb' operand must be in the range [0,31]");
4565 return MatchOperand_ParseFail;
4567 E = Parser.getTok().getLoc();
4569 // Expect another immediate operand.
4570 if (Parser.getTok().isNot(AsmToken::Comma)) {
4571 Error(Parser.getTok().getLoc(), "too few operands");
4572 return MatchOperand_ParseFail;
4574 Parser.Lex(); // Eat hash token.
4575 if (Parser.getTok().isNot(AsmToken::Hash) &&
4576 Parser.getTok().isNot(AsmToken::Dollar)) {
4577 Error(Parser.getTok().getLoc(), "'#' expected");
4578 return MatchOperand_ParseFail;
4580 Parser.Lex(); // Eat hash token.
4582 const MCExpr *WidthExpr;
4584 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4585 Error(E, "malformed immediate expression");
4586 return MatchOperand_ParseFail;
4588 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4590 Error(E, "'width' operand must be an immediate");
4591 return MatchOperand_ParseFail;
4594 int64_t Width = CE->getValue();
4595 // The LSB must be in the range [1,32-lsb]
4596 if (Width < 1 || Width > 32 - LSB) {
4597 Error(E, "'width' operand must be in the range [1,32-lsb]");
4598 return MatchOperand_ParseFail;
4601 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4603 return MatchOperand_Success;
4606 ARMAsmParser::OperandMatchResultTy
4607 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4608 // Check for a post-index addressing register operand. Specifically:
4609 // postidx_reg := '+' register {, shift}
4610 // | '-' register {, shift}
4611 // | register {, shift}
4613 // This method must return MatchOperand_NoMatch without consuming any tokens
4614 // in the case where there is no match, as other alternatives take other
4616 MCAsmParser &Parser = getParser();
4617 AsmToken Tok = Parser.getTok();
4618 SMLoc S = Tok.getLoc();
4619 bool haveEaten = false;
4621 if (Tok.is(AsmToken::Plus)) {
4622 Parser.Lex(); // Eat the '+' token.
4624 } else if (Tok.is(AsmToken::Minus)) {
4625 Parser.Lex(); // Eat the '-' token.
4630 SMLoc E = Parser.getTok().getEndLoc();
4631 int Reg = tryParseRegister();
4634 return MatchOperand_NoMatch;
4635 Error(Parser.getTok().getLoc(), "register expected");
4636 return MatchOperand_ParseFail;
4639 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4640 unsigned ShiftImm = 0;
4641 if (Parser.getTok().is(AsmToken::Comma)) {
4642 Parser.Lex(); // Eat the ','.
4643 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4644 return MatchOperand_ParseFail;
4646 // FIXME: Only approximates end...may include intervening whitespace.
4647 E = Parser.getTok().getLoc();
4650 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4653 return MatchOperand_Success;
4656 ARMAsmParser::OperandMatchResultTy
4657 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4658 // Check for a post-index addressing register operand. Specifically:
4659 // am3offset := '+' register
4666 // This method must return MatchOperand_NoMatch without consuming any tokens
4667 // in the case where there is no match, as other alternatives take other
4669 MCAsmParser &Parser = getParser();
4670 AsmToken Tok = Parser.getTok();
4671 SMLoc S = Tok.getLoc();
4673 // Do immediates first, as we always parse those if we have a '#'.
4674 if (Parser.getTok().is(AsmToken::Hash) ||
4675 Parser.getTok().is(AsmToken::Dollar)) {
4676 Parser.Lex(); // Eat '#' or '$'.
4677 // Explicitly look for a '-', as we need to encode negative zero
4679 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4680 const MCExpr *Offset;
4682 if (getParser().parseExpression(Offset, E))
4683 return MatchOperand_ParseFail;
4684 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4686 Error(S, "constant expression expected");
4687 return MatchOperand_ParseFail;
4689 // Negative zero is encoded as the flag value INT32_MIN.
4690 int32_t Val = CE->getValue();
4691 if (isNegative && Val == 0)
4695 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4697 return MatchOperand_Success;
4701 bool haveEaten = false;
4703 if (Tok.is(AsmToken::Plus)) {
4704 Parser.Lex(); // Eat the '+' token.
4706 } else if (Tok.is(AsmToken::Minus)) {
4707 Parser.Lex(); // Eat the '-' token.
4712 Tok = Parser.getTok();
4713 int Reg = tryParseRegister();
4716 return MatchOperand_NoMatch;
4717 Error(Tok.getLoc(), "register expected");
4718 return MatchOperand_ParseFail;
4721 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4722 0, S, Tok.getEndLoc()));
4724 return MatchOperand_Success;
4727 /// Convert parsed operands to MCInst. Needed here because this instruction
4728 /// only has two register operands, but multiplication is commutative so
4729 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4730 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4731 const OperandVector &Operands) {
4732 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4733 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4734 // If we have a three-operand form, make sure to set Rn to be the operand
4735 // that isn't the same as Rd.
4737 if (Operands.size() == 6 &&
4738 ((ARMOperand &)*Operands[4]).getReg() ==
4739 ((ARMOperand &)*Operands[3]).getReg())
4741 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4742 Inst.addOperand(Inst.getOperand(0));
4743 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4746 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4747 const OperandVector &Operands) {
4748 int CondOp = -1, ImmOp = -1;
4749 switch(Inst.getOpcode()) {
4751 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4754 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4756 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4758 // first decide whether or not the branch should be conditional
4759 // by looking at it's location relative to an IT block
4761 // inside an IT block we cannot have any conditional branches. any
4762 // such instructions needs to be converted to unconditional form
4763 switch(Inst.getOpcode()) {
4764 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4765 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4768 // outside IT blocks we can only have unconditional branches with AL
4769 // condition code or conditional branches with non-AL condition code
4770 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4771 switch(Inst.getOpcode()) {
4774 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4778 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4783 // now decide on encoding size based on branch target range
4784 switch(Inst.getOpcode()) {
4785 // classify tB as either t2B or t1B based on range of immediate operand
4787 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4788 if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4789 Inst.setOpcode(ARM::t2B);
4792 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4794 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4795 if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4796 Inst.setOpcode(ARM::t2Bcc);
4800 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4801 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4804 /// Parse an ARM memory expression, return false if successful else return true
4805 /// or an error. The first token must be a '[' when called.
4806 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4807 MCAsmParser &Parser = getParser();
4809 assert(Parser.getTok().is(AsmToken::LBrac) &&
4810 "Token is not a Left Bracket");
4811 S = Parser.getTok().getLoc();
4812 Parser.Lex(); // Eat left bracket token.
4814 const AsmToken &BaseRegTok = Parser.getTok();
4815 int BaseRegNum = tryParseRegister();
4816 if (BaseRegNum == -1)
4817 return Error(BaseRegTok.getLoc(), "register expected");
4819 // The next token must either be a comma, a colon or a closing bracket.
4820 const AsmToken &Tok = Parser.getTok();
4821 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4822 !Tok.is(AsmToken::RBrac))
4823 return Error(Tok.getLoc(), "malformed memory operand");
4825 if (Tok.is(AsmToken::RBrac)) {
4826 E = Tok.getEndLoc();
4827 Parser.Lex(); // Eat right bracket token.
4829 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4830 ARM_AM::no_shift, 0, 0, false,
4833 // If there's a pre-indexing writeback marker, '!', just add it as a token
4834 // operand. It's rather odd, but syntactically valid.
4835 if (Parser.getTok().is(AsmToken::Exclaim)) {
4836 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4837 Parser.Lex(); // Eat the '!'.
4843 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4844 "Lost colon or comma in memory operand?!");
4845 if (Tok.is(AsmToken::Comma)) {
4846 Parser.Lex(); // Eat the comma.
4849 // If we have a ':', it's an alignment specifier.
4850 if (Parser.getTok().is(AsmToken::Colon)) {
4851 Parser.Lex(); // Eat the ':'.
4852 E = Parser.getTok().getLoc();
4853 SMLoc AlignmentLoc = Tok.getLoc();
4856 if (getParser().parseExpression(Expr))
4859 // The expression has to be a constant. Memory references with relocations
4860 // don't come through here, as they use the <label> forms of the relevant
4862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4864 return Error (E, "constant expression expected");
4867 switch (CE->getValue()) {
4870 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4871 case 16: Align = 2; break;
4872 case 32: Align = 4; break;
4873 case 64: Align = 8; break;
4874 case 128: Align = 16; break;
4875 case 256: Align = 32; break;
4878 // Now we should have the closing ']'
4879 if (Parser.getTok().isNot(AsmToken::RBrac))
4880 return Error(Parser.getTok().getLoc(), "']' expected");
4881 E = Parser.getTok().getEndLoc();
4882 Parser.Lex(); // Eat right bracket token.
4884 // Don't worry about range checking the value here. That's handled by
4885 // the is*() predicates.
4886 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4887 ARM_AM::no_shift, 0, Align,
4888 false, S, E, AlignmentLoc));
4890 // If there's a pre-indexing writeback marker, '!', just add it as a token
4892 if (Parser.getTok().is(AsmToken::Exclaim)) {
4893 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4894 Parser.Lex(); // Eat the '!'.
4900 // If we have a '#', it's an immediate offset, else assume it's a register
4901 // offset. Be friendly and also accept a plain integer (without a leading
4902 // hash) for gas compatibility.
4903 if (Parser.getTok().is(AsmToken::Hash) ||
4904 Parser.getTok().is(AsmToken::Dollar) ||
4905 Parser.getTok().is(AsmToken::Integer)) {
4906 if (Parser.getTok().isNot(AsmToken::Integer))
4907 Parser.Lex(); // Eat '#' or '$'.
4908 E = Parser.getTok().getLoc();
4910 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4911 const MCExpr *Offset;
4912 if (getParser().parseExpression(Offset))
4915 // The expression has to be a constant. Memory references with relocations
4916 // don't come through here, as they use the <label> forms of the relevant
4918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4920 return Error (E, "constant expression expected");
4922 // If the constant was #-0, represent it as INT32_MIN.
4923 int32_t Val = CE->getValue();
4924 if (isNegative && Val == 0)
4925 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4927 // Now we should have the closing ']'
4928 if (Parser.getTok().isNot(AsmToken::RBrac))
4929 return Error(Parser.getTok().getLoc(), "']' expected");
4930 E = Parser.getTok().getEndLoc();
4931 Parser.Lex(); // Eat right bracket token.
4933 // Don't worry about range checking the value here. That's handled by
4934 // the is*() predicates.
4935 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4936 ARM_AM::no_shift, 0, 0,
4939 // If there's a pre-indexing writeback marker, '!', just add it as a token
4941 if (Parser.getTok().is(AsmToken::Exclaim)) {
4942 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4943 Parser.Lex(); // Eat the '!'.
4949 // The register offset is optionally preceded by a '+' or '-'
4950 bool isNegative = false;
4951 if (Parser.getTok().is(AsmToken::Minus)) {
4953 Parser.Lex(); // Eat the '-'.
4954 } else if (Parser.getTok().is(AsmToken::Plus)) {
4956 Parser.Lex(); // Eat the '+'.
4959 E = Parser.getTok().getLoc();
4960 int OffsetRegNum = tryParseRegister();
4961 if (OffsetRegNum == -1)
4962 return Error(E, "register expected");
4964 // If there's a shift operator, handle it.
4965 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4966 unsigned ShiftImm = 0;
4967 if (Parser.getTok().is(AsmToken::Comma)) {
4968 Parser.Lex(); // Eat the ','.
4969 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4973 // Now we should have the closing ']'
4974 if (Parser.getTok().isNot(AsmToken::RBrac))
4975 return Error(Parser.getTok().getLoc(), "']' expected");
4976 E = Parser.getTok().getEndLoc();
4977 Parser.Lex(); // Eat right bracket token.
4979 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4980 ShiftType, ShiftImm, 0, isNegative,
4983 // If there's a pre-indexing writeback marker, '!', just add it as a token
4985 if (Parser.getTok().is(AsmToken::Exclaim)) {
4986 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4987 Parser.Lex(); // Eat the '!'.
4993 /// parseMemRegOffsetShift - one of these two:
4994 /// ( lsl | lsr | asr | ror ) , # shift_amount
4996 /// return true if it parses a shift otherwise it returns false.
4997 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4999 MCAsmParser &Parser = getParser();
5000 SMLoc Loc = Parser.getTok().getLoc();
5001 const AsmToken &Tok = Parser.getTok();
5002 if (Tok.isNot(AsmToken::Identifier))
5004 StringRef ShiftName = Tok.getString();
5005 if (ShiftName == "lsl" || ShiftName == "LSL" ||
5006 ShiftName == "asl" || ShiftName == "ASL")
5008 else if (ShiftName == "lsr" || ShiftName == "LSR")
5010 else if (ShiftName == "asr" || ShiftName == "ASR")
5012 else if (ShiftName == "ror" || ShiftName == "ROR")
5014 else if (ShiftName == "rrx" || ShiftName == "RRX")
5017 return Error(Loc, "illegal shift operator");
5018 Parser.Lex(); // Eat shift type token.
5020 // rrx stands alone.
5022 if (St != ARM_AM::rrx) {
5023 Loc = Parser.getTok().getLoc();
5024 // A '#' and a shift amount.
5025 const AsmToken &HashTok = Parser.getTok();
5026 if (HashTok.isNot(AsmToken::Hash) &&
5027 HashTok.isNot(AsmToken::Dollar))
5028 return Error(HashTok.getLoc(), "'#' expected");
5029 Parser.Lex(); // Eat hash token.
5032 if (getParser().parseExpression(Expr))
5034 // Range check the immediate.
5035 // lsl, ror: 0 <= imm <= 31
5036 // lsr, asr: 0 <= imm <= 32
5037 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5039 return Error(Loc, "shift amount must be an immediate");
5040 int64_t Imm = CE->getValue();
5042 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5043 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5044 return Error(Loc, "immediate shift value out of range");
5045 // If <ShiftTy> #0, turn it into a no_shift.
5048 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5057 /// parseFPImm - A floating point immediate expression operand.
5058 ARMAsmParser::OperandMatchResultTy
5059 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5060 MCAsmParser &Parser = getParser();
5061 // Anything that can accept a floating point constant as an operand
5062 // needs to go through here, as the regular parseExpression is
5065 // This routine still creates a generic Immediate operand, containing
5066 // a bitcast of the 64-bit floating point value. The various operands
5067 // that accept floats can check whether the value is valid for them
5068 // via the standard is*() predicates.
5070 SMLoc S = Parser.getTok().getLoc();
5072 if (Parser.getTok().isNot(AsmToken::Hash) &&
5073 Parser.getTok().isNot(AsmToken::Dollar))
5074 return MatchOperand_NoMatch;
5076 // Disambiguate the VMOV forms that can accept an FP immediate.
5077 // vmov.f32 <sreg>, #imm
5078 // vmov.f64 <dreg>, #imm
5079 // vmov.f32 <dreg>, #imm @ vector f32x2
5080 // vmov.f32 <qreg>, #imm @ vector f32x4
5082 // There are also the NEON VMOV instructions which expect an
5083 // integer constant. Make sure we don't try to parse an FPImm
5085 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5086 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5087 bool isVmovf = TyOp.isToken() &&
5088 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
5089 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5090 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5091 Mnemonic.getToken() == "fconsts");
5092 if (!(isVmovf || isFconst))
5093 return MatchOperand_NoMatch;
5095 Parser.Lex(); // Eat '#' or '$'.
5097 // Handle negation, as that still comes through as a separate token.
5098 bool isNegative = false;
5099 if (Parser.getTok().is(AsmToken::Minus)) {
5103 const AsmToken &Tok = Parser.getTok();
5104 SMLoc Loc = Tok.getLoc();
5105 if (Tok.is(AsmToken::Real) && isVmovf) {
5106 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
5107 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5108 // If we had a '-' in front, toggle the sign bit.
5109 IntVal ^= (uint64_t)isNegative << 31;
5110 Parser.Lex(); // Eat the token.
5111 Operands.push_back(ARMOperand::CreateImm(
5112 MCConstantExpr::Create(IntVal, getContext()),
5113 S, Parser.getTok().getLoc()));
5114 return MatchOperand_Success;
5116 // Also handle plain integers. Instructions which allow floating point
5117 // immediates also allow a raw encoded 8-bit value.
5118 if (Tok.is(AsmToken::Integer) && isFconst) {
5119 int64_t Val = Tok.getIntVal();
5120 Parser.Lex(); // Eat the token.
5121 if (Val > 255 || Val < 0) {
5122 Error(Loc, "encoded floating point value out of range");
5123 return MatchOperand_ParseFail;
5125 float RealVal = ARM_AM::getFPImmFloat(Val);
5126 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5128 Operands.push_back(ARMOperand::CreateImm(
5129 MCConstantExpr::Create(Val, getContext()), S,
5130 Parser.getTok().getLoc()));
5131 return MatchOperand_Success;
5134 Error(Loc, "invalid floating point immediate");
5135 return MatchOperand_ParseFail;
5138 /// Parse a arm instruction operand. For now this parses the operand regardless
5139 /// of the mnemonic.
5140 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5141 MCAsmParser &Parser = getParser();
5144 // Check if the current operand has a custom associated parser, if so, try to
5145 // custom parse the operand, or fallback to the general approach.
5146 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5147 if (ResTy == MatchOperand_Success)
5149 // If there wasn't a custom match, try the generic matcher below. Otherwise,
5150 // there was a match, but an error occurred, in which case, just return that
5151 // the operand parsing failed.
5152 if (ResTy == MatchOperand_ParseFail)
5155 switch (getLexer().getKind()) {
5157 Error(Parser.getTok().getLoc(), "unexpected token in operand");
5159 case AsmToken::Identifier: {
5160 // If we've seen a branch mnemonic, the next operand must be a label. This
5161 // is true even if the label is a register name. So "br r1" means branch to
5163 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5165 if (!tryParseRegisterWithWriteBack(Operands))
5167 int Res = tryParseShiftRegister(Operands);
5168 if (Res == 0) // success
5170 else if (Res == -1) // irrecoverable error
5172 // If this is VMRS, check for the apsr_nzcv operand.
5173 if (Mnemonic == "vmrs" &&
5174 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5175 S = Parser.getTok().getLoc();
5177 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5182 // Fall though for the Identifier case that is not a register or a
5185 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
5186 case AsmToken::Integer: // things like 1f and 2b as a branch targets
5187 case AsmToken::String: // quoted label names.
5188 case AsmToken::Dot: { // . as a branch target
5189 // This was not a register so parse other operands that start with an
5190 // identifier (like labels) as expressions and create them as immediates.
5191 const MCExpr *IdVal;
5192 S = Parser.getTok().getLoc();
5193 if (getParser().parseExpression(IdVal))
5195 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5196 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5199 case AsmToken::LBrac:
5200 return parseMemory(Operands);
5201 case AsmToken::LCurly:
5202 return parseRegisterList(Operands);
5203 case AsmToken::Dollar:
5204 case AsmToken::Hash: {
5205 // #42 -> immediate.
5206 S = Parser.getTok().getLoc();
5209 if (Parser.getTok().isNot(AsmToken::Colon)) {
5210 bool isNegative = Parser.getTok().is(AsmToken::Minus);
5211 const MCExpr *ImmVal;
5212 if (getParser().parseExpression(ImmVal))
5214 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5216 int32_t Val = CE->getValue();
5217 if (isNegative && Val == 0)
5218 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
5220 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5221 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5223 // There can be a trailing '!' on operands that we want as a separate
5224 // '!' Token operand. Handle that here. For example, the compatibility
5225 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5226 if (Parser.getTok().is(AsmToken::Exclaim)) {
5227 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5228 Parser.getTok().getLoc()));
5229 Parser.Lex(); // Eat exclaim token
5233 // w/ a ':' after the '#', it's just like a plain ':'.
5236 case AsmToken::Colon: {
5237 // ":lower16:" and ":upper16:" expression prefixes
5238 // FIXME: Check it's an expression prefix,
5239 // e.g. (FOO - :lower16:BAR) isn't legal.
5240 ARMMCExpr::VariantKind RefKind;
5241 if (parsePrefix(RefKind))
5244 const MCExpr *SubExprVal;
5245 if (getParser().parseExpression(SubExprVal))
5248 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
5250 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5251 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5254 case AsmToken::Equal: {
5255 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5256 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
5258 Parser.Lex(); // Eat '='
5259 const MCExpr *SubExprVal;
5260 if (getParser().parseExpression(SubExprVal))
5262 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5264 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5265 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5271 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5272 // :lower16: and :upper16:.
5273 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5274 MCAsmParser &Parser = getParser();
5275 RefKind = ARMMCExpr::VK_ARM_None;
5277 // consume an optional '#' (GNU compatibility)
5278 if (getLexer().is(AsmToken::Hash))
5281 // :lower16: and :upper16: modifiers
5282 assert(getLexer().is(AsmToken::Colon) && "expected a :");
5283 Parser.Lex(); // Eat ':'
5285 if (getLexer().isNot(AsmToken::Identifier)) {
5286 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5290 StringRef IDVal = Parser.getTok().getIdentifier();
5291 if (IDVal == "lower16") {
5292 RefKind = ARMMCExpr::VK_ARM_LO16;
5293 } else if (IDVal == "upper16") {
5294 RefKind = ARMMCExpr::VK_ARM_HI16;
5296 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5301 if (getLexer().isNot(AsmToken::Colon)) {
5302 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5305 Parser.Lex(); // Eat the last ':'
5309 /// \brief Given a mnemonic, split out possible predication code and carry
5310 /// setting letters to form a canonical mnemonic and flags.
5312 // FIXME: Would be nice to autogen this.
5313 // FIXME: This is a bit of a maze of special cases.
5314 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5315 unsigned &PredicationCode,
5317 unsigned &ProcessorIMod,
5318 StringRef &ITMask) {
5319 PredicationCode = ARMCC::AL;
5320 CarrySetting = false;
5323 // Ignore some mnemonics we know aren't predicated forms.
5325 // FIXME: Would be nice to autogen this.
5326 if ((Mnemonic == "movs" && isThumb()) ||
5327 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
5328 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
5329 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
5330 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
5331 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
5332 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
5333 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
5334 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5335 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5336 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
5337 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5338 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5339 Mnemonic.startswith("vsel"))
5342 // First, split out any predication code. Ignore mnemonics we know aren't
5343 // predicated but do have a carry-set and so weren't caught above.
5344 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5345 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5346 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5347 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5348 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5349 .Case("eq", ARMCC::EQ)
5350 .Case("ne", ARMCC::NE)
5351 .Case("hs", ARMCC::HS)
5352 .Case("cs", ARMCC::HS)
5353 .Case("lo", ARMCC::LO)
5354 .Case("cc", ARMCC::LO)
5355 .Case("mi", ARMCC::MI)
5356 .Case("pl", ARMCC::PL)
5357 .Case("vs", ARMCC::VS)
5358 .Case("vc", ARMCC::VC)
5359 .Case("hi", ARMCC::HI)
5360 .Case("ls", ARMCC::LS)
5361 .Case("ge", ARMCC::GE)
5362 .Case("lt", ARMCC::LT)
5363 .Case("gt", ARMCC::GT)
5364 .Case("le", ARMCC::LE)
5365 .Case("al", ARMCC::AL)
5368 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5369 PredicationCode = CC;
5373 // Next, determine if we have a carry setting bit. We explicitly ignore all
5374 // the instructions we know end in 's'.
5375 if (Mnemonic.endswith("s") &&
5376 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5377 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5378 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5379 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5380 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5381 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5382 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5383 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5384 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5385 (Mnemonic == "movs" && isThumb()))) {
5386 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5387 CarrySetting = true;
5390 // The "cps" instruction can have a interrupt mode operand which is glued into
5391 // the mnemonic. Check if this is the case, split it and parse the imod op
5392 if (Mnemonic.startswith("cps")) {
5393 // Split out any imod code.
5395 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5396 .Case("ie", ARM_PROC::IE)
5397 .Case("id", ARM_PROC::ID)
5400 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5401 ProcessorIMod = IMod;
5405 // The "it" instruction has the condition mask on the end of the mnemonic.
5406 if (Mnemonic.startswith("it")) {
5407 ITMask = Mnemonic.slice(2, Mnemonic.size());
5408 Mnemonic = Mnemonic.slice(0, 2);
5414 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5415 /// inclusion of carry set or predication code operands.
5417 // FIXME: It would be nice to autogen this.
5419 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5420 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5421 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5422 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5423 Mnemonic == "add" || Mnemonic == "adc" ||
5424 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5425 Mnemonic == "orr" || Mnemonic == "mvn" ||
5426 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5427 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5428 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5429 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5430 Mnemonic == "mla" || Mnemonic == "smlal" ||
5431 Mnemonic == "umlal" || Mnemonic == "umull"))) {
5432 CanAcceptCarrySet = true;
5434 CanAcceptCarrySet = false;
5436 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5437 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5438 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5439 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5440 Mnemonic.startswith("vsel") ||
5441 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5442 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5443 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5444 Mnemonic == "vrintm" || Mnemonic.startswith("aes") || Mnemonic == "hvc" ||
5445 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5446 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5447 // These mnemonics are never predicable
5448 CanAcceptPredicationCode = false;
5449 } else if (!isThumb()) {
5450 // Some instructions are only predicable in Thumb mode
5451 CanAcceptPredicationCode
5452 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5453 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5454 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5455 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5456 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5457 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5458 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5459 } else if (isThumbOne()) {
5461 CanAcceptPredicationCode = Mnemonic != "movs";
5463 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5465 CanAcceptPredicationCode = true;
5468 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5469 OperandVector &Operands) {
5470 // FIXME: This is all horribly hacky. We really need a better way to deal
5471 // with optional operands like this in the matcher table.
5473 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5474 // another does not. Specifically, the MOVW instruction does not. So we
5475 // special case it here and remove the defaulted (non-setting) cc_out
5476 // operand if that's the instruction we're trying to match.
5478 // We do this as post-processing of the explicit operands rather than just
5479 // conditionally adding the cc_out in the first place because we need
5480 // to check the type of the parsed immediate operand.
5481 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5482 !static_cast<ARMOperand &>(*Operands[4]).isARMSOImm() &&
5483 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5484 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5487 // Register-register 'add' for thumb does not have a cc_out operand
5488 // when there are only two register operands.
5489 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5490 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5491 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5492 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5494 // Register-register 'add' for thumb does not have a cc_out operand
5495 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5496 // have to check the immediate range here since Thumb2 has a variant
5497 // that can handle a different range and has a cc_out operand.
5498 if (((isThumb() && Mnemonic == "add") ||
5499 (isThumbTwo() && Mnemonic == "sub")) &&
5500 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5501 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5502 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5503 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5504 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5505 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5507 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5508 // imm0_4095 variant. That's the least-preferred variant when
5509 // selecting via the generic "add" mnemonic, so to know that we
5510 // should remove the cc_out operand, we have to explicitly check that
5511 // it's not one of the other variants. Ugh.
5512 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5513 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5514 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5515 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5516 // Nest conditions rather than one big 'if' statement for readability.
5518 // If both registers are low, we're in an IT block, and the immediate is
5519 // in range, we should use encoding T1 instead, which has a cc_out.
5521 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5522 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5523 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5525 // Check against T3. If the second register is the PC, this is an
5526 // alternate form of ADR, which uses encoding T4, so check for that too.
5527 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5528 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5531 // Otherwise, we use encoding T4, which does not have a cc_out
5536 // The thumb2 multiply instruction doesn't have a CCOut register, so
5537 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5538 // use the 16-bit encoding or not.
5539 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5540 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5541 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5542 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5543 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5544 // If the registers aren't low regs, the destination reg isn't the
5545 // same as one of the source regs, or the cc_out operand is zero
5546 // outside of an IT block, we have to use the 32-bit encoding, so
5547 // remove the cc_out operand.
5548 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5549 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5550 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5551 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5552 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5553 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5554 static_cast<ARMOperand &>(*Operands[4]).getReg())))
5557 // Also check the 'mul' syntax variant that doesn't specify an explicit
5558 // destination register.
5559 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5560 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5561 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5562 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5563 // If the registers aren't low regs or the cc_out operand is zero
5564 // outside of an IT block, we have to use the 32-bit encoding, so
5565 // remove the cc_out operand.
5566 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5567 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5573 // Register-register 'add/sub' for thumb does not have a cc_out operand
5574 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5575 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5576 // right, this will result in better diagnostics (which operand is off)
5578 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5579 (Operands.size() == 5 || Operands.size() == 6) &&
5580 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5581 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5582 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5583 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5584 (Operands.size() == 6 &&
5585 static_cast<ARMOperand &>(*Operands[5]).isImm())))
5591 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5592 OperandVector &Operands) {
5593 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5594 unsigned RegIdx = 3;
5595 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5596 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5597 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5598 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5601 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5602 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5603 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5604 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5605 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5611 static bool isDataTypeToken(StringRef Tok) {
5612 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5613 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5614 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5615 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5616 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5617 Tok == ".f" || Tok == ".d";
5620 // FIXME: This bit should probably be handled via an explicit match class
5621 // in the .td files that matches the suffix instead of having it be
5622 // a literal string token the way it is now.
5623 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5624 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5626 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5627 unsigned VariantID);
5629 static bool RequiresVFPRegListValidation(StringRef Inst,
5630 bool &AcceptSinglePrecisionOnly,
5631 bool &AcceptDoublePrecisionOnly) {
5632 if (Inst.size() < 7)
5635 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5636 StringRef AddressingMode = Inst.substr(4, 2);
5637 if (AddressingMode == "ia" || AddressingMode == "db" ||
5638 AddressingMode == "ea" || AddressingMode == "fd") {
5639 AcceptSinglePrecisionOnly = Inst[6] == 's';
5640 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5648 /// Parse an arm instruction mnemonic followed by its operands.
5649 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5650 SMLoc NameLoc, OperandVector &Operands) {
5651 MCAsmParser &Parser = getParser();
5652 // FIXME: Can this be done via tablegen in some fashion?
5653 bool RequireVFPRegisterListCheck;
5654 bool AcceptSinglePrecisionOnly;
5655 bool AcceptDoublePrecisionOnly;
5656 RequireVFPRegisterListCheck =
5657 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5658 AcceptDoublePrecisionOnly);
5660 // Apply mnemonic aliases before doing anything else, as the destination
5661 // mnemonic may include suffices and we want to handle them normally.
5662 // The generic tblgen'erated code does this later, at the start of
5663 // MatchInstructionImpl(), but that's too late for aliases that include
5664 // any sort of suffix.
5665 uint64_t AvailableFeatures = getAvailableFeatures();
5666 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5667 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5669 // First check for the ARM-specific .req directive.
5670 if (Parser.getTok().is(AsmToken::Identifier) &&
5671 Parser.getTok().getIdentifier() == ".req") {
5672 parseDirectiveReq(Name, NameLoc);
5673 // We always return 'error' for this, as we're done with this
5674 // statement and don't need to match the 'instruction."
5678 // Create the leading tokens for the mnemonic, split by '.' characters.
5679 size_t Start = 0, Next = Name.find('.');
5680 StringRef Mnemonic = Name.slice(Start, Next);
5682 // Split out the predication code and carry setting flag from the mnemonic.
5683 unsigned PredicationCode;
5684 unsigned ProcessorIMod;
5687 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5688 ProcessorIMod, ITMask);
5690 // In Thumb1, only the branch (B) instruction can be predicated.
5691 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5692 Parser.eatToEndOfStatement();
5693 return Error(NameLoc, "conditional execution not supported in Thumb1");
5696 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5698 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5699 // is the mask as it will be for the IT encoding if the conditional
5700 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5701 // where the conditional bit0 is zero, the instruction post-processing
5702 // will adjust the mask accordingly.
5703 if (Mnemonic == "it") {
5704 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5705 if (ITMask.size() > 3) {
5706 Parser.eatToEndOfStatement();
5707 return Error(Loc, "too many conditions on IT instruction");
5710 for (unsigned i = ITMask.size(); i != 0; --i) {
5711 char pos = ITMask[i - 1];
5712 if (pos != 't' && pos != 'e') {
5713 Parser.eatToEndOfStatement();
5714 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5717 if (ITMask[i - 1] == 't')
5720 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5723 // FIXME: This is all a pretty gross hack. We should automatically handle
5724 // optional operands like this via tblgen.
5726 // Next, add the CCOut and ConditionCode operands, if needed.
5728 // For mnemonics which can ever incorporate a carry setting bit or predication
5729 // code, our matching model involves us always generating CCOut and
5730 // ConditionCode operands to match the mnemonic "as written" and then we let
5731 // the matcher deal with finding the right instruction or generating an
5732 // appropriate error.
5733 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5734 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5736 // If we had a carry-set on an instruction that can't do that, issue an
5738 if (!CanAcceptCarrySet && CarrySetting) {
5739 Parser.eatToEndOfStatement();
5740 return Error(NameLoc, "instruction '" + Mnemonic +
5741 "' can not set flags, but 's' suffix specified");
5743 // If we had a predication code on an instruction that can't do that, issue an
5745 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5746 Parser.eatToEndOfStatement();
5747 return Error(NameLoc, "instruction '" + Mnemonic +
5748 "' is not predicable, but condition code specified");
5751 // Add the carry setting operand, if necessary.
5752 if (CanAcceptCarrySet) {
5753 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5754 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5758 // Add the predication code operand, if necessary.
5759 if (CanAcceptPredicationCode) {
5760 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5762 Operands.push_back(ARMOperand::CreateCondCode(
5763 ARMCC::CondCodes(PredicationCode), Loc));
5766 // Add the processor imod operand, if necessary.
5767 if (ProcessorIMod) {
5768 Operands.push_back(ARMOperand::CreateImm(
5769 MCConstantExpr::Create(ProcessorIMod, getContext()),
5771 } else if (Mnemonic == "cps" && isMClass()) {
5772 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
5775 // Add the remaining tokens in the mnemonic.
5776 while (Next != StringRef::npos) {
5778 Next = Name.find('.', Start + 1);
5779 StringRef ExtraToken = Name.slice(Start, Next);
5781 // Some NEON instructions have an optional datatype suffix that is
5782 // completely ignored. Check for that.
5783 if (isDataTypeToken(ExtraToken) &&
5784 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5787 // For for ARM mode generate an error if the .n qualifier is used.
5788 if (ExtraToken == ".n" && !isThumb()) {
5789 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5790 Parser.eatToEndOfStatement();
5791 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5795 // The .n qualifier is always discarded as that is what the tables
5796 // and matcher expect. In ARM mode the .w qualifier has no effect,
5797 // so discard it to avoid errors that can be caused by the matcher.
5798 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5799 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5800 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5804 // Read the remaining operands.
5805 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5806 // Read the first operand.
5807 if (parseOperand(Operands, Mnemonic)) {
5808 Parser.eatToEndOfStatement();
5812 while (getLexer().is(AsmToken::Comma)) {
5813 Parser.Lex(); // Eat the comma.
5815 // Parse and remember the operand.
5816 if (parseOperand(Operands, Mnemonic)) {
5817 Parser.eatToEndOfStatement();
5823 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5824 SMLoc Loc = getLexer().getLoc();
5825 Parser.eatToEndOfStatement();
5826 return Error(Loc, "unexpected token in argument list");
5829 Parser.Lex(); // Consume the EndOfStatement
5831 if (RequireVFPRegisterListCheck) {
5832 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5833 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5834 return Error(Op.getStartLoc(),
5835 "VFP/Neon single precision register expected");
5836 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5837 return Error(Op.getStartLoc(),
5838 "VFP/Neon double precision register expected");
5841 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5842 // do and don't have a cc_out optional-def operand. With some spot-checks
5843 // of the operand list, we can figure out which variant we're trying to
5844 // parse and adjust accordingly before actually matching. We shouldn't ever
5845 // try to remove a cc_out operand that was explicitly set on the the
5846 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5847 // table driven matcher doesn't fit well with the ARM instruction set.
5848 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5849 Operands.erase(Operands.begin() + 1);
5851 // Some instructions have the same mnemonic, but don't always
5852 // have a predicate. Distinguish them here and delete the
5853 // predicate if needed.
5854 if (shouldOmitPredicateOperand(Mnemonic, Operands))
5855 Operands.erase(Operands.begin() + 1);
5857 // ARM mode 'blx' need special handling, as the register operand version
5858 // is predicable, but the label operand version is not. So, we can't rely
5859 // on the Mnemonic based checking to correctly figure out when to put
5860 // a k_CondCode operand in the list. If we're trying to match the label
5861 // version, remove the k_CondCode operand here.
5862 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5863 static_cast<ARMOperand &>(*Operands[2]).isImm())
5864 Operands.erase(Operands.begin() + 1);
5866 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5867 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5868 // a single GPRPair reg operand is used in the .td file to replace the two
5869 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5870 // expressed as a GPRPair, so we have to manually merge them.
5871 // FIXME: We would really like to be able to tablegen'erate this.
5872 if (!isThumb() && Operands.size() > 4 &&
5873 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5874 Mnemonic == "stlexd")) {
5875 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5876 unsigned Idx = isLoad ? 2 : 3;
5877 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5878 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5880 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5881 // Adjust only if Op1 and Op2 are GPRs.
5882 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5883 MRC.contains(Op2.getReg())) {
5884 unsigned Reg1 = Op1.getReg();
5885 unsigned Reg2 = Op2.getReg();
5886 unsigned Rt = MRI->getEncodingValue(Reg1);
5887 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5889 // Rt2 must be Rt + 1 and Rt must be even.
5890 if (Rt + 1 != Rt2 || (Rt & 1)) {
5891 Error(Op2.getStartLoc(), isLoad
5892 ? "destination operands must be sequential"
5893 : "source operands must be sequential");
5896 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5897 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5899 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5900 Operands.erase(Operands.begin() + Idx + 1);
5904 // If first 2 operands of a 3 operand instruction are the same
5905 // then transform to 2 operand version of the same instruction
5906 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5907 // FIXME: We would really like to be able to tablegen'erate this.
5908 if (isThumbOne() && Operands.size() == 6 &&
5909 (Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5910 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5911 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5912 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) {
5913 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5914 ARMOperand &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5915 ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5917 // If both registers are the same then remove one of them from
5918 // the operand list.
5919 if (Op3.isReg() && Op4.isReg() && Op3.getReg() == Op4.getReg()) {
5920 // If 3rd operand (variable Op5) is a register and the instruction is adds/sub
5921 // then do not transform as the backend already handles this instruction
5923 if (!Op5.isReg() || !((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub")) {
5924 Operands.erase(Operands.begin() + 3);
5925 if (Mnemonic == "add" && !CarrySetting) {
5926 // Special case for 'add' (not 'adds') instruction must
5927 // remove the CCOut operand as well.
5928 Operands.erase(Operands.begin() + 1);
5934 // If instruction is 'add' and first two register operands
5935 // use SP register, then remove one of the SP registers from
5937 // FIXME: We would really like to be able to tablegen'erate this.
5938 if (isThumbOne() && Operands.size() == 5 && Mnemonic == "add" && !CarrySetting) {
5939 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5940 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5941 if (Op2.isReg() && Op3.isReg() && Op2.getReg() == ARM::SP && Op3.getReg() == ARM::SP) {
5942 Operands.erase(Operands.begin() + 2);
5946 // GNU Assembler extension (compatibility)
5947 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5948 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5949 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5951 assert(Op2.isReg() && "expected register argument");
5953 unsigned SuperReg = MRI->getMatchingSuperReg(
5954 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5956 assert(SuperReg && "expected register pair");
5958 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5961 Operands.begin() + 3,
5962 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5966 // FIXME: As said above, this is all a pretty gross hack. This instruction
5967 // does not fit with other "subs" and tblgen.
5968 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5969 // so the Mnemonic is the original name "subs" and delete the predicate
5970 // operand so it will match the table entry.
5971 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5972 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5973 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5974 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5975 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5976 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5977 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5978 Operands.erase(Operands.begin() + 1);
5983 // Validate context-sensitive operand constraints.
5985 // return 'true' if register list contains non-low GPR registers,
5986 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5987 // 'containsReg' to true.
5988 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5989 unsigned HiReg, bool &containsReg) {
5990 containsReg = false;
5991 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5992 unsigned OpReg = Inst.getOperand(i).getReg();
5995 // Anything other than a low register isn't legal here.
5996 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6002 // Check if the specified regisgter is in the register list of the inst,
6003 // starting at the indicated operand number.
6004 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
6005 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6006 unsigned OpReg = Inst.getOperand(i).getReg();
6013 // Return true if instruction has the interesting property of being
6014 // allowed in IT blocks, but not being predicable.
6015 static bool instIsBreakpoint(const MCInst &Inst) {
6016 return Inst.getOpcode() == ARM::tBKPT ||
6017 Inst.getOpcode() == ARM::BKPT ||
6018 Inst.getOpcode() == ARM::tHLT ||
6019 Inst.getOpcode() == ARM::HLT;
6023 // FIXME: We would really like to be able to tablegen'erate this.
6024 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6025 const OperandVector &Operands) {
6026 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6027 SMLoc Loc = Operands[0]->getStartLoc();
6029 // Check the IT block state first.
6030 // NOTE: BKPT and HLT instructions have the interesting property of being
6031 // allowed in IT blocks, but not being predicable. They just always execute.
6032 if (inITBlock() && !instIsBreakpoint(Inst)) {
6034 if (ITState.FirstCond)
6035 ITState.FirstCond = false;
6037 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
6038 // The instruction must be predicable.
6039 if (!MCID.isPredicable())
6040 return Error(Loc, "instructions in IT block must be predicable");
6041 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6042 unsigned ITCond = Bit ? ITState.Cond :
6043 ARMCC::getOppositeCondition(ITState.Cond);
6044 if (Cond != ITCond) {
6045 // Find the condition code Operand to get its SMLoc information.
6047 for (unsigned I = 1; I < Operands.size(); ++I)
6048 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6049 CondLoc = Operands[I]->getStartLoc();
6050 return Error(CondLoc, "incorrect condition in IT block; got '" +
6051 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
6052 "', but expected '" +
6053 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
6055 // Check for non-'al' condition codes outside of the IT block.
6056 } else if (isThumbTwo() && MCID.isPredicable() &&
6057 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6058 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6059 Inst.getOpcode() != ARM::t2Bcc)
6060 return Error(Loc, "predicated instructions must be in IT block");
6062 const unsigned Opcode = Inst.getOpcode();
6066 case ARM::LDRD_POST: {
6067 const unsigned RtReg = Inst.getOperand(0).getReg();
6070 if (RtReg == ARM::LR)
6071 return Error(Operands[3]->getStartLoc(),
6074 const unsigned Rt = MRI->getEncodingValue(RtReg);
6075 // Rt must be even-numbered.
6077 return Error(Operands[3]->getStartLoc(),
6078 "Rt must be even-numbered");
6080 // Rt2 must be Rt + 1.
6081 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6083 return Error(Operands[3]->getStartLoc(),
6084 "destination operands must be sequential");
6086 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
6087 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6088 // For addressing modes with writeback, the base register needs to be
6089 // different from the destination registers.
6090 if (Rn == Rt || Rn == Rt2)
6091 return Error(Operands[3]->getStartLoc(),
6092 "base register needs to be different from destination "
6099 case ARM::t2LDRD_PRE:
6100 case ARM::t2LDRD_POST: {
6101 // Rt2 must be different from Rt.
6102 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6103 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6105 return Error(Operands[3]->getStartLoc(),
6106 "destination operands can't be identical");
6110 // Rt2 must be Rt + 1.
6111 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6112 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6114 return Error(Operands[3]->getStartLoc(),
6115 "source operands must be sequential");
6119 case ARM::STRD_POST: {
6120 // Rt2 must be Rt + 1.
6121 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6122 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6124 return Error(Operands[3]->getStartLoc(),
6125 "source operands must be sequential");
6128 case ARM::STR_PRE_IMM:
6129 case ARM::STR_PRE_REG:
6130 case ARM::STR_POST_IMM:
6131 case ARM::STR_POST_REG:
6133 case ARM::STRH_POST:
6134 case ARM::STRB_PRE_IMM:
6135 case ARM::STRB_PRE_REG:
6136 case ARM::STRB_POST_IMM:
6137 case ARM::STRB_POST_REG: {
6138 // Rt must be different from Rn.
6139 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6140 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6143 return Error(Operands[3]->getStartLoc(),
6144 "source register and base register can't be identical");
6147 case ARM::LDR_PRE_IMM:
6148 case ARM::LDR_PRE_REG:
6149 case ARM::LDR_POST_IMM:
6150 case ARM::LDR_POST_REG:
6152 case ARM::LDRH_POST:
6153 case ARM::LDRSH_PRE:
6154 case ARM::LDRSH_POST:
6155 case ARM::LDRB_PRE_IMM:
6156 case ARM::LDRB_PRE_REG:
6157 case ARM::LDRB_POST_IMM:
6158 case ARM::LDRB_POST_REG:
6159 case ARM::LDRSB_PRE:
6160 case ARM::LDRSB_POST: {
6161 // Rt must be different from Rn.
6162 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6163 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6166 return Error(Operands[3]->getStartLoc(),
6167 "destination register and base register can't be identical");
6172 // Width must be in range [1, 32-lsb].
6173 unsigned LSB = Inst.getOperand(2).getImm();
6174 unsigned Widthm1 = Inst.getOperand(3).getImm();
6175 if (Widthm1 >= 32 - LSB)
6176 return Error(Operands[5]->getStartLoc(),
6177 "bitfield width must be in range [1,32-lsb]");
6180 // Notionally handles ARM::tLDMIA_UPD too.
6182 // If we're parsing Thumb2, the .w variant is available and handles
6183 // most cases that are normally illegal for a Thumb1 LDM instruction.
6184 // We'll make the transformation in processInstruction() if necessary.
6186 // Thumb LDM instructions are writeback iff the base register is not
6187 // in the register list.
6188 unsigned Rn = Inst.getOperand(0).getReg();
6189 bool HasWritebackToken =
6190 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6191 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6192 bool ListContainsBase;
6193 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6194 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6195 "registers must be in range r0-r7");
6196 // If we should have writeback, then there should be a '!' token.
6197 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6198 return Error(Operands[2]->getStartLoc(),
6199 "writeback operator '!' expected");
6200 // If we should not have writeback, there must not be a '!'. This is
6201 // true even for the 32-bit wide encodings.
6202 if (ListContainsBase && HasWritebackToken)
6203 return Error(Operands[3]->getStartLoc(),
6204 "writeback operator '!' not allowed when base register "
6205 "in register list");
6206 if (listContainsReg(Inst, 3 + HasWritebackToken, ARM::SP))
6207 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6208 "SP not allowed in register list");
6211 case ARM::LDMIA_UPD:
6212 case ARM::LDMDB_UPD:
6213 case ARM::LDMIB_UPD:
6214 case ARM::LDMDA_UPD:
6215 // ARM variants loading and updating the same register are only officially
6216 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6219 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6220 return Error(Operands.back()->getStartLoc(),
6221 "writeback register not allowed in register list");
6226 case ARM::t2STMDB: {
6227 if (listContainsReg(Inst, 3, ARM::SP))
6228 return Error(Operands.back()->getStartLoc(),
6229 "SP not allowed in register list");
6232 case ARM::t2LDMIA_UPD:
6233 case ARM::t2LDMDB_UPD:
6234 case ARM::t2STMIA_UPD:
6235 case ARM::t2STMDB_UPD: {
6236 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6237 return Error(Operands.back()->getStartLoc(),
6238 "writeback register not allowed in register list");
6240 if (listContainsReg(Inst, 4, ARM::SP))
6241 return Error(Operands.back()->getStartLoc(),
6242 "SP not allowed in register list");
6245 case ARM::sysLDMIA_UPD:
6246 case ARM::sysLDMDA_UPD:
6247 case ARM::sysLDMDB_UPD:
6248 case ARM::sysLDMIB_UPD:
6249 if (!listContainsReg(Inst, 3, ARM::PC))
6250 return Error(Operands[4]->getStartLoc(),
6251 "writeback register only allowed on system LDM "
6252 "if PC in register-list");
6254 case ARM::sysSTMIA_UPD:
6255 case ARM::sysSTMDA_UPD:
6256 case ARM::sysSTMDB_UPD:
6257 case ARM::sysSTMIB_UPD:
6258 return Error(Operands[2]->getStartLoc(),
6259 "system STM cannot have writeback register");
6261 // The second source operand must be the same register as the destination
6264 // In this case, we must directly check the parsed operands because the
6265 // cvtThumbMultiply() function is written in such a way that it guarantees
6266 // this first statement is always true for the new Inst. Essentially, the
6267 // destination is unconditionally copied into the second source operand
6268 // without checking to see if it matches what we actually parsed.
6269 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6270 ((ARMOperand &)*Operands[5]).getReg()) &&
6271 (((ARMOperand &)*Operands[3]).getReg() !=
6272 ((ARMOperand &)*Operands[4]).getReg())) {
6273 return Error(Operands[3]->getStartLoc(),
6274 "destination register must match source register");
6278 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6279 // so only issue a diagnostic for thumb1. The instructions will be
6280 // switched to the t2 encodings in processInstruction() if necessary.
6282 bool ListContainsBase;
6283 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6285 return Error(Operands[2]->getStartLoc(),
6286 "registers must be in range r0-r7 or pc");
6290 bool ListContainsBase;
6291 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6293 return Error(Operands[2]->getStartLoc(),
6294 "registers must be in range r0-r7 or lr");
6297 case ARM::tSTMIA_UPD: {
6298 bool ListContainsBase, InvalidLowList;
6299 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6300 0, ListContainsBase);
6301 if (InvalidLowList && !isThumbTwo())
6302 return Error(Operands[4]->getStartLoc(),
6303 "registers must be in range r0-r7");
6305 // This would be converted to a 32-bit stm, but that's not valid if the
6306 // writeback register is in the list.
6307 if (InvalidLowList && ListContainsBase)
6308 return Error(Operands[4]->getStartLoc(),
6309 "writeback operator '!' not allowed when base register "
6310 "in register list");
6311 if (listContainsReg(Inst, 4, ARM::SP) && !inITBlock())
6312 return Error(Operands.back()->getStartLoc(),
6313 "SP not allowed in register list");
6316 case ARM::tADDrSP: {
6317 // If the non-SP source operand and the destination operand are not the
6318 // same, we need thumb2 (for the wide encoding), or we have an error.
6319 if (!isThumbTwo() &&
6320 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6321 return Error(Operands[4]->getStartLoc(),
6322 "source register must be the same as destination");
6326 // Final range checking for Thumb unconditional branch instructions.
6328 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6329 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6332 int op = (Operands[2]->isImm()) ? 2 : 3;
6333 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6334 return Error(Operands[op]->getStartLoc(), "branch target out of range");
6337 // Final range checking for Thumb conditional branch instructions.
6339 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6340 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6343 int Op = (Operands[2]->isImm()) ? 2 : 3;
6344 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6345 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6350 case ARM::t2MOVTi16:
6352 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6353 // especially when we turn it into a movw and the expression <symbol> does
6354 // not have a :lower16: or :upper16 as part of the expression. We don't
6355 // want the behavior of silently truncating, which can be unexpected and
6356 // lead to bugs that are difficult to find since this is an easy mistake
6358 int i = (Operands[3]->isImm()) ? 3 : 4;
6359 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6360 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6362 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6364 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6365 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6366 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6369 "immediate expression for mov requires :lower16: or :upper16");
6377 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6379 default: llvm_unreachable("unexpected opcode!");
6381 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6382 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6383 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6384 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6385 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6386 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6387 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
6388 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6389 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6392 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6393 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6394 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6395 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6396 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6398 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6399 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6400 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6401 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6402 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6404 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
6405 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6406 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6407 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6408 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6411 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6412 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6413 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6414 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6415 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6416 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6417 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6418 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6419 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6420 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6421 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
6422 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6423 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6424 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6425 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6428 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6429 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6430 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6431 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6432 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6433 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6434 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6435 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6436 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6437 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6438 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6439 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6440 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6441 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6442 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6443 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6444 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6445 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6448 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6449 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6450 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6451 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6452 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6453 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6454 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6455 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6456 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6457 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6458 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6459 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6460 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6461 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6462 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6465 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6466 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6467 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6468 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6469 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6470 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6471 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6472 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6473 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6474 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6475 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6476 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6477 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6478 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6479 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6480 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6481 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6482 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6486 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6488 default: llvm_unreachable("unexpected opcode!");
6490 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6491 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6492 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6493 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6494 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6495 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6496 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6497 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6498 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6501 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6502 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6503 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6504 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6505 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6506 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6507 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6508 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6509 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6510 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6511 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6512 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6513 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6514 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6515 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6518 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6519 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6520 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6521 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6522 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6523 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6524 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6525 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6526 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6527 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6528 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6529 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6530 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6531 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6532 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6533 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6534 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6535 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6538 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6539 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6540 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6541 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6542 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6543 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6544 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6545 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6546 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6547 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6548 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6549 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6550 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6551 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6552 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6555 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6556 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6557 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6558 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6559 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6560 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6561 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6562 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6563 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6564 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6565 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6566 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6567 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6568 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6569 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6570 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6571 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6572 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6575 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6576 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6577 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6578 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6579 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6580 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6581 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6582 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6583 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6584 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6585 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6586 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6587 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6588 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6589 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6592 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6593 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6594 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6595 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6596 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6597 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6598 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6599 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6600 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6601 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6602 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6603 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6604 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6605 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6606 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6607 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6608 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6609 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6612 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6613 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6614 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6615 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6616 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6617 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6618 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6619 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6620 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6621 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6622 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6623 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6624 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6625 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6626 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6627 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6628 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6629 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6633 bool ARMAsmParser::processInstruction(MCInst &Inst,
6634 const OperandVector &Operands,
6636 switch (Inst.getOpcode()) {
6637 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6638 case ARM::LDRT_POST:
6639 case ARM::LDRBT_POST: {
6640 const unsigned Opcode =
6641 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6642 : ARM::LDRBT_POST_IMM;
6644 TmpInst.setOpcode(Opcode);
6645 TmpInst.addOperand(Inst.getOperand(0));
6646 TmpInst.addOperand(Inst.getOperand(1));
6647 TmpInst.addOperand(Inst.getOperand(1));
6648 TmpInst.addOperand(MCOperand::CreateReg(0));
6649 TmpInst.addOperand(MCOperand::CreateImm(0));
6650 TmpInst.addOperand(Inst.getOperand(2));
6651 TmpInst.addOperand(Inst.getOperand(3));
6655 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6656 case ARM::STRT_POST:
6657 case ARM::STRBT_POST: {
6658 const unsigned Opcode =
6659 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6660 : ARM::STRBT_POST_IMM;
6662 TmpInst.setOpcode(Opcode);
6663 TmpInst.addOperand(Inst.getOperand(1));
6664 TmpInst.addOperand(Inst.getOperand(0));
6665 TmpInst.addOperand(Inst.getOperand(1));
6666 TmpInst.addOperand(MCOperand::CreateReg(0));
6667 TmpInst.addOperand(MCOperand::CreateImm(0));
6668 TmpInst.addOperand(Inst.getOperand(2));
6669 TmpInst.addOperand(Inst.getOperand(3));
6673 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6675 if (Inst.getOperand(1).getReg() != ARM::PC ||
6676 Inst.getOperand(5).getReg() != 0 ||
6677 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
6680 TmpInst.setOpcode(ARM::ADR);
6681 TmpInst.addOperand(Inst.getOperand(0));
6682 if (Inst.getOperand(2).isImm()) {
6683 TmpInst.addOperand(Inst.getOperand(2));
6685 // Turn PC-relative expression into absolute expression.
6686 // Reading PC provides the start of the current instruction + 8 and
6687 // the transform to adr is biased by that.
6688 MCSymbol *Dot = getContext().CreateTempSymbol();
6690 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
6691 const MCExpr *InstPC = MCSymbolRefExpr::Create(Dot,
6692 MCSymbolRefExpr::VK_None,
6694 const MCExpr *Const8 = MCConstantExpr::Create(8, getContext());
6695 const MCExpr *ReadPC = MCBinaryExpr::CreateAdd(InstPC, Const8,
6697 const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr,
6699 TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));
6701 TmpInst.addOperand(Inst.getOperand(3));
6702 TmpInst.addOperand(Inst.getOperand(4));
6706 // Aliases for alternate PC+imm syntax of LDR instructions.
6707 case ARM::t2LDRpcrel:
6708 // Select the narrow version if the immediate will fit.
6709 if (Inst.getOperand(1).getImm() > 0 &&
6710 Inst.getOperand(1).getImm() <= 0xff &&
6711 !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6712 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6713 Inst.setOpcode(ARM::tLDRpci);
6715 Inst.setOpcode(ARM::t2LDRpci);
6717 case ARM::t2LDRBpcrel:
6718 Inst.setOpcode(ARM::t2LDRBpci);
6720 case ARM::t2LDRHpcrel:
6721 Inst.setOpcode(ARM::t2LDRHpci);
6723 case ARM::t2LDRSBpcrel:
6724 Inst.setOpcode(ARM::t2LDRSBpci);
6726 case ARM::t2LDRSHpcrel:
6727 Inst.setOpcode(ARM::t2LDRSHpci);
6729 // Handle NEON VST complex aliases.
6730 case ARM::VST1LNdWB_register_Asm_8:
6731 case ARM::VST1LNdWB_register_Asm_16:
6732 case ARM::VST1LNdWB_register_Asm_32: {
6734 // Shuffle the operands around so the lane index operand is in the
6737 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6738 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6739 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6740 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6741 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6742 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6743 TmpInst.addOperand(Inst.getOperand(1)); // lane
6744 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6745 TmpInst.addOperand(Inst.getOperand(6));
6750 case ARM::VST2LNdWB_register_Asm_8:
6751 case ARM::VST2LNdWB_register_Asm_16:
6752 case ARM::VST2LNdWB_register_Asm_32:
6753 case ARM::VST2LNqWB_register_Asm_16:
6754 case ARM::VST2LNqWB_register_Asm_32: {
6756 // Shuffle the operands around so the lane index operand is in the
6759 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6760 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6761 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6762 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6763 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6764 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6765 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6767 TmpInst.addOperand(Inst.getOperand(1)); // lane
6768 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6769 TmpInst.addOperand(Inst.getOperand(6));
6774 case ARM::VST3LNdWB_register_Asm_8:
6775 case ARM::VST3LNdWB_register_Asm_16:
6776 case ARM::VST3LNdWB_register_Asm_32:
6777 case ARM::VST3LNqWB_register_Asm_16:
6778 case ARM::VST3LNqWB_register_Asm_32: {
6780 // Shuffle the operands around so the lane index operand is in the
6783 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6784 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6785 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6786 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6787 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6788 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6789 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6791 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6793 TmpInst.addOperand(Inst.getOperand(1)); // lane
6794 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6795 TmpInst.addOperand(Inst.getOperand(6));
6800 case ARM::VST4LNdWB_register_Asm_8:
6801 case ARM::VST4LNdWB_register_Asm_16:
6802 case ARM::VST4LNdWB_register_Asm_32:
6803 case ARM::VST4LNqWB_register_Asm_16:
6804 case ARM::VST4LNqWB_register_Asm_32: {
6806 // Shuffle the operands around so the lane index operand is in the
6809 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6810 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6811 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6812 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6813 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6814 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6815 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6817 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6819 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6821 TmpInst.addOperand(Inst.getOperand(1)); // lane
6822 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6823 TmpInst.addOperand(Inst.getOperand(6));
6828 case ARM::VST1LNdWB_fixed_Asm_8:
6829 case ARM::VST1LNdWB_fixed_Asm_16:
6830 case ARM::VST1LNdWB_fixed_Asm_32: {
6832 // Shuffle the operands around so the lane index operand is in the
6835 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6836 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6837 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6838 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6839 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6840 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6841 TmpInst.addOperand(Inst.getOperand(1)); // lane
6842 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6843 TmpInst.addOperand(Inst.getOperand(5));
6848 case ARM::VST2LNdWB_fixed_Asm_8:
6849 case ARM::VST2LNdWB_fixed_Asm_16:
6850 case ARM::VST2LNdWB_fixed_Asm_32:
6851 case ARM::VST2LNqWB_fixed_Asm_16:
6852 case ARM::VST2LNqWB_fixed_Asm_32: {
6854 // Shuffle the operands around so the lane index operand is in the
6857 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6858 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6859 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6860 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6861 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6862 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6863 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6865 TmpInst.addOperand(Inst.getOperand(1)); // lane
6866 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6867 TmpInst.addOperand(Inst.getOperand(5));
6872 case ARM::VST3LNdWB_fixed_Asm_8:
6873 case ARM::VST3LNdWB_fixed_Asm_16:
6874 case ARM::VST3LNdWB_fixed_Asm_32:
6875 case ARM::VST3LNqWB_fixed_Asm_16:
6876 case ARM::VST3LNqWB_fixed_Asm_32: {
6878 // Shuffle the operands around so the lane index operand is in the
6881 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6882 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6883 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6884 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6885 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6886 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6887 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6889 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6891 TmpInst.addOperand(Inst.getOperand(1)); // lane
6892 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6893 TmpInst.addOperand(Inst.getOperand(5));
6898 case ARM::VST4LNdWB_fixed_Asm_8:
6899 case ARM::VST4LNdWB_fixed_Asm_16:
6900 case ARM::VST4LNdWB_fixed_Asm_32:
6901 case ARM::VST4LNqWB_fixed_Asm_16:
6902 case ARM::VST4LNqWB_fixed_Asm_32: {
6904 // Shuffle the operands around so the lane index operand is in the
6907 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6908 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6909 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6910 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6911 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6912 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6913 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6915 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6917 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6919 TmpInst.addOperand(Inst.getOperand(1)); // lane
6920 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6921 TmpInst.addOperand(Inst.getOperand(5));
6926 case ARM::VST1LNdAsm_8:
6927 case ARM::VST1LNdAsm_16:
6928 case ARM::VST1LNdAsm_32: {
6930 // Shuffle the operands around so the lane index operand is in the
6933 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6934 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6935 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6936 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6937 TmpInst.addOperand(Inst.getOperand(1)); // lane
6938 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6939 TmpInst.addOperand(Inst.getOperand(5));
6944 case ARM::VST2LNdAsm_8:
6945 case ARM::VST2LNdAsm_16:
6946 case ARM::VST2LNdAsm_32:
6947 case ARM::VST2LNqAsm_16:
6948 case ARM::VST2LNqAsm_32: {
6950 // Shuffle the operands around so the lane index operand is in the
6953 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6954 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6955 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6956 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6957 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6959 TmpInst.addOperand(Inst.getOperand(1)); // lane
6960 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6961 TmpInst.addOperand(Inst.getOperand(5));
6966 case ARM::VST3LNdAsm_8:
6967 case ARM::VST3LNdAsm_16:
6968 case ARM::VST3LNdAsm_32:
6969 case ARM::VST3LNqAsm_16:
6970 case ARM::VST3LNqAsm_32: {
6972 // Shuffle the operands around so the lane index operand is in the
6975 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6976 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6977 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6978 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6979 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6981 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6983 TmpInst.addOperand(Inst.getOperand(1)); // lane
6984 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6985 TmpInst.addOperand(Inst.getOperand(5));
6990 case ARM::VST4LNdAsm_8:
6991 case ARM::VST4LNdAsm_16:
6992 case ARM::VST4LNdAsm_32:
6993 case ARM::VST4LNqAsm_16:
6994 case ARM::VST4LNqAsm_32: {
6996 // Shuffle the operands around so the lane index operand is in the
6999 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7000 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7001 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7002 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7003 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7005 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7007 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7009 TmpInst.addOperand(Inst.getOperand(1)); // lane
7010 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7011 TmpInst.addOperand(Inst.getOperand(5));
7016 // Handle NEON VLD complex aliases.
7017 case ARM::VLD1LNdWB_register_Asm_8:
7018 case ARM::VLD1LNdWB_register_Asm_16:
7019 case ARM::VLD1LNdWB_register_Asm_32: {
7021 // Shuffle the operands around so the lane index operand is in the
7024 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7025 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7026 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7027 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7028 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7029 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7030 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7031 TmpInst.addOperand(Inst.getOperand(1)); // lane
7032 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7033 TmpInst.addOperand(Inst.getOperand(6));
7038 case ARM::VLD2LNdWB_register_Asm_8:
7039 case ARM::VLD2LNdWB_register_Asm_16:
7040 case ARM::VLD2LNdWB_register_Asm_32:
7041 case ARM::VLD2LNqWB_register_Asm_16:
7042 case ARM::VLD2LNqWB_register_Asm_32: {
7044 // Shuffle the operands around so the lane index operand is in the
7047 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7048 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7049 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7051 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7052 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7053 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7054 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7055 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7056 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7058 TmpInst.addOperand(Inst.getOperand(1)); // lane
7059 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7060 TmpInst.addOperand(Inst.getOperand(6));
7065 case ARM::VLD3LNdWB_register_Asm_8:
7066 case ARM::VLD3LNdWB_register_Asm_16:
7067 case ARM::VLD3LNdWB_register_Asm_32:
7068 case ARM::VLD3LNqWB_register_Asm_16:
7069 case ARM::VLD3LNqWB_register_Asm_32: {
7071 // Shuffle the operands around so the lane index operand is in the
7074 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7075 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7076 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7078 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7080 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7081 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7082 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7083 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7084 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7085 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7087 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7089 TmpInst.addOperand(Inst.getOperand(1)); // lane
7090 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7091 TmpInst.addOperand(Inst.getOperand(6));
7096 case ARM::VLD4LNdWB_register_Asm_8:
7097 case ARM::VLD4LNdWB_register_Asm_16:
7098 case ARM::VLD4LNdWB_register_Asm_32:
7099 case ARM::VLD4LNqWB_register_Asm_16:
7100 case ARM::VLD4LNqWB_register_Asm_32: {
7102 // Shuffle the operands around so the lane index operand is in the
7105 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7106 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7107 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7109 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7111 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7113 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7114 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7115 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7116 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7117 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7118 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7120 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7122 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7124 TmpInst.addOperand(Inst.getOperand(1)); // lane
7125 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7126 TmpInst.addOperand(Inst.getOperand(6));
7131 case ARM::VLD1LNdWB_fixed_Asm_8:
7132 case ARM::VLD1LNdWB_fixed_Asm_16:
7133 case ARM::VLD1LNdWB_fixed_Asm_32: {
7135 // Shuffle the operands around so the lane index operand is in the
7138 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7139 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7140 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7141 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7142 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7143 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7144 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7145 TmpInst.addOperand(Inst.getOperand(1)); // lane
7146 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7147 TmpInst.addOperand(Inst.getOperand(5));
7152 case ARM::VLD2LNdWB_fixed_Asm_8:
7153 case ARM::VLD2LNdWB_fixed_Asm_16:
7154 case ARM::VLD2LNdWB_fixed_Asm_32:
7155 case ARM::VLD2LNqWB_fixed_Asm_16:
7156 case ARM::VLD2LNqWB_fixed_Asm_32: {
7158 // Shuffle the operands around so the lane index operand is in the
7161 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7162 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7163 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7165 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7166 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7167 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7168 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7169 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7170 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7172 TmpInst.addOperand(Inst.getOperand(1)); // lane
7173 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7174 TmpInst.addOperand(Inst.getOperand(5));
7179 case ARM::VLD3LNdWB_fixed_Asm_8:
7180 case ARM::VLD3LNdWB_fixed_Asm_16:
7181 case ARM::VLD3LNdWB_fixed_Asm_32:
7182 case ARM::VLD3LNqWB_fixed_Asm_16:
7183 case ARM::VLD3LNqWB_fixed_Asm_32: {
7185 // Shuffle the operands around so the lane index operand is in the
7188 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7189 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7190 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7192 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7194 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7195 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7196 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7197 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7198 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7199 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7201 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7203 TmpInst.addOperand(Inst.getOperand(1)); // lane
7204 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7205 TmpInst.addOperand(Inst.getOperand(5));
7210 case ARM::VLD4LNdWB_fixed_Asm_8:
7211 case ARM::VLD4LNdWB_fixed_Asm_16:
7212 case ARM::VLD4LNdWB_fixed_Asm_32:
7213 case ARM::VLD4LNqWB_fixed_Asm_16:
7214 case ARM::VLD4LNqWB_fixed_Asm_32: {
7216 // Shuffle the operands around so the lane index operand is in the
7219 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7220 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7221 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7223 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7225 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7227 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7228 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7229 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7230 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7231 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7232 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7234 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7236 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7238 TmpInst.addOperand(Inst.getOperand(1)); // lane
7239 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7240 TmpInst.addOperand(Inst.getOperand(5));
7245 case ARM::VLD1LNdAsm_8:
7246 case ARM::VLD1LNdAsm_16:
7247 case ARM::VLD1LNdAsm_32: {
7249 // Shuffle the operands around so the lane index operand is in the
7252 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7253 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7254 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7255 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7256 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7257 TmpInst.addOperand(Inst.getOperand(1)); // lane
7258 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7259 TmpInst.addOperand(Inst.getOperand(5));
7264 case ARM::VLD2LNdAsm_8:
7265 case ARM::VLD2LNdAsm_16:
7266 case ARM::VLD2LNdAsm_32:
7267 case ARM::VLD2LNqAsm_16:
7268 case ARM::VLD2LNqAsm_32: {
7270 // Shuffle the operands around so the lane index operand is in the
7273 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7274 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7275 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7277 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7278 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7279 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7280 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7282 TmpInst.addOperand(Inst.getOperand(1)); // lane
7283 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7284 TmpInst.addOperand(Inst.getOperand(5));
7289 case ARM::VLD3LNdAsm_8:
7290 case ARM::VLD3LNdAsm_16:
7291 case ARM::VLD3LNdAsm_32:
7292 case ARM::VLD3LNqAsm_16:
7293 case ARM::VLD3LNqAsm_32: {
7295 // Shuffle the operands around so the lane index operand is in the
7298 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7299 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7300 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7302 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7304 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7305 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7306 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7307 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7309 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7311 TmpInst.addOperand(Inst.getOperand(1)); // lane
7312 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7313 TmpInst.addOperand(Inst.getOperand(5));
7318 case ARM::VLD4LNdAsm_8:
7319 case ARM::VLD4LNdAsm_16:
7320 case ARM::VLD4LNdAsm_32:
7321 case ARM::VLD4LNqAsm_16:
7322 case ARM::VLD4LNqAsm_32: {
7324 // Shuffle the operands around so the lane index operand is in the
7327 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7328 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7329 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7331 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7333 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7335 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7336 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7337 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7338 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7340 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7342 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7344 TmpInst.addOperand(Inst.getOperand(1)); // lane
7345 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7346 TmpInst.addOperand(Inst.getOperand(5));
7351 // VLD3DUP single 3-element structure to all lanes instructions.
7352 case ARM::VLD3DUPdAsm_8:
7353 case ARM::VLD3DUPdAsm_16:
7354 case ARM::VLD3DUPdAsm_32:
7355 case ARM::VLD3DUPqAsm_8:
7356 case ARM::VLD3DUPqAsm_16:
7357 case ARM::VLD3DUPqAsm_32: {
7360 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7361 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7362 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7364 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7366 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7367 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7368 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7369 TmpInst.addOperand(Inst.getOperand(4));
7374 case ARM::VLD3DUPdWB_fixed_Asm_8:
7375 case ARM::VLD3DUPdWB_fixed_Asm_16:
7376 case ARM::VLD3DUPdWB_fixed_Asm_32:
7377 case ARM::VLD3DUPqWB_fixed_Asm_8:
7378 case ARM::VLD3DUPqWB_fixed_Asm_16:
7379 case ARM::VLD3DUPqWB_fixed_Asm_32: {
7382 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7383 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7384 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7386 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7388 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7389 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7390 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7391 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7392 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7393 TmpInst.addOperand(Inst.getOperand(4));
7398 case ARM::VLD3DUPdWB_register_Asm_8:
7399 case ARM::VLD3DUPdWB_register_Asm_16:
7400 case ARM::VLD3DUPdWB_register_Asm_32:
7401 case ARM::VLD3DUPqWB_register_Asm_8:
7402 case ARM::VLD3DUPqWB_register_Asm_16:
7403 case ARM::VLD3DUPqWB_register_Asm_32: {
7406 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7407 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7408 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7410 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7412 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7413 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7414 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7415 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7416 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7417 TmpInst.addOperand(Inst.getOperand(5));
7422 // VLD3 multiple 3-element structure instructions.
7423 case ARM::VLD3dAsm_8:
7424 case ARM::VLD3dAsm_16:
7425 case ARM::VLD3dAsm_32:
7426 case ARM::VLD3qAsm_8:
7427 case ARM::VLD3qAsm_16:
7428 case ARM::VLD3qAsm_32: {
7431 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7432 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7433 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7435 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7437 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7438 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7439 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7440 TmpInst.addOperand(Inst.getOperand(4));
7445 case ARM::VLD3dWB_fixed_Asm_8:
7446 case ARM::VLD3dWB_fixed_Asm_16:
7447 case ARM::VLD3dWB_fixed_Asm_32:
7448 case ARM::VLD3qWB_fixed_Asm_8:
7449 case ARM::VLD3qWB_fixed_Asm_16:
7450 case ARM::VLD3qWB_fixed_Asm_32: {
7453 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7454 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7455 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7457 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7459 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7460 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7461 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7462 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7463 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7464 TmpInst.addOperand(Inst.getOperand(4));
7469 case ARM::VLD3dWB_register_Asm_8:
7470 case ARM::VLD3dWB_register_Asm_16:
7471 case ARM::VLD3dWB_register_Asm_32:
7472 case ARM::VLD3qWB_register_Asm_8:
7473 case ARM::VLD3qWB_register_Asm_16:
7474 case ARM::VLD3qWB_register_Asm_32: {
7477 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7478 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7479 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7481 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7483 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7484 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7485 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7486 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7487 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7488 TmpInst.addOperand(Inst.getOperand(5));
7493 // VLD4DUP single 3-element structure to all lanes instructions.
7494 case ARM::VLD4DUPdAsm_8:
7495 case ARM::VLD4DUPdAsm_16:
7496 case ARM::VLD4DUPdAsm_32:
7497 case ARM::VLD4DUPqAsm_8:
7498 case ARM::VLD4DUPqAsm_16:
7499 case ARM::VLD4DUPqAsm_32: {
7502 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7503 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7504 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7506 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7508 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7510 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7511 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7512 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7513 TmpInst.addOperand(Inst.getOperand(4));
7518 case ARM::VLD4DUPdWB_fixed_Asm_8:
7519 case ARM::VLD4DUPdWB_fixed_Asm_16:
7520 case ARM::VLD4DUPdWB_fixed_Asm_32:
7521 case ARM::VLD4DUPqWB_fixed_Asm_8:
7522 case ARM::VLD4DUPqWB_fixed_Asm_16:
7523 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7526 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7527 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7528 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7530 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7532 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7534 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7535 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7536 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7537 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7538 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7539 TmpInst.addOperand(Inst.getOperand(4));
7544 case ARM::VLD4DUPdWB_register_Asm_8:
7545 case ARM::VLD4DUPdWB_register_Asm_16:
7546 case ARM::VLD4DUPdWB_register_Asm_32:
7547 case ARM::VLD4DUPqWB_register_Asm_8:
7548 case ARM::VLD4DUPqWB_register_Asm_16:
7549 case ARM::VLD4DUPqWB_register_Asm_32: {
7552 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7553 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7554 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7556 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7558 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7560 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7561 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7562 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7563 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7564 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7565 TmpInst.addOperand(Inst.getOperand(5));
7570 // VLD4 multiple 4-element structure instructions.
7571 case ARM::VLD4dAsm_8:
7572 case ARM::VLD4dAsm_16:
7573 case ARM::VLD4dAsm_32:
7574 case ARM::VLD4qAsm_8:
7575 case ARM::VLD4qAsm_16:
7576 case ARM::VLD4qAsm_32: {
7579 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7580 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7581 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7583 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7585 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7587 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7588 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7589 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7590 TmpInst.addOperand(Inst.getOperand(4));
7595 case ARM::VLD4dWB_fixed_Asm_8:
7596 case ARM::VLD4dWB_fixed_Asm_16:
7597 case ARM::VLD4dWB_fixed_Asm_32:
7598 case ARM::VLD4qWB_fixed_Asm_8:
7599 case ARM::VLD4qWB_fixed_Asm_16:
7600 case ARM::VLD4qWB_fixed_Asm_32: {
7603 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7604 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7605 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7607 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7609 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7611 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7612 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7613 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7614 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7615 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7616 TmpInst.addOperand(Inst.getOperand(4));
7621 case ARM::VLD4dWB_register_Asm_8:
7622 case ARM::VLD4dWB_register_Asm_16:
7623 case ARM::VLD4dWB_register_Asm_32:
7624 case ARM::VLD4qWB_register_Asm_8:
7625 case ARM::VLD4qWB_register_Asm_16:
7626 case ARM::VLD4qWB_register_Asm_32: {
7629 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7630 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7631 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7633 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7635 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7637 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7638 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7639 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7640 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7641 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7642 TmpInst.addOperand(Inst.getOperand(5));
7647 // VST3 multiple 3-element structure instructions.
7648 case ARM::VST3dAsm_8:
7649 case ARM::VST3dAsm_16:
7650 case ARM::VST3dAsm_32:
7651 case ARM::VST3qAsm_8:
7652 case ARM::VST3qAsm_16:
7653 case ARM::VST3qAsm_32: {
7656 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7657 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7658 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7659 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7660 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7662 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7664 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7665 TmpInst.addOperand(Inst.getOperand(4));
7670 case ARM::VST3dWB_fixed_Asm_8:
7671 case ARM::VST3dWB_fixed_Asm_16:
7672 case ARM::VST3dWB_fixed_Asm_32:
7673 case ARM::VST3qWB_fixed_Asm_8:
7674 case ARM::VST3qWB_fixed_Asm_16:
7675 case ARM::VST3qWB_fixed_Asm_32: {
7678 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7679 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7680 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7681 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7682 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7683 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7684 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7686 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7688 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7689 TmpInst.addOperand(Inst.getOperand(4));
7694 case ARM::VST3dWB_register_Asm_8:
7695 case ARM::VST3dWB_register_Asm_16:
7696 case ARM::VST3dWB_register_Asm_32:
7697 case ARM::VST3qWB_register_Asm_8:
7698 case ARM::VST3qWB_register_Asm_16:
7699 case ARM::VST3qWB_register_Asm_32: {
7702 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7703 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7704 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7705 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7706 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7707 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7708 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7710 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7712 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7713 TmpInst.addOperand(Inst.getOperand(5));
7718 // VST4 multiple 3-element structure instructions.
7719 case ARM::VST4dAsm_8:
7720 case ARM::VST4dAsm_16:
7721 case ARM::VST4dAsm_32:
7722 case ARM::VST4qAsm_8:
7723 case ARM::VST4qAsm_16:
7724 case ARM::VST4qAsm_32: {
7727 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7728 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7729 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7730 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7731 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7733 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7735 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7737 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7738 TmpInst.addOperand(Inst.getOperand(4));
7743 case ARM::VST4dWB_fixed_Asm_8:
7744 case ARM::VST4dWB_fixed_Asm_16:
7745 case ARM::VST4dWB_fixed_Asm_32:
7746 case ARM::VST4qWB_fixed_Asm_8:
7747 case ARM::VST4qWB_fixed_Asm_16:
7748 case ARM::VST4qWB_fixed_Asm_32: {
7751 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7752 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7753 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7754 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7755 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7756 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7757 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7759 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7761 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7763 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7764 TmpInst.addOperand(Inst.getOperand(4));
7769 case ARM::VST4dWB_register_Asm_8:
7770 case ARM::VST4dWB_register_Asm_16:
7771 case ARM::VST4dWB_register_Asm_32:
7772 case ARM::VST4qWB_register_Asm_8:
7773 case ARM::VST4qWB_register_Asm_16:
7774 case ARM::VST4qWB_register_Asm_32: {
7777 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7778 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7779 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7780 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7781 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7782 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7783 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7785 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7787 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7789 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7790 TmpInst.addOperand(Inst.getOperand(5));
7795 // Handle encoding choice for the shift-immediate instructions.
7798 case ARM::t2ASRri: {
7799 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7800 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7801 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7802 !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7803 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7805 switch (Inst.getOpcode()) {
7806 default: llvm_unreachable("unexpected opcode");
7807 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7808 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7809 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7811 // The Thumb1 operands aren't in the same order. Awesome, eh?
7813 TmpInst.setOpcode(NewOpc);
7814 TmpInst.addOperand(Inst.getOperand(0));
7815 TmpInst.addOperand(Inst.getOperand(5));
7816 TmpInst.addOperand(Inst.getOperand(1));
7817 TmpInst.addOperand(Inst.getOperand(2));
7818 TmpInst.addOperand(Inst.getOperand(3));
7819 TmpInst.addOperand(Inst.getOperand(4));
7826 // Handle the Thumb2 mode MOV complex aliases.
7828 case ARM::t2MOVSsr: {
7829 // Which instruction to expand to depends on the CCOut operand and
7830 // whether we're in an IT block if the register operands are low
7832 bool isNarrow = false;
7833 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7834 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7835 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7836 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7837 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7841 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7842 default: llvm_unreachable("unexpected opcode!");
7843 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7844 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7845 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7846 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7848 TmpInst.setOpcode(newOpc);
7849 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7851 TmpInst.addOperand(MCOperand::CreateReg(
7852 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7853 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7854 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7855 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7856 TmpInst.addOperand(Inst.getOperand(5));
7858 TmpInst.addOperand(MCOperand::CreateReg(
7859 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7864 case ARM::t2MOVSsi: {
7865 // Which instruction to expand to depends on the CCOut operand and
7866 // whether we're in an IT block if the register operands are low
7868 bool isNarrow = false;
7869 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7870 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7871 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7875 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7876 default: llvm_unreachable("unexpected opcode!");
7877 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7878 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7879 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7880 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7881 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7883 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7884 if (Amount == 32) Amount = 0;
7885 TmpInst.setOpcode(newOpc);
7886 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7888 TmpInst.addOperand(MCOperand::CreateReg(
7889 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7890 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7891 if (newOpc != ARM::t2RRX)
7892 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7893 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7894 TmpInst.addOperand(Inst.getOperand(4));
7896 TmpInst.addOperand(MCOperand::CreateReg(
7897 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7901 // Handle the ARM mode MOV complex aliases.
7906 ARM_AM::ShiftOpc ShiftTy;
7907 switch(Inst.getOpcode()) {
7908 default: llvm_unreachable("unexpected opcode!");
7909 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7910 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7911 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7912 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7914 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7916 TmpInst.setOpcode(ARM::MOVsr);
7917 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7918 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7919 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7920 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7921 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7922 TmpInst.addOperand(Inst.getOperand(4));
7923 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7931 ARM_AM::ShiftOpc ShiftTy;
7932 switch(Inst.getOpcode()) {
7933 default: llvm_unreachable("unexpected opcode!");
7934 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7935 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7936 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7937 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7939 // A shift by zero is a plain MOVr, not a MOVsi.
7940 unsigned Amt = Inst.getOperand(2).getImm();
7941 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7942 // A shift by 32 should be encoded as 0 when permitted
7943 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7945 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7947 TmpInst.setOpcode(Opc);
7948 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7949 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7950 if (Opc == ARM::MOVsi)
7951 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7952 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7953 TmpInst.addOperand(Inst.getOperand(4));
7954 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7959 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7961 TmpInst.setOpcode(ARM::MOVsi);
7962 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7963 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7964 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7965 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7966 TmpInst.addOperand(Inst.getOperand(3));
7967 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7971 case ARM::t2LDMIA_UPD: {
7972 // If this is a load of a single register, then we should use
7973 // a post-indexed LDR instruction instead, per the ARM ARM.
7974 if (Inst.getNumOperands() != 5)
7977 TmpInst.setOpcode(ARM::t2LDR_POST);
7978 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7979 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7980 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7981 TmpInst.addOperand(MCOperand::CreateImm(4));
7982 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7983 TmpInst.addOperand(Inst.getOperand(3));
7987 case ARM::t2STMDB_UPD: {
7988 // If this is a store of a single register, then we should use
7989 // a pre-indexed STR instruction instead, per the ARM ARM.
7990 if (Inst.getNumOperands() != 5)
7993 TmpInst.setOpcode(ARM::t2STR_PRE);
7994 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7995 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7996 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7997 TmpInst.addOperand(MCOperand::CreateImm(-4));
7998 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7999 TmpInst.addOperand(Inst.getOperand(3));
8003 case ARM::LDMIA_UPD:
8004 // If this is a load of a single register via a 'pop', then we should use
8005 // a post-indexed LDR instruction instead, per the ARM ARM.
8006 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8007 Inst.getNumOperands() == 5) {
8009 TmpInst.setOpcode(ARM::LDR_POST_IMM);
8010 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8011 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8012 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8013 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
8014 TmpInst.addOperand(MCOperand::CreateImm(4));
8015 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8016 TmpInst.addOperand(Inst.getOperand(3));
8021 case ARM::STMDB_UPD:
8022 // If this is a store of a single register via a 'push', then we should use
8023 // a pre-indexed STR instruction instead, per the ARM ARM.
8024 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8025 Inst.getNumOperands() == 5) {
8027 TmpInst.setOpcode(ARM::STR_PRE_IMM);
8028 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8029 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8030 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8031 TmpInst.addOperand(MCOperand::CreateImm(-4));
8032 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8033 TmpInst.addOperand(Inst.getOperand(3));
8037 case ARM::t2ADDri12:
8038 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8039 // mnemonic was used (not "addw"), encoding T3 is preferred.
8040 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8041 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8043 Inst.setOpcode(ARM::t2ADDri);
8044 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8046 case ARM::t2SUBri12:
8047 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8048 // mnemonic was used (not "subw"), encoding T3 is preferred.
8049 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8050 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8052 Inst.setOpcode(ARM::t2SUBri);
8053 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8056 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8057 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8058 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8059 // to encoding T1 if <Rd> is omitted."
8060 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8061 Inst.setOpcode(ARM::tADDi3);
8066 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8067 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8068 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8069 // to encoding T1 if <Rd> is omitted."
8070 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8071 Inst.setOpcode(ARM::tSUBi3);
8076 case ARM::t2SUBri: {
8077 // If the destination and first source operand are the same, and
8078 // the flags are compatible with the current IT status, use encoding T2
8079 // instead of T3. For compatibility with the system 'as'. Make sure the
8080 // wide encoding wasn't explicit.
8081 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8082 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8083 (unsigned)Inst.getOperand(2).getImm() > 255 ||
8084 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8085 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8086 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8087 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8090 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8091 ARM::tADDi8 : ARM::tSUBi8);
8092 TmpInst.addOperand(Inst.getOperand(0));
8093 TmpInst.addOperand(Inst.getOperand(5));
8094 TmpInst.addOperand(Inst.getOperand(0));
8095 TmpInst.addOperand(Inst.getOperand(2));
8096 TmpInst.addOperand(Inst.getOperand(3));
8097 TmpInst.addOperand(Inst.getOperand(4));
8101 case ARM::t2ADDrr: {
8102 // If the destination and first source operand are the same, and
8103 // there's no setting of the flags, use encoding T2 instead of T3.
8104 // Note that this is only for ADD, not SUB. This mirrors the system
8105 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
8106 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8107 Inst.getOperand(5).getReg() != 0 ||
8108 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8109 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8112 TmpInst.setOpcode(ARM::tADDhirr);
8113 TmpInst.addOperand(Inst.getOperand(0));
8114 TmpInst.addOperand(Inst.getOperand(0));
8115 TmpInst.addOperand(Inst.getOperand(2));
8116 TmpInst.addOperand(Inst.getOperand(3));
8117 TmpInst.addOperand(Inst.getOperand(4));
8121 case ARM::tADDrSP: {
8122 // If the non-SP source operand and the destination operand are not the
8123 // same, we need to use the 32-bit encoding if it's available.
8124 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8125 Inst.setOpcode(ARM::t2ADDrr);
8126 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8132 // A Thumb conditional branch outside of an IT block is a tBcc.
8133 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8134 Inst.setOpcode(ARM::tBcc);
8139 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8140 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8141 Inst.setOpcode(ARM::t2Bcc);
8146 // If the conditional is AL or we're in an IT block, we really want t2B.
8147 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8148 Inst.setOpcode(ARM::t2B);
8153 // If the conditional is AL, we really want tB.
8154 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8155 Inst.setOpcode(ARM::tB);
8160 // If the register list contains any high registers, or if the writeback
8161 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8162 // instead if we're in Thumb2. Otherwise, this should have generated
8163 // an error in validateInstruction().
8164 unsigned Rn = Inst.getOperand(0).getReg();
8165 bool hasWritebackToken =
8166 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8167 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8168 bool listContainsBase;
8169 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8170 (!listContainsBase && !hasWritebackToken) ||
8171 (listContainsBase && hasWritebackToken)) {
8172 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8173 assert (isThumbTwo());
8174 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8175 // If we're switching to the updating version, we need to insert
8176 // the writeback tied operand.
8177 if (hasWritebackToken)
8178 Inst.insert(Inst.begin(),
8179 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
8184 case ARM::tSTMIA_UPD: {
8185 // If the register list contains any high registers, we need to use
8186 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8187 // should have generated an error in validateInstruction().
8188 unsigned Rn = Inst.getOperand(0).getReg();
8189 bool listContainsBase;
8190 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8191 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8192 assert (isThumbTwo());
8193 Inst.setOpcode(ARM::t2STMIA_UPD);
8199 bool listContainsBase;
8200 // If the register list contains any high registers, we need to use
8201 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8202 // should have generated an error in validateInstruction().
8203 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8205 assert (isThumbTwo());
8206 Inst.setOpcode(ARM::t2LDMIA_UPD);
8207 // Add the base register and writeback operands.
8208 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8209 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8213 bool listContainsBase;
8214 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8216 assert (isThumbTwo());
8217 Inst.setOpcode(ARM::t2STMDB_UPD);
8218 // Add the base register and writeback operands.
8219 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8220 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8224 // If we can use the 16-bit encoding and the user didn't explicitly
8225 // request the 32-bit variant, transform it here.
8226 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8227 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8228 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8229 Inst.getOperand(4).getReg() == ARM::CPSR) ||
8230 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8231 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8232 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8233 // The operands aren't in the same order for tMOVi8...
8235 TmpInst.setOpcode(ARM::tMOVi8);
8236 TmpInst.addOperand(Inst.getOperand(0));
8237 TmpInst.addOperand(Inst.getOperand(4));
8238 TmpInst.addOperand(Inst.getOperand(1));
8239 TmpInst.addOperand(Inst.getOperand(2));
8240 TmpInst.addOperand(Inst.getOperand(3));
8247 // If we can use the 16-bit encoding and the user didn't explicitly
8248 // request the 32-bit variant, transform it here.
8249 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8250 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8251 Inst.getOperand(2).getImm() == ARMCC::AL &&
8252 Inst.getOperand(4).getReg() == ARM::CPSR &&
8253 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8254 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8255 // The operands aren't the same for tMOV[S]r... (no cc_out)
8257 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8258 TmpInst.addOperand(Inst.getOperand(0));
8259 TmpInst.addOperand(Inst.getOperand(1));
8260 TmpInst.addOperand(Inst.getOperand(2));
8261 TmpInst.addOperand(Inst.getOperand(3));
8271 // If we can use the 16-bit encoding and the user didn't explicitly
8272 // request the 32-bit variant, transform it here.
8273 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8274 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8275 Inst.getOperand(2).getImm() == 0 &&
8276 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8277 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8279 switch (Inst.getOpcode()) {
8280 default: llvm_unreachable("Illegal opcode!");
8281 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8282 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8283 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8284 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8286 // The operands aren't the same for thumb1 (no rotate operand).
8288 TmpInst.setOpcode(NewOpc);
8289 TmpInst.addOperand(Inst.getOperand(0));
8290 TmpInst.addOperand(Inst.getOperand(1));
8291 TmpInst.addOperand(Inst.getOperand(3));
8292 TmpInst.addOperand(Inst.getOperand(4));
8299 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8300 // rrx shifts and asr/lsr of #32 is encoded as 0
8301 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8303 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8304 // Shifting by zero is accepted as a vanilla 'MOVr'
8306 TmpInst.setOpcode(ARM::MOVr);
8307 TmpInst.addOperand(Inst.getOperand(0));
8308 TmpInst.addOperand(Inst.getOperand(1));
8309 TmpInst.addOperand(Inst.getOperand(3));
8310 TmpInst.addOperand(Inst.getOperand(4));
8311 TmpInst.addOperand(Inst.getOperand(5));
8324 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8325 if (SOpc == ARM_AM::rrx) return false;
8326 switch (Inst.getOpcode()) {
8327 default: llvm_unreachable("unexpected opcode!");
8328 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8329 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8330 case ARM::EORrsi: newOpc = ARM::EORrr; break;
8331 case ARM::BICrsi: newOpc = ARM::BICrr; break;
8332 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8333 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8335 // If the shift is by zero, use the non-shifted instruction definition.
8336 // The exception is for right shifts, where 0 == 32
8337 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8338 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8340 TmpInst.setOpcode(newOpc);
8341 TmpInst.addOperand(Inst.getOperand(0));
8342 TmpInst.addOperand(Inst.getOperand(1));
8343 TmpInst.addOperand(Inst.getOperand(2));
8344 TmpInst.addOperand(Inst.getOperand(4));
8345 TmpInst.addOperand(Inst.getOperand(5));
8346 TmpInst.addOperand(Inst.getOperand(6));
8354 // The mask bits for all but the first condition are represented as
8355 // the low bit of the condition code value implies 't'. We currently
8356 // always have 1 implies 't', so XOR toggle the bits if the low bit
8357 // of the condition code is zero.
8358 MCOperand &MO = Inst.getOperand(1);
8359 unsigned Mask = MO.getImm();
8360 unsigned OrigMask = Mask;
8361 unsigned TZ = countTrailingZeros(Mask);
8362 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8363 assert(Mask && TZ <= 3 && "illegal IT mask value!");
8364 Mask ^= (0xE << TZ) & 0xF;
8368 // Set up the IT block state according to the IT instruction we just
8370 assert(!inITBlock() && "nested IT blocks?!");
8371 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8372 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8373 ITState.CurPosition = 0;
8374 ITState.FirstCond = true;
8384 // Assemblers should use the narrow encodings of these instructions when permissible.
8385 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8386 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8387 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8388 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8389 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8390 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8391 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8394 switch (Inst.getOpcode()) {
8395 default: llvm_unreachable("unexpected opcode");
8396 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8397 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8398 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8399 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8400 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8401 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8404 TmpInst.setOpcode(NewOpc);
8405 TmpInst.addOperand(Inst.getOperand(0));
8406 TmpInst.addOperand(Inst.getOperand(5));
8407 TmpInst.addOperand(Inst.getOperand(1));
8408 TmpInst.addOperand(Inst.getOperand(2));
8409 TmpInst.addOperand(Inst.getOperand(3));
8410 TmpInst.addOperand(Inst.getOperand(4));
8421 // Assemblers should use the narrow encodings of these instructions when permissible.
8422 // These instructions are special in that they are commutable, so shorter encodings
8423 // are available more often.
8424 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8425 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8426 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8427 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8428 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8429 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8430 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8431 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8434 switch (Inst.getOpcode()) {
8435 default: llvm_unreachable("unexpected opcode");
8436 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8437 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8438 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8439 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8442 TmpInst.setOpcode(NewOpc);
8443 TmpInst.addOperand(Inst.getOperand(0));
8444 TmpInst.addOperand(Inst.getOperand(5));
8445 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8446 TmpInst.addOperand(Inst.getOperand(1));
8447 TmpInst.addOperand(Inst.getOperand(2));
8449 TmpInst.addOperand(Inst.getOperand(2));
8450 TmpInst.addOperand(Inst.getOperand(1));
8452 TmpInst.addOperand(Inst.getOperand(3));
8453 TmpInst.addOperand(Inst.getOperand(4));
8463 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8464 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8465 // suffix depending on whether they're in an IT block or not.
8466 unsigned Opc = Inst.getOpcode();
8467 const MCInstrDesc &MCID = MII.get(Opc);
8468 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8469 assert(MCID.hasOptionalDef() &&
8470 "optionally flag setting instruction missing optional def operand");
8471 assert(MCID.NumOperands == Inst.getNumOperands() &&
8472 "operand count mismatch!");
8473 // Find the optional-def operand (cc_out).
8476 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8479 // If we're parsing Thumb1, reject it completely.
8480 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8481 return Match_MnemonicFail;
8482 // If we're parsing Thumb2, which form is legal depends on whether we're
8484 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8486 return Match_RequiresITBlock;
8487 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8489 return Match_RequiresNotITBlock;
8491 // Some high-register supporting Thumb1 encodings only allow both registers
8492 // to be from r0-r7 when in Thumb2.
8493 else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
8494 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8495 isARMLowRegister(Inst.getOperand(2).getReg()))
8496 return Match_RequiresThumb2;
8497 // Others only require ARMv6 or later.
8498 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8499 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8500 isARMLowRegister(Inst.getOperand(1).getReg()))
8501 return Match_RequiresV6;
8502 return Match_Success;
8506 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8507 return true; // In an assembly source, no need to second-guess
8511 static const char *getSubtargetFeatureName(uint64_t Val);
8512 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8513 OperandVector &Operands,
8514 MCStreamer &Out, uint64_t &ErrorInfo,
8515 bool MatchingInlineAsm) {
8517 unsigned MatchResult;
8519 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8521 switch (MatchResult) {
8524 // Context sensitive operand constraints aren't handled by the matcher,
8525 // so check them here.
8526 if (validateInstruction(Inst, Operands)) {
8527 // Still progress the IT block, otherwise one wrong condition causes
8528 // nasty cascading errors.
8529 forwardITPosition();
8533 { // processInstruction() updates inITBlock state, we need to save it away
8534 bool wasInITBlock = inITBlock();
8536 // Some instructions need post-processing to, for example, tweak which
8537 // encoding is selected. Loop on it while changes happen so the
8538 // individual transformations can chain off each other. E.g.,
8539 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8540 while (processInstruction(Inst, Operands, Out))
8543 // Only after the instruction is fully processed, we can validate it
8544 if (wasInITBlock && hasV8Ops() && isThumb() &&
8545 !isV8EligibleForIT(&Inst)) {
8546 Warning(IDLoc, "deprecated instruction in IT block");
8550 // Only move forward at the very end so that everything in validate
8551 // and process gets a consistent answer about whether we're in an IT
8553 forwardITPosition();
8555 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8556 // doesn't actually encode.
8557 if (Inst.getOpcode() == ARM::ITasm)
8561 Out.EmitInstruction(Inst, STI);
8563 case Match_MissingFeature: {
8564 assert(ErrorInfo && "Unknown missing feature!");
8565 // Special case the error message for the very common case where only
8566 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8567 std::string Msg = "instruction requires:";
8569 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8570 if (ErrorInfo & Mask) {
8572 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8576 return Error(IDLoc, Msg);
8578 case Match_InvalidOperand: {
8579 SMLoc ErrorLoc = IDLoc;
8580 if (ErrorInfo != ~0ULL) {
8581 if (ErrorInfo >= Operands.size())
8582 return Error(IDLoc, "too few operands for instruction");
8584 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8585 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8588 return Error(ErrorLoc, "invalid operand for instruction");
8590 case Match_MnemonicFail:
8591 return Error(IDLoc, "invalid instruction",
8592 ((ARMOperand &)*Operands[0]).getLocRange());
8593 case Match_RequiresNotITBlock:
8594 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8595 case Match_RequiresITBlock:
8596 return Error(IDLoc, "instruction only valid inside IT block");
8597 case Match_RequiresV6:
8598 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8599 case Match_RequiresThumb2:
8600 return Error(IDLoc, "instruction variant requires Thumb2");
8601 case Match_ImmRange0_15: {
8602 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8603 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8604 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8606 case Match_ImmRange0_239: {
8607 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8608 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8609 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8611 case Match_AlignedMemoryRequiresNone:
8612 case Match_DupAlignedMemoryRequiresNone:
8613 case Match_AlignedMemoryRequires16:
8614 case Match_DupAlignedMemoryRequires16:
8615 case Match_AlignedMemoryRequires32:
8616 case Match_DupAlignedMemoryRequires32:
8617 case Match_AlignedMemoryRequires64:
8618 case Match_DupAlignedMemoryRequires64:
8619 case Match_AlignedMemoryRequires64or128:
8620 case Match_DupAlignedMemoryRequires64or128:
8621 case Match_AlignedMemoryRequires64or128or256:
8623 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8624 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8625 switch (MatchResult) {
8627 llvm_unreachable("Missing Match_Aligned type");
8628 case Match_AlignedMemoryRequiresNone:
8629 case Match_DupAlignedMemoryRequiresNone:
8630 return Error(ErrorLoc, "alignment must be omitted");
8631 case Match_AlignedMemoryRequires16:
8632 case Match_DupAlignedMemoryRequires16:
8633 return Error(ErrorLoc, "alignment must be 16 or omitted");
8634 case Match_AlignedMemoryRequires32:
8635 case Match_DupAlignedMemoryRequires32:
8636 return Error(ErrorLoc, "alignment must be 32 or omitted");
8637 case Match_AlignedMemoryRequires64:
8638 case Match_DupAlignedMemoryRequires64:
8639 return Error(ErrorLoc, "alignment must be 64 or omitted");
8640 case Match_AlignedMemoryRequires64or128:
8641 case Match_DupAlignedMemoryRequires64or128:
8642 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8643 case Match_AlignedMemoryRequires64or128or256:
8644 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8649 llvm_unreachable("Implement any new match types added!");
8652 /// parseDirective parses the arm specific directives
8653 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8654 const MCObjectFileInfo::Environment Format =
8655 getContext().getObjectFileInfo()->getObjectFileType();
8656 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8657 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
8659 StringRef IDVal = DirectiveID.getIdentifier();
8660 if (IDVal == ".word")
8661 return parseLiteralValues(4, DirectiveID.getLoc());
8662 else if (IDVal == ".short" || IDVal == ".hword")
8663 return parseLiteralValues(2, DirectiveID.getLoc());
8664 else if (IDVal == ".thumb")
8665 return parseDirectiveThumb(DirectiveID.getLoc());
8666 else if (IDVal == ".arm")
8667 return parseDirectiveARM(DirectiveID.getLoc());
8668 else if (IDVal == ".thumb_func")
8669 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8670 else if (IDVal == ".code")
8671 return parseDirectiveCode(DirectiveID.getLoc());
8672 else if (IDVal == ".syntax")
8673 return parseDirectiveSyntax(DirectiveID.getLoc());
8674 else if (IDVal == ".unreq")
8675 return parseDirectiveUnreq(DirectiveID.getLoc());
8676 else if (IDVal == ".fnend")
8677 return parseDirectiveFnEnd(DirectiveID.getLoc());
8678 else if (IDVal == ".cantunwind")
8679 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8680 else if (IDVal == ".personality")
8681 return parseDirectivePersonality(DirectiveID.getLoc());
8682 else if (IDVal == ".handlerdata")
8683 return parseDirectiveHandlerData(DirectiveID.getLoc());
8684 else if (IDVal == ".setfp")
8685 return parseDirectiveSetFP(DirectiveID.getLoc());
8686 else if (IDVal == ".pad")
8687 return parseDirectivePad(DirectiveID.getLoc());
8688 else if (IDVal == ".save")
8689 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8690 else if (IDVal == ".vsave")
8691 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8692 else if (IDVal == ".ltorg" || IDVal == ".pool")
8693 return parseDirectiveLtorg(DirectiveID.getLoc());
8694 else if (IDVal == ".even")
8695 return parseDirectiveEven(DirectiveID.getLoc());
8696 else if (IDVal == ".personalityindex")
8697 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8698 else if (IDVal == ".unwind_raw")
8699 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8700 else if (IDVal == ".movsp")
8701 return parseDirectiveMovSP(DirectiveID.getLoc());
8702 else if (IDVal == ".arch_extension")
8703 return parseDirectiveArchExtension(DirectiveID.getLoc());
8704 else if (IDVal == ".align")
8705 return parseDirectiveAlign(DirectiveID.getLoc());
8706 else if (IDVal == ".thumb_set")
8707 return parseDirectiveThumbSet(DirectiveID.getLoc());
8709 if (!IsMachO && !IsCOFF) {
8710 if (IDVal == ".arch")
8711 return parseDirectiveArch(DirectiveID.getLoc());
8712 else if (IDVal == ".cpu")
8713 return parseDirectiveCPU(DirectiveID.getLoc());
8714 else if (IDVal == ".eabi_attribute")
8715 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8716 else if (IDVal == ".fpu")
8717 return parseDirectiveFPU(DirectiveID.getLoc());
8718 else if (IDVal == ".fnstart")
8719 return parseDirectiveFnStart(DirectiveID.getLoc());
8720 else if (IDVal == ".inst")
8721 return parseDirectiveInst(DirectiveID.getLoc());
8722 else if (IDVal == ".inst.n")
8723 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8724 else if (IDVal == ".inst.w")
8725 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8726 else if (IDVal == ".object_arch")
8727 return parseDirectiveObjectArch(DirectiveID.getLoc());
8728 else if (IDVal == ".tlsdescseq")
8729 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8735 /// parseLiteralValues
8736 /// ::= .hword expression [, expression]*
8737 /// ::= .short expression [, expression]*
8738 /// ::= .word expression [, expression]*
8739 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8740 MCAsmParser &Parser = getParser();
8741 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8743 const MCExpr *Value;
8744 if (getParser().parseExpression(Value)) {
8745 Parser.eatToEndOfStatement();
8749 getParser().getStreamer().EmitValue(Value, Size);
8751 if (getLexer().is(AsmToken::EndOfStatement))
8754 // FIXME: Improve diagnostic.
8755 if (getLexer().isNot(AsmToken::Comma)) {
8756 Error(L, "unexpected token in directive");
8767 /// parseDirectiveThumb
8769 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8770 MCAsmParser &Parser = getParser();
8771 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8772 Error(L, "unexpected token in directive");
8778 Error(L, "target does not support Thumb mode");
8785 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8789 /// parseDirectiveARM
8791 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8792 MCAsmParser &Parser = getParser();
8793 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8794 Error(L, "unexpected token in directive");
8800 Error(L, "target does not support ARM mode");
8807 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8811 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8812 if (NextSymbolIsThumb) {
8813 getParser().getStreamer().EmitThumbFunc(Symbol);
8814 NextSymbolIsThumb = false;
8818 /// parseDirectiveThumbFunc
8819 /// ::= .thumbfunc symbol_name
8820 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8821 MCAsmParser &Parser = getParser();
8822 const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
8823 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8825 // Darwin asm has (optionally) function name after .thumb_func direction
8828 const AsmToken &Tok = Parser.getTok();
8829 if (Tok.isNot(AsmToken::EndOfStatement)) {
8830 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8831 Error(L, "unexpected token in .thumb_func directive");
8836 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8837 getParser().getStreamer().EmitThumbFunc(Func);
8838 Parser.Lex(); // Consume the identifier token.
8843 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8844 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8845 Parser.eatToEndOfStatement();
8849 NextSymbolIsThumb = true;
8853 /// parseDirectiveSyntax
8854 /// ::= .syntax unified | divided
8855 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8856 MCAsmParser &Parser = getParser();
8857 const AsmToken &Tok = Parser.getTok();
8858 if (Tok.isNot(AsmToken::Identifier)) {
8859 Error(L, "unexpected token in .syntax directive");
8863 StringRef Mode = Tok.getString();
8864 if (Mode == "unified" || Mode == "UNIFIED") {
8866 } else if (Mode == "divided" || Mode == "DIVIDED") {
8867 Error(L, "'.syntax divided' arm asssembly not supported");
8870 Error(L, "unrecognized syntax mode in .syntax directive");
8874 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8875 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8880 // TODO tell the MC streamer the mode
8881 // getParser().getStreamer().Emit???();
8885 /// parseDirectiveCode
8886 /// ::= .code 16 | 32
8887 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8888 MCAsmParser &Parser = getParser();
8889 const AsmToken &Tok = Parser.getTok();
8890 if (Tok.isNot(AsmToken::Integer)) {
8891 Error(L, "unexpected token in .code directive");
8894 int64_t Val = Parser.getTok().getIntVal();
8895 if (Val != 16 && Val != 32) {
8896 Error(L, "invalid operand to .code directive");
8901 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8902 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8909 Error(L, "target does not support Thumb mode");
8915 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8918 Error(L, "target does not support ARM mode");
8924 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8930 /// parseDirectiveReq
8931 /// ::= name .req registername
8932 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8933 MCAsmParser &Parser = getParser();
8934 Parser.Lex(); // Eat the '.req' token.
8936 SMLoc SRegLoc, ERegLoc;
8937 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8938 Parser.eatToEndOfStatement();
8939 Error(SRegLoc, "register name expected");
8943 // Shouldn't be anything else.
8944 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8945 Parser.eatToEndOfStatement();
8946 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8950 Parser.Lex(); // Consume the EndOfStatement
8952 if (!RegisterReqs.insert(std::make_pair(Name, Reg)).second) {
8953 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8960 /// parseDirectiveUneq
8961 /// ::= .unreq registername
8962 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8963 MCAsmParser &Parser = getParser();
8964 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8965 Parser.eatToEndOfStatement();
8966 Error(L, "unexpected input in .unreq directive.");
8969 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8970 Parser.Lex(); // Eat the identifier.
8974 /// parseDirectiveArch
8976 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8977 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8979 unsigned ID = StringSwitch<unsigned>(Arch)
8980 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8981 .Case(NAME, ARM::ID)
8982 #define ARM_ARCH_ALIAS(NAME, ID) \
8983 .Case(NAME, ARM::ID)
8984 #include "MCTargetDesc/ARMArchName.def"
8985 .Default(ARM::INVALID_ARCH);
8987 if (ID == ARM::INVALID_ARCH) {
8988 Error(L, "Unknown arch name");
8992 getTargetStreamer().emitArch(ID);
8996 /// parseDirectiveEabiAttr
8997 /// ::= .eabi_attribute int, int [, "str"]
8998 /// ::= .eabi_attribute Tag_name, int [, "str"]
8999 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9000 MCAsmParser &Parser = getParser();
9003 TagLoc = Parser.getTok().getLoc();
9004 if (Parser.getTok().is(AsmToken::Identifier)) {
9005 StringRef Name = Parser.getTok().getIdentifier();
9006 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9008 Error(TagLoc, "attribute name not recognised: " + Name);
9009 Parser.eatToEndOfStatement();
9014 const MCExpr *AttrExpr;
9016 TagLoc = Parser.getTok().getLoc();
9017 if (Parser.parseExpression(AttrExpr)) {
9018 Parser.eatToEndOfStatement();
9022 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9024 Error(TagLoc, "expected numeric constant");
9025 Parser.eatToEndOfStatement();
9029 Tag = CE->getValue();
9032 if (Parser.getTok().isNot(AsmToken::Comma)) {
9033 Error(Parser.getTok().getLoc(), "comma expected");
9034 Parser.eatToEndOfStatement();
9037 Parser.Lex(); // skip comma
9039 StringRef StringValue = "";
9040 bool IsStringValue = false;
9042 int64_t IntegerValue = 0;
9043 bool IsIntegerValue = false;
9045 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9046 IsStringValue = true;
9047 else if (Tag == ARMBuildAttrs::compatibility) {
9048 IsStringValue = true;
9049 IsIntegerValue = true;
9050 } else if (Tag < 32 || Tag % 2 == 0)
9051 IsIntegerValue = true;
9052 else if (Tag % 2 == 1)
9053 IsStringValue = true;
9055 llvm_unreachable("invalid tag type");
9057 if (IsIntegerValue) {
9058 const MCExpr *ValueExpr;
9059 SMLoc ValueExprLoc = Parser.getTok().getLoc();
9060 if (Parser.parseExpression(ValueExpr)) {
9061 Parser.eatToEndOfStatement();
9065 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9067 Error(ValueExprLoc, "expected numeric constant");
9068 Parser.eatToEndOfStatement();
9072 IntegerValue = CE->getValue();
9075 if (Tag == ARMBuildAttrs::compatibility) {
9076 if (Parser.getTok().isNot(AsmToken::Comma))
9077 IsStringValue = false;
9082 if (IsStringValue) {
9083 if (Parser.getTok().isNot(AsmToken::String)) {
9084 Error(Parser.getTok().getLoc(), "bad string constant");
9085 Parser.eatToEndOfStatement();
9089 StringValue = Parser.getTok().getStringContents();
9093 if (IsIntegerValue && IsStringValue) {
9094 assert(Tag == ARMBuildAttrs::compatibility);
9095 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9096 } else if (IsIntegerValue)
9097 getTargetStreamer().emitAttribute(Tag, IntegerValue);
9098 else if (IsStringValue)
9099 getTargetStreamer().emitTextAttribute(Tag, StringValue);
9103 /// parseDirectiveCPU
9105 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9106 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9107 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9109 if (!STI.isCPUStringValid(CPU)) {
9110 Error(L, "Unknown CPU name");
9114 STI.InitMCProcessorInfo(CPU, "");
9115 STI.InitCPUSchedModel(CPU);
9116 unsigned FB = ComputeAvailableFeatures(STI.getFeatureBits());
9117 setAvailableFeatures(FB);
9122 // FIXME: This is duplicated in getARMFPUFeatures() in
9123 // tools/clang/lib/Driver/Tools.cpp
9124 static const struct {
9126 const uint64_t Enabled;
9127 const uint64_t Disabled;
9129 {ARM::VFP, ARM::FeatureVFP2, ARM::FeatureNEON},
9130 {ARM::VFPV2, ARM::FeatureVFP2, ARM::FeatureNEON},
9131 {ARM::VFPV3, ARM::FeatureVFP3, ARM::FeatureNEON},
9132 {ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON},
9133 {ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON},
9134 {ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON},
9135 {ARM::FPV5_D16, ARM::FeatureFPARMv8 | ARM::FeatureD16,
9136 ARM::FeatureNEON | ARM::FeatureCrypto},
9137 {ARM::FP_ARMV8, ARM::FeatureFPARMv8,
9138 ARM::FeatureNEON | ARM::FeatureCrypto},
9139 {ARM::NEON, ARM::FeatureNEON, 0},
9140 {ARM::NEON_VFPV4, ARM::FeatureVFP4 | ARM::FeatureNEON, 0},
9141 {ARM::NEON_FP_ARMV8, ARM::FeatureFPARMv8 | ARM::FeatureNEON,
9142 ARM::FeatureCrypto},
9143 {ARM::CRYPTO_NEON_FP_ARMV8,
9144 ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, 0},
9145 {ARM::SOFTVFP, 0, 0},
9148 /// parseDirectiveFPU
9150 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9151 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9153 unsigned ID = StringSwitch<unsigned>(FPU)
9154 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
9155 #include "ARMFPUName.def"
9156 .Default(ARM::INVALID_FPU);
9158 if (ID == ARM::INVALID_FPU) {
9159 Error(L, "Unknown FPU name");
9163 for (const auto &Fpu : Fpus) {
9167 // Need to toggle features that should be on but are off and that
9168 // should off but are on.
9169 uint64_t Toggle = (Fpu.Enabled & ~STI.getFeatureBits()) |
9170 (Fpu.Disabled & STI.getFeatureBits());
9171 setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
9175 getTargetStreamer().emitFPU(ID);
9179 /// parseDirectiveFnStart
9181 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9182 if (UC.hasFnStart()) {
9183 Error(L, ".fnstart starts before the end of previous one");
9184 UC.emitFnStartLocNotes();
9188 // Reset the unwind directives parser state
9191 getTargetStreamer().emitFnStart();
9193 UC.recordFnStart(L);
9197 /// parseDirectiveFnEnd
9199 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9200 // Check the ordering of unwind directives
9201 if (!UC.hasFnStart()) {
9202 Error(L, ".fnstart must precede .fnend directive");
9206 // Reset the unwind directives parser state
9207 getTargetStreamer().emitFnEnd();
9213 /// parseDirectiveCantUnwind
9215 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9216 UC.recordCantUnwind(L);
9218 // Check the ordering of unwind directives
9219 if (!UC.hasFnStart()) {
9220 Error(L, ".fnstart must precede .cantunwind directive");
9223 if (UC.hasHandlerData()) {
9224 Error(L, ".cantunwind can't be used with .handlerdata directive");
9225 UC.emitHandlerDataLocNotes();
9228 if (UC.hasPersonality()) {
9229 Error(L, ".cantunwind can't be used with .personality directive");
9230 UC.emitPersonalityLocNotes();
9234 getTargetStreamer().emitCantUnwind();
9238 /// parseDirectivePersonality
9239 /// ::= .personality name
9240 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9241 MCAsmParser &Parser = getParser();
9242 bool HasExistingPersonality = UC.hasPersonality();
9244 UC.recordPersonality(L);
9246 // Check the ordering of unwind directives
9247 if (!UC.hasFnStart()) {
9248 Error(L, ".fnstart must precede .personality directive");
9251 if (UC.cantUnwind()) {
9252 Error(L, ".personality can't be used with .cantunwind directive");
9253 UC.emitCantUnwindLocNotes();
9256 if (UC.hasHandlerData()) {
9257 Error(L, ".personality must precede .handlerdata directive");
9258 UC.emitHandlerDataLocNotes();
9261 if (HasExistingPersonality) {
9262 Parser.eatToEndOfStatement();
9263 Error(L, "multiple personality directives");
9264 UC.emitPersonalityLocNotes();
9268 // Parse the name of the personality routine
9269 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9270 Parser.eatToEndOfStatement();
9271 Error(L, "unexpected input in .personality directive.");
9274 StringRef Name(Parser.getTok().getIdentifier());
9277 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
9278 getTargetStreamer().emitPersonality(PR);
9282 /// parseDirectiveHandlerData
9283 /// ::= .handlerdata
9284 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9285 UC.recordHandlerData(L);
9287 // Check the ordering of unwind directives
9288 if (!UC.hasFnStart()) {
9289 Error(L, ".fnstart must precede .personality directive");
9292 if (UC.cantUnwind()) {
9293 Error(L, ".handlerdata can't be used with .cantunwind directive");
9294 UC.emitCantUnwindLocNotes();
9298 getTargetStreamer().emitHandlerData();
9302 /// parseDirectiveSetFP
9303 /// ::= .setfp fpreg, spreg [, offset]
9304 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9305 MCAsmParser &Parser = getParser();
9306 // Check the ordering of unwind directives
9307 if (!UC.hasFnStart()) {
9308 Error(L, ".fnstart must precede .setfp directive");
9311 if (UC.hasHandlerData()) {
9312 Error(L, ".setfp must precede .handlerdata directive");
9317 SMLoc FPRegLoc = Parser.getTok().getLoc();
9318 int FPReg = tryParseRegister();
9320 Error(FPRegLoc, "frame pointer register expected");
9325 if (Parser.getTok().isNot(AsmToken::Comma)) {
9326 Error(Parser.getTok().getLoc(), "comma expected");
9329 Parser.Lex(); // skip comma
9332 SMLoc SPRegLoc = Parser.getTok().getLoc();
9333 int SPReg = tryParseRegister();
9335 Error(SPRegLoc, "stack pointer register expected");
9339 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
9340 Error(SPRegLoc, "register should be either $sp or the latest fp register");
9344 // Update the frame pointer register
9345 UC.saveFPReg(FPReg);
9349 if (Parser.getTok().is(AsmToken::Comma)) {
9350 Parser.Lex(); // skip comma
9352 if (Parser.getTok().isNot(AsmToken::Hash) &&
9353 Parser.getTok().isNot(AsmToken::Dollar)) {
9354 Error(Parser.getTok().getLoc(), "'#' expected");
9357 Parser.Lex(); // skip hash token.
9359 const MCExpr *OffsetExpr;
9360 SMLoc ExLoc = Parser.getTok().getLoc();
9362 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9363 Error(ExLoc, "malformed setfp offset");
9366 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9368 Error(ExLoc, "setfp offset must be an immediate");
9372 Offset = CE->getValue();
9375 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9376 static_cast<unsigned>(SPReg), Offset);
9382 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9383 MCAsmParser &Parser = getParser();
9384 // Check the ordering of unwind directives
9385 if (!UC.hasFnStart()) {
9386 Error(L, ".fnstart must precede .pad directive");
9389 if (UC.hasHandlerData()) {
9390 Error(L, ".pad must precede .handlerdata directive");
9395 if (Parser.getTok().isNot(AsmToken::Hash) &&
9396 Parser.getTok().isNot(AsmToken::Dollar)) {
9397 Error(Parser.getTok().getLoc(), "'#' expected");
9400 Parser.Lex(); // skip hash token.
9402 const MCExpr *OffsetExpr;
9403 SMLoc ExLoc = Parser.getTok().getLoc();
9405 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9406 Error(ExLoc, "malformed pad offset");
9409 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9411 Error(ExLoc, "pad offset must be an immediate");
9415 getTargetStreamer().emitPad(CE->getValue());
9419 /// parseDirectiveRegSave
9420 /// ::= .save { registers }
9421 /// ::= .vsave { registers }
9422 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9423 // Check the ordering of unwind directives
9424 if (!UC.hasFnStart()) {
9425 Error(L, ".fnstart must precede .save or .vsave directives");
9428 if (UC.hasHandlerData()) {
9429 Error(L, ".save or .vsave must precede .handlerdata directive");
9433 // RAII object to make sure parsed operands are deleted.
9434 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9436 // Parse the register list
9437 if (parseRegisterList(Operands))
9439 ARMOperand &Op = (ARMOperand &)*Operands[0];
9440 if (!IsVector && !Op.isRegList()) {
9441 Error(L, ".save expects GPR registers");
9444 if (IsVector && !Op.isDPRRegList()) {
9445 Error(L, ".vsave expects DPR registers");
9449 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9453 /// parseDirectiveInst
9454 /// ::= .inst opcode [, ...]
9455 /// ::= .inst.n opcode [, ...]
9456 /// ::= .inst.w opcode [, ...]
9457 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9458 MCAsmParser &Parser = getParser();
9470 Parser.eatToEndOfStatement();
9471 Error(Loc, "cannot determine Thumb instruction size, "
9472 "use inst.n/inst.w instead");
9477 Parser.eatToEndOfStatement();
9478 Error(Loc, "width suffixes are invalid in ARM mode");
9484 if (getLexer().is(AsmToken::EndOfStatement)) {
9485 Parser.eatToEndOfStatement();
9486 Error(Loc, "expected expression following directive");
9493 if (getParser().parseExpression(Expr)) {
9494 Error(Loc, "expected expression");
9498 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9500 Error(Loc, "expected constant expression");
9506 if (Value->getValue() > 0xffff) {
9507 Error(Loc, "inst.n operand is too big, use inst.w instead");
9512 if (Value->getValue() > 0xffffffff) {
9514 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9519 llvm_unreachable("only supported widths are 2 and 4");
9522 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9524 if (getLexer().is(AsmToken::EndOfStatement))
9527 if (getLexer().isNot(AsmToken::Comma)) {
9528 Error(Loc, "unexpected token in directive");
9539 /// parseDirectiveLtorg
9540 /// ::= .ltorg | .pool
9541 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9542 getTargetStreamer().emitCurrentConstantPool();
9546 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9547 const MCSection *Section = getStreamer().getCurrentSection().first;
9549 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9550 TokError("unexpected token in directive");
9555 getStreamer().InitSections(false);
9556 Section = getStreamer().getCurrentSection().first;
9559 assert(Section && "must have section to emit alignment");
9560 if (Section->UseCodeAlign())
9561 getStreamer().EmitCodeAlignment(2);
9563 getStreamer().EmitValueToAlignment(2);
9568 /// parseDirectivePersonalityIndex
9569 /// ::= .personalityindex index
9570 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9571 MCAsmParser &Parser = getParser();
9572 bool HasExistingPersonality = UC.hasPersonality();
9574 UC.recordPersonalityIndex(L);
9576 if (!UC.hasFnStart()) {
9577 Parser.eatToEndOfStatement();
9578 Error(L, ".fnstart must precede .personalityindex directive");
9581 if (UC.cantUnwind()) {
9582 Parser.eatToEndOfStatement();
9583 Error(L, ".personalityindex cannot be used with .cantunwind");
9584 UC.emitCantUnwindLocNotes();
9587 if (UC.hasHandlerData()) {
9588 Parser.eatToEndOfStatement();
9589 Error(L, ".personalityindex must precede .handlerdata directive");
9590 UC.emitHandlerDataLocNotes();
9593 if (HasExistingPersonality) {
9594 Parser.eatToEndOfStatement();
9595 Error(L, "multiple personality directives");
9596 UC.emitPersonalityLocNotes();
9600 const MCExpr *IndexExpression;
9601 SMLoc IndexLoc = Parser.getTok().getLoc();
9602 if (Parser.parseExpression(IndexExpression)) {
9603 Parser.eatToEndOfStatement();
9607 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9609 Parser.eatToEndOfStatement();
9610 Error(IndexLoc, "index must be a constant number");
9613 if (CE->getValue() < 0 ||
9614 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9615 Parser.eatToEndOfStatement();
9616 Error(IndexLoc, "personality routine index should be in range [0-3]");
9620 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9624 /// parseDirectiveUnwindRaw
9625 /// ::= .unwind_raw offset, opcode [, opcode...]
9626 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9627 MCAsmParser &Parser = getParser();
9628 if (!UC.hasFnStart()) {
9629 Parser.eatToEndOfStatement();
9630 Error(L, ".fnstart must precede .unwind_raw directives");
9634 int64_t StackOffset;
9636 const MCExpr *OffsetExpr;
9637 SMLoc OffsetLoc = getLexer().getLoc();
9638 if (getLexer().is(AsmToken::EndOfStatement) ||
9639 getParser().parseExpression(OffsetExpr)) {
9640 Error(OffsetLoc, "expected expression");
9641 Parser.eatToEndOfStatement();
9645 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9647 Error(OffsetLoc, "offset must be a constant");
9648 Parser.eatToEndOfStatement();
9652 StackOffset = CE->getValue();
9654 if (getLexer().isNot(AsmToken::Comma)) {
9655 Error(getLexer().getLoc(), "expected comma");
9656 Parser.eatToEndOfStatement();
9661 SmallVector<uint8_t, 16> Opcodes;
9665 SMLoc OpcodeLoc = getLexer().getLoc();
9666 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9667 Error(OpcodeLoc, "expected opcode expression");
9668 Parser.eatToEndOfStatement();
9672 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9674 Error(OpcodeLoc, "opcode value must be a constant");
9675 Parser.eatToEndOfStatement();
9679 const int64_t Opcode = OC->getValue();
9680 if (Opcode & ~0xff) {
9681 Error(OpcodeLoc, "invalid opcode");
9682 Parser.eatToEndOfStatement();
9686 Opcodes.push_back(uint8_t(Opcode));
9688 if (getLexer().is(AsmToken::EndOfStatement))
9691 if (getLexer().isNot(AsmToken::Comma)) {
9692 Error(getLexer().getLoc(), "unexpected token in directive");
9693 Parser.eatToEndOfStatement();
9700 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9706 /// parseDirectiveTLSDescSeq
9707 /// ::= .tlsdescseq tls-variable
9708 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9709 MCAsmParser &Parser = getParser();
9711 if (getLexer().isNot(AsmToken::Identifier)) {
9712 TokError("expected variable after '.tlsdescseq' directive");
9713 Parser.eatToEndOfStatement();
9717 const MCSymbolRefExpr *SRE =
9718 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9719 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9722 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9723 Error(Parser.getTok().getLoc(), "unexpected token");
9724 Parser.eatToEndOfStatement();
9728 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9732 /// parseDirectiveMovSP
9733 /// ::= .movsp reg [, #offset]
9734 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9735 MCAsmParser &Parser = getParser();
9736 if (!UC.hasFnStart()) {
9737 Parser.eatToEndOfStatement();
9738 Error(L, ".fnstart must precede .movsp directives");
9741 if (UC.getFPReg() != ARM::SP) {
9742 Parser.eatToEndOfStatement();
9743 Error(L, "unexpected .movsp directive");
9747 SMLoc SPRegLoc = Parser.getTok().getLoc();
9748 int SPReg = tryParseRegister();
9750 Parser.eatToEndOfStatement();
9751 Error(SPRegLoc, "register expected");
9755 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9756 Parser.eatToEndOfStatement();
9757 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9762 if (Parser.getTok().is(AsmToken::Comma)) {
9765 if (Parser.getTok().isNot(AsmToken::Hash)) {
9766 Error(Parser.getTok().getLoc(), "expected #constant");
9767 Parser.eatToEndOfStatement();
9772 const MCExpr *OffsetExpr;
9773 SMLoc OffsetLoc = Parser.getTok().getLoc();
9774 if (Parser.parseExpression(OffsetExpr)) {
9775 Parser.eatToEndOfStatement();
9776 Error(OffsetLoc, "malformed offset expression");
9780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9782 Parser.eatToEndOfStatement();
9783 Error(OffsetLoc, "offset must be an immediate constant");
9787 Offset = CE->getValue();
9790 getTargetStreamer().emitMovSP(SPReg, Offset);
9791 UC.saveFPReg(SPReg);
9796 /// parseDirectiveObjectArch
9797 /// ::= .object_arch name
9798 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9799 MCAsmParser &Parser = getParser();
9800 if (getLexer().isNot(AsmToken::Identifier)) {
9801 Error(getLexer().getLoc(), "unexpected token");
9802 Parser.eatToEndOfStatement();
9806 StringRef Arch = Parser.getTok().getString();
9807 SMLoc ArchLoc = Parser.getTok().getLoc();
9810 unsigned ID = StringSwitch<unsigned>(Arch)
9811 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9812 .Case(NAME, ARM::ID)
9813 #define ARM_ARCH_ALIAS(NAME, ID) \
9814 .Case(NAME, ARM::ID)
9815 #include "MCTargetDesc/ARMArchName.def"
9816 #undef ARM_ARCH_NAME
9817 #undef ARM_ARCH_ALIAS
9818 .Default(ARM::INVALID_ARCH);
9820 if (ID == ARM::INVALID_ARCH) {
9821 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9822 Parser.eatToEndOfStatement();
9826 getTargetStreamer().emitObjectArch(ID);
9828 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9829 Error(getLexer().getLoc(), "unexpected token");
9830 Parser.eatToEndOfStatement();
9836 /// parseDirectiveAlign
9838 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9839 // NOTE: if this is not the end of the statement, fall back to the target
9840 // agnostic handling for this directive which will correctly handle this.
9841 if (getLexer().isNot(AsmToken::EndOfStatement))
9844 // '.align' is target specifically handled to mean 2**2 byte alignment.
9845 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9846 getStreamer().EmitCodeAlignment(4, 0);
9848 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9853 /// parseDirectiveThumbSet
9854 /// ::= .thumb_set name, value
9855 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9856 MCAsmParser &Parser = getParser();
9859 if (Parser.parseIdentifier(Name)) {
9860 TokError("expected identifier after '.thumb_set'");
9861 Parser.eatToEndOfStatement();
9865 if (getLexer().isNot(AsmToken::Comma)) {
9866 TokError("expected comma after name '" + Name + "'");
9867 Parser.eatToEndOfStatement();
9872 const MCExpr *Value;
9873 if (Parser.parseExpression(Value)) {
9874 TokError("missing expression");
9875 Parser.eatToEndOfStatement();
9879 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9880 TokError("unexpected token");
9881 Parser.eatToEndOfStatement();
9886 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9887 getTargetStreamer().emitThumbSet(Alias, Value);
9891 /// Force static initialization.
9892 extern "C" void LLVMInitializeARMAsmParser() {
9893 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9894 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9895 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9896 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9899 #define GET_REGISTER_MATCHER
9900 #define GET_SUBTARGET_FEATURE_NAME
9901 #define GET_MATCHER_IMPLEMENTATION
9902 #include "ARMGenAsmMatcher.inc"
9904 static const struct {
9906 const unsigned ArchCheck;
9907 const uint64_t Features;
9909 { "crc", Feature_HasV8, ARM::FeatureCRC },
9910 { "crypto", Feature_HasV8,
9911 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9912 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9913 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9914 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9915 // FIXME: iWMMXT not supported
9916 { "iwmmxt", Feature_None, 0 },
9917 // FIXME: iWMMXT2 not supported
9918 { "iwmmxt2", Feature_None, 0 },
9919 // FIXME: Maverick not supported
9920 { "maverick", Feature_None, 0 },
9921 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9922 // FIXME: ARMv6-m OS Extensions feature not checked
9923 { "os", Feature_None, 0 },
9924 // FIXME: Also available in ARMv6-K
9925 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9926 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9927 // FIXME: Only available in A-class, isel not predicated
9928 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9929 // FIXME: xscale not supported
9930 { "xscale", Feature_None, 0 },
9933 /// parseDirectiveArchExtension
9934 /// ::= .arch_extension [no]feature
9935 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9936 MCAsmParser &Parser = getParser();
9938 if (getLexer().isNot(AsmToken::Identifier)) {
9939 Error(getLexer().getLoc(), "unexpected token");
9940 Parser.eatToEndOfStatement();
9944 StringRef Name = Parser.getTok().getString();
9945 SMLoc ExtLoc = Parser.getTok().getLoc();
9948 bool EnableFeature = true;
9949 if (Name.startswith_lower("no")) {
9950 EnableFeature = false;
9951 Name = Name.substr(2);
9954 for (const auto &Extension : Extensions) {
9955 if (Extension.Name != Name)
9958 if (!Extension.Features)
9959 report_fatal_error("unsupported architectural extension: " + Name);
9961 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
9962 Error(ExtLoc, "architectural extension '" + Name + "' is not "
9963 "allowed for the current base architecture");
9967 uint64_t ToggleFeatures = EnableFeature
9968 ? (~STI.getFeatureBits() & Extension.Features)
9969 : ( STI.getFeatureBits() & Extension.Features);
9971 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
9972 setAvailableFeatures(Features);
9976 Error(ExtLoc, "unknown architectural extension: " + Name);
9977 Parser.eatToEndOfStatement();
9981 // Define this matcher function after the auto-generated include so we
9982 // have the match class enum definitions.
9983 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
9985 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
9986 // If the kind is a token for a literal immediate, check if our asm
9987 // operand matches. This is for InstAliases which have a fixed-value
9988 // immediate in the syntax.
9993 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
9994 if (CE->getValue() == 0)
9995 return Match_Success;
10000 const MCExpr *SOExpr = Op.getImm();
10002 if (!SOExpr->EvaluateAsAbsolute(Value))
10003 return Match_Success;
10004 assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
10005 "expression value must be representable in 32 bits");
10010 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10011 return Match_Success;
10014 return Match_InvalidOperand;