1 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// ARM target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "armtti"
19 #include "ARMTargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetLowering.h"
25 // Declare the pass initialization routine locally as target-specific passes
26 // don't havve a target-wide initialization entry point, and so we rely on the
27 // pass constructor initialization.
29 void initializeARMTTIPass(PassRegistry &);
34 class ARMTTI : public ImmutablePass, public TargetTransformInfo {
35 const ARMBaseTargetMachine *TM;
36 const ARMSubtarget *ST;
38 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
39 /// are set if the result needs to be inserted and/or extracted from vectors.
40 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
43 ARMTTI() : ImmutablePass(ID), TM(0), ST(0) {
44 llvm_unreachable("This pass cannot be directly constructed");
47 ARMTTI(const ARMBaseTargetMachine *TM)
48 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()) {
49 initializeARMTTIPass(*PassRegistry::getPassRegistry());
52 virtual void initializePass() {
56 virtual void finalizePass() {
60 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
61 TargetTransformInfo::getAnalysisUsage(AU);
64 /// Pass identification.
67 /// Provide necessary pointer adjustments for the two base classes.
68 virtual void *getAdjustedAnalysisPointer(const void *ID) {
69 if (ID == &TargetTransformInfo::ID)
70 return (TargetTransformInfo*)this;
74 /// \name Scalar TTI Implementations
77 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
82 /// \name Vector TTI Implementations
85 unsigned getNumberOfRegisters(bool Vector) const {
92 if (ST->isThumb1Only())
97 unsigned getMaximumUnrollFactor() const {
98 // These are out of order CPUs:
99 if (ST->isCortexA15() || ST->isSwift())
107 } // end anonymous namespace
109 INITIALIZE_AG_PASS(ARMTTI, TargetTransformInfo, "armtti",
110 "ARM Target Transform Info", true, true, false)
114 llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
115 return new ARMTTI(TM);
119 unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
120 assert(Ty->isIntegerTy());
122 unsigned Bits = Ty->getPrimitiveSizeInBits();
123 if (Bits == 0 || Bits > 32)
126 int32_t SImmVal = Imm.getSExtValue();
127 uint32_t ZImmVal = Imm.getZExtValue();
128 if (!ST->isThumb()) {
129 if ((SImmVal >= 0 && SImmVal < 65536) ||
130 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
131 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
133 return ST->hasV6T2Ops() ? 2 : 3;
134 } else if (ST->isThumb2()) {
135 if ((SImmVal >= 0 && SImmVal < 65536) ||
136 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
137 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
139 return ST->hasV6T2Ops() ? 2 : 3;
141 if (SImmVal >= 0 && SImmVal < 256)
143 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
145 // Load from constantpool.