1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "ARMFrameLowering.h"
18 #include "ARMISelLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMJITInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "Thumb1FrameLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
26 #include "llvm/ADT/OwningPtr.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/Target/TargetMachine.h"
33 class ARMBaseTargetMachine : public LLVMTargetMachine {
35 ARMSubtarget Subtarget;
38 InstrItineraryData InstrItins;
41 ARMBaseTargetMachine(const Target &T, StringRef TT,
42 StringRef CPU, StringRef FS,
43 const TargetOptions &Options,
44 Reloc::Model RM, CodeModel::Model CM,
48 ARMJITInfo *getJITInfo() override { return &JITInfo; }
49 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
50 const ARMTargetLowering *getTargetLowering() const override {
51 // Implemented by derived classes
52 llvm_unreachable("getTargetLowering not implemented");
54 const InstrItineraryData *getInstrItineraryData() const override {
58 /// \brief Register ARM analysis passes with a pass manager.
59 void addAnalysisPasses(PassManagerBase &PM) override;
61 // Pass Pipeline Configuration
62 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
64 bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
67 /// ARMTargetMachine - ARM target machine.
69 class ARMTargetMachine : public ARMBaseTargetMachine {
70 virtual void anchor();
71 ARMInstrInfo InstrInfo;
72 const DataLayout DL; // Calculates type size & alignment
73 ARMTargetLowering TLInfo;
74 ARMSelectionDAGInfo TSInfo;
75 ARMFrameLowering FrameLowering;
77 ARMTargetMachine(const Target &T, StringRef TT,
78 StringRef CPU, StringRef FS,
79 const TargetOptions &Options,
80 Reloc::Model RM, CodeModel::Model CM,
84 const ARMRegisterInfo *getRegisterInfo() const override {
85 return &InstrInfo.getRegisterInfo();
88 const ARMTargetLowering *getTargetLowering() const override {
92 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
95 const ARMFrameLowering *getFrameLowering() const override {
96 return &FrameLowering;
98 const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
99 const DataLayout *getDataLayout() const override { return &DL; }
102 /// ARMleTargetMachine - ARM little endian target machine.
104 class ARMleTargetMachine : public ARMTargetMachine {
105 virtual void anchor();
107 ARMleTargetMachine(const Target &T, StringRef TT,
108 StringRef CPU, StringRef FS, const TargetOptions &Options,
109 Reloc::Model RM, CodeModel::Model CM,
110 CodeGenOpt::Level OL);
113 /// ARMbeTargetMachine - ARM big endian target machine.
115 class ARMbeTargetMachine : public ARMTargetMachine {
116 virtual void anchor();
118 ARMbeTargetMachine(const Target &T, StringRef TT,
119 StringRef CPU, StringRef FS, const TargetOptions &Options,
120 Reloc::Model RM, CodeModel::Model CM,
121 CodeGenOpt::Level OL);
124 /// ThumbTargetMachine - Thumb target machine.
125 /// Due to the way architectures are handled, this represents both
126 /// Thumb-1 and Thumb-2.
128 class ThumbTargetMachine : public ARMBaseTargetMachine {
129 virtual void anchor();
130 // Either Thumb1InstrInfo or Thumb2InstrInfo.
131 OwningPtr<ARMBaseInstrInfo> InstrInfo;
132 const DataLayout DL; // Calculates type size & alignment
133 ARMTargetLowering TLInfo;
134 ARMSelectionDAGInfo TSInfo;
135 // Either Thumb1FrameLowering or ARMFrameLowering.
136 OwningPtr<ARMFrameLowering> FrameLowering;
138 ThumbTargetMachine(const Target &T, StringRef TT,
139 StringRef CPU, StringRef FS,
140 const TargetOptions &Options,
141 Reloc::Model RM, CodeModel::Model CM,
142 CodeGenOpt::Level OL,
145 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
146 const ARMBaseRegisterInfo *getRegisterInfo() const override {
147 return &InstrInfo->getRegisterInfo();
150 const ARMTargetLowering *getTargetLowering() const override {
154 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
158 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
159 const ARMBaseInstrInfo *getInstrInfo() const override {
160 return InstrInfo.get();
162 /// returns either Thumb1FrameLowering or ARMFrameLowering
163 const ARMFrameLowering *getFrameLowering() const override {
164 return FrameLowering.get();
166 const DataLayout *getDataLayout() const override { return &DL; }
169 /// ThumbleTargetMachine - Thumb little endian target machine.
171 class ThumbleTargetMachine : public ThumbTargetMachine {
172 virtual void anchor();
174 ThumbleTargetMachine(const Target &T, StringRef TT,
175 StringRef CPU, StringRef FS, const TargetOptions &Options,
176 Reloc::Model RM, CodeModel::Model CM,
177 CodeGenOpt::Level OL);
180 /// ThumbbeTargetMachine - Thumb big endian target machine.
182 class ThumbbeTargetMachine : public ThumbTargetMachine {
183 virtual void anchor();
185 ThumbbeTargetMachine(const Target &T, StringRef TT,
186 StringRef CPU, StringRef FS, const TargetOptions &Options,
187 Reloc::Model RM, CodeModel::Model CM,
188 CodeGenOpt::Level OL);
191 } // end namespace llvm