1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetData.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMFrameInfo.h"
21 #include "ARMJITInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMISelLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
26 #include "llvm/ADT/OwningPtr.h"
30 class ARMBaseTargetMachine : public LLVMTargetMachine {
32 ARMSubtarget Subtarget;
35 ARMFrameInfo FrameInfo;
37 InstrItineraryData InstrItins;
38 Reloc::Model DefRelocModel; // Reloc model before it's overridden.
41 ARMBaseTargetMachine(const Target &T, const std::string &TT,
42 const std::string &FS, bool isThumb);
44 virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; }
45 virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
46 virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
47 virtual const InstrItineraryData getInstrItineraryData() const {
51 // Pass Pipeline Configuration
52 virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
53 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55 virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
56 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
57 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
61 /// ARMTargetMachine - ARM target machine.
63 class ARMTargetMachine : public ARMBaseTargetMachine {
64 ARMInstrInfo InstrInfo;
65 const TargetData DataLayout; // Calculates type size & alignment
66 ARMTargetLowering TLInfo;
68 ARMTargetMachine(const Target &T, const std::string &TT,
69 const std::string &FS);
71 virtual const ARMRegisterInfo *getRegisterInfo() const {
72 return &InstrInfo.getRegisterInfo();
75 virtual ARMTargetLowering *getTargetLowering() const {
76 return const_cast<ARMTargetLowering*>(&TLInfo);
79 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
80 virtual const TargetData *getTargetData() const { return &DataLayout; }
83 /// ThumbTargetMachine - Thumb target machine.
84 /// Due to the way architectures are handled, this represents both
85 /// Thumb-1 and Thumb-2.
87 class ThumbTargetMachine : public ARMBaseTargetMachine {
88 // Either Thumb1InstrInfo or Thumb2InstrInfo.
89 OwningPtr<ARMBaseInstrInfo> InstrInfo;
90 const TargetData DataLayout; // Calculates type size & alignment
91 ARMTargetLowering TLInfo;
93 ThumbTargetMachine(const Target &T, const std::string &TT,
94 const std::string &FS);
96 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
97 virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
98 return &InstrInfo->getRegisterInfo();
101 virtual ARMTargetLowering *getTargetLowering() const {
102 return const_cast<ARMTargetLowering*>(&TLInfo);
105 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
106 virtual const ARMBaseInstrInfo *getInstrInfo() const {
107 return InstrInfo.get();
109 virtual const TargetData *getTargetData() const { return &DataLayout; }
112 } // end namespace llvm